?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
V4L/DVB (8471): cx23885: Reallocated the sram to avoid concurrent VIDB/C issues.
[linux-2.6/verdex.git] / drivers / media / video / cx23885 / cx23885-core.c
blob3ae04d6e1362bec0db5b2a80d075e8ff4db9998c
1 /*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
32
33 #include "cx23885.h"
34
35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
37 MODULE_LICENSE("GPL");
38
39 static unsigned int debug;
40 module_param(debug,int,0644);
41 MODULE_PARM_DESC(debug,"enable debug messages");
42
43 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44 module_param_array(card, int, NULL, 0444);
45 MODULE_PARM_DESC(card,"card type");
46
47 #define dprintk(level, fmt, arg...)\
48 do { if (debug >= level)\
49 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
50 } while (0)
51
52 static unsigned int cx23885_devcount;
53
54 static DEFINE_MUTEX(devlist);
55 LIST_HEAD(cx23885_devlist);
56
57 #define NO_SYNC_LINE (-1U)
58
59 /* FIXME, these allocations will change when
60 * analog arrives. The be reviewed.
61 * CX23887 Assumptions
62 * 1 line = 16 bytes of CDT
63 * cmds size = 80
64 * cdt size = 16 * linesize
65 * iqsize = 64
66 * maxlines = 6
67 *
68 * Address Space:
69 * 0x00000000 0x00008fff FIFO clusters
70 * 0x00010000 0x000104af Channel Management Data Structures
71 * 0x000104b0 0x000104ff Free
72 * 0x00010500 0x000108bf 15 channels * iqsize
73 * 0x000108c0 0x000108ff Free
74 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
75 * 15 channels * (iqsize + (maxlines * linesize))
76 * 0x00010ea0 0x00010xxx Free
77 */
78
79 static struct sram_channel cx23887_sram_channels[] = {
80 [SRAM_CH01] = {
81 .name = "VID A",
82 .cmds_start = 0x10000,
83 .ctrl_start = 0x10380,
84 .cdt = 0x104c0,
85 .fifo_start = 0x40,
86 .fifo_size = 0x2800,
87 .ptr1_reg = DMA1_PTR1,
88 .ptr2_reg = DMA1_PTR2,
89 .cnt1_reg = DMA1_CNT1,
90 .cnt2_reg = DMA1_CNT2,
91 },
92 [SRAM_CH02] = {
93 .name = "ch2",
94 .cmds_start = 0x0,
95 .ctrl_start = 0x0,
96 .cdt = 0x0,
97 .fifo_start = 0x0,
98 .fifo_size = 0x0,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
103 },
104 [SRAM_CH03] = {
105 .name = "TS1 B",
106 .cmds_start = 0x100A0,
107 .ctrl_start = 0x10400,
108 .cdt = 0x10580,
109 .fifo_start = 0x5000,
110 .fifo_size = 0x1000,
111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
115 },
116 [SRAM_CH04] = {
117 .name = "ch4",
118 .cmds_start = 0x0,
119 .ctrl_start = 0x0,
120 .cdt = 0x0,
121 .fifo_start = 0x0,
122 .fifo_size = 0x0,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
127 },
128 [SRAM_CH05] = {
129 .name = "ch5",
130 .cmds_start = 0x0,
131 .ctrl_start = 0x0,
132 .cdt = 0x0,
133 .fifo_start = 0x0,
134 .fifo_size = 0x0,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
139 },
140 [SRAM_CH06] = {
141 .name = "TS2 C",
142 .cmds_start = 0x10140,
143 .ctrl_start = 0x10440,
144 .cdt = 0x105e0,
145 .fifo_start = 0x6000,
146 .fifo_size = 0x1000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
151 },
152 [SRAM_CH07] = {
153 .name = "ch7",
154 .cmds_start = 0x0,
155 .ctrl_start = 0x0,
156 .cdt = 0x0,
157 .fifo_start = 0x0,
158 .fifo_size = 0x0,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
163 },
164 [SRAM_CH08] = {
165 .name = "ch8",
166 .cmds_start = 0x0,
167 .ctrl_start = 0x0,
168 .cdt = 0x0,
169 .fifo_start = 0x0,
170 .fifo_size = 0x0,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
175 },
176 [SRAM_CH09] = {
177 .name = "ch9",
178 .cmds_start = 0x0,
179 .ctrl_start = 0x0,
180 .cdt = 0x0,
181 .fifo_start = 0x0,
182 .fifo_size = 0x0,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
187 },
188 };
189
190 static int cx23885_risc_decode(u32 risc)
191 {
192 static char *instr[16] = {
193 [RISC_SYNC >> 28] = "sync",
194 [RISC_WRITE >> 28] = "write",
195 [RISC_WRITEC >> 28] = "writec",
196 [RISC_READ >> 28] = "read",
197 [RISC_READC >> 28] = "readc",
198 [RISC_JUMP >> 28] = "jump",
199 [RISC_SKIP >> 28] = "skip",
200 [RISC_WRITERM >> 28] = "writerm",
201 [RISC_WRITECM >> 28] = "writecm",
202 [RISC_WRITECR >> 28] = "writecr",
203 };
204 static int incr[16] = {
205 [RISC_WRITE >> 28] = 3,
206 [RISC_JUMP >> 28] = 3,
207 [RISC_SKIP >> 28] = 1,
208 [RISC_SYNC >> 28] = 1,
209 [RISC_WRITERM >> 28] = 3,
210 [RISC_WRITECM >> 28] = 3,
211 [RISC_WRITECR >> 28] = 4,
212 };
213 static char *bits[] = {
214 "12", "13", "14", "resync",
215 "cnt0", "cnt1", "18", "19",
216 "20", "21", "22", "23",
217 "irq1", "irq2", "eol", "sol",
218 };
219 int i;
220
221 printk("0x%08x [ %s", risc,
222 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
223 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
224 if (risc & (1 << (i + 12)))
225 printk(" %s", bits[i]);
226 printk(" count=%d ]\n", risc & 0xfff);
227 return incr[risc >> 28] ? incr[risc >> 28] : 1;
228 }
229
230 void cx23885_wakeup(struct cx23885_tsport *port,
231 struct cx23885_dmaqueue *q, u32 count)
232 {
233 struct cx23885_dev *dev = port->dev;
234 struct cx23885_buffer *buf;
235 int bc;
236
237 for (bc = 0;; bc++) {
238 if (list_empty(&q->active))
239 break;
240 buf = list_entry(q->active.next,
241 struct cx23885_buffer, vb.queue);
242
243 /* count comes from the hw and is is 16bit wide --
244 * this trick handles wrap-arounds correctly for
245 * up to 32767 buffers in flight... */
246 if ((s16) (count - buf->count) < 0)
247 break;
248
249 do_gettimeofday(&buf->vb.ts);
250 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
251 count, buf->count);
252 buf->vb.state = VIDEOBUF_DONE;
253 list_del(&buf->vb.queue);
254 wake_up(&buf->vb.done);
255 }
256 if (list_empty(&q->active)) {
257 del_timer(&q->timeout);
258 } else {
259 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
260 }
261 if (bc != 1)
262 printk("%s: %d buffers handled (should be 1)\n",
263 __func__, bc);
264 }
265
266 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
267 struct sram_channel *ch,
268 unsigned int bpl, u32 risc)
269 {
270 unsigned int i, lines;
271 u32 cdt;
272
273 if (ch->cmds_start == 0)
274 {
275 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
276 ch->name);
277 cx_write(ch->ptr1_reg, 0);
278 cx_write(ch->ptr2_reg, 0);
279 cx_write(ch->cnt2_reg, 0);
280 cx_write(ch->cnt1_reg, 0);
281 return 0;
282 } else {
283 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
284 ch->name);
285 }
286
287 bpl = (bpl + 7) & ~7; /* alignment */
288 cdt = ch->cdt;
289 lines = ch->fifo_size / bpl;
290 if (lines > 6)
291 lines = 6;
292 BUG_ON(lines < 2);
293
294 cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
295 cx_write(8 + 4, 8);
296 cx_write(8 + 8, 0);
297
298 /* write CDT */
299 for (i = 0; i < lines; i++) {
300 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
301 ch->fifo_start + bpl*i);
302 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
303 cx_write(cdt + 16*i + 4, 0);
304 cx_write(cdt + 16*i + 8, 0);
305 cx_write(cdt + 16*i + 12, 0);
306 }
307
308 /* write CMDS */
309 if (ch->jumponly)
310 cx_write(ch->cmds_start + 0, 8);
311 else
312 cx_write(ch->cmds_start + 0, risc);
313 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
314 cx_write(ch->cmds_start + 8, cdt);
315 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
316 cx_write(ch->cmds_start + 16, ch->ctrl_start);
317 if (ch->jumponly)
318 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
319 else
320 cx_write(ch->cmds_start + 20, 64 >> 2);
321 for (i = 24; i < 80; i += 4)
322 cx_write(ch->cmds_start + i, 0);
323
324 /* fill registers */
325 cx_write(ch->ptr1_reg, ch->fifo_start);
326 cx_write(ch->ptr2_reg, cdt);
327 cx_write(ch->cnt2_reg, (lines*16) >> 3);
328 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
329
330 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
331 dev->bridge,
332 ch->name,
333 bpl,
334 lines);
335
336 return 0;
337 }
338
339 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
340 struct sram_channel *ch)
341 {
342 static char *name[] = {
343 "init risc lo",
344 "init risc hi",
345 "cdt base",
346 "cdt size",
347 "iq base",
348 "iq size",
349 "risc pc lo",
350 "risc pc hi",
351 "iq wr ptr",
352 "iq rd ptr",
353 "cdt current",
354 "pci target lo",
355 "pci target hi",
356 "line / byte",
357 };
358 u32 risc;
359 unsigned int i, j, n;
360
361 printk("%s: %s - dma channel status dump\n",
362 dev->name, ch->name);
363 for (i = 0; i < ARRAY_SIZE(name); i++)
364 printk("%s: cmds: %-15s: 0x%08x\n",
365 dev->name, name[i],
366 cx_read(ch->cmds_start + 4*i));
367
368 for (i = 0; i < 4; i++) {
369 risc = cx_read(ch->cmds_start + 4 * (i + 14));
370 printk("%s: risc%d: ", dev->name, i);
371 cx23885_risc_decode(risc);
372 }
373 for (i = 0; i < (64 >> 2); i += n) {
374 risc = cx_read(ch->ctrl_start + 4 * i);
375 /* No consideration for bits 63-32 */
376
377 printk("%s: (0x%08x) iq %x: ", dev->name,
378 ch->ctrl_start + 4 * i, i);
379 n = cx23885_risc_decode(risc);
380 for (j = 1; j < n; j++) {
381 risc = cx_read(ch->ctrl_start + 4 * (i + j));
382 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
383 dev->name, i+j, risc, j);
384 }
385 }
386
387 printk("%s: fifo: 0x%08x -> 0x%x\n",
388 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
389 printk("%s: ctrl: 0x%08x -> 0x%x\n",
390 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
391 printk("%s: ptr1_reg: 0x%08x\n",
392 dev->name, cx_read(ch->ptr1_reg));
393 printk("%s: ptr2_reg: 0x%08x\n",
394 dev->name, cx_read(ch->ptr2_reg));
395 printk("%s: cnt1_reg: 0x%08x\n",
396 dev->name, cx_read(ch->cnt1_reg));
397 printk("%s: cnt2_reg: 0x%08x\n",
398 dev->name, cx_read(ch->cnt2_reg));
399 }
400
401 static void cx23885_risc_disasm(struct cx23885_tsport *port,
402 struct btcx_riscmem *risc)
403 {
404 struct cx23885_dev *dev = port->dev;
405 unsigned int i, j, n;
406
407 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
408 dev->name, risc->cpu, (unsigned long)risc->dma);
409 for (i = 0; i < (risc->size >> 2); i += n) {
410 printk("%s: %04d: ", dev->name, i);
411 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
412 for (j = 1; j < n; j++)
413 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
414 dev->name, i + j, risc->cpu[i + j], j);
415 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
416 break;
417 }
418 }
419
420 static void cx23885_shutdown(struct cx23885_dev *dev)
421 {
422 /* disable RISC controller */
423 cx_write(DEV_CNTRL2, 0);
424
425 /* Disable all IR activity */
426 cx_write(IR_CNTRL_REG, 0);
427
428 /* Disable Video A/B activity */
429 cx_write(VID_A_DMA_CTL, 0);
430 cx_write(VID_B_DMA_CTL, 0);
431 cx_write(VID_C_DMA_CTL, 0);
432
433 /* Disable Audio activity */
434 cx_write(AUD_INT_DMA_CTL, 0);
435 cx_write(AUD_EXT_DMA_CTL, 0);
436
437 /* Disable Serial port */
438 cx_write(UART_CTL, 0);
439
440 /* Disable Interrupts */
441 cx_write(PCI_INT_MSK, 0);
442 cx_write(VID_A_INT_MSK, 0);
443 cx_write(VID_B_INT_MSK, 0);
444 cx_write(VID_C_INT_MSK, 0);
445 cx_write(AUDIO_INT_INT_MSK, 0);
446 cx_write(AUDIO_EXT_INT_MSK, 0);
447
448 }
449
450 static void cx23885_reset(struct cx23885_dev *dev)
451 {
452 dprintk(1, "%s()\n", __func__);
453
454 cx23885_shutdown(dev);
455
456 cx_write(PCI_INT_STAT, 0xffffffff);
457 cx_write(VID_A_INT_STAT, 0xffffffff);
458 cx_write(VID_B_INT_STAT, 0xffffffff);
459 cx_write(VID_C_INT_STAT, 0xffffffff);
460 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
461 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
462 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
463 cx_write(PAD_CTRL, 0x00500300);
464
465 mdelay(100);
466
467 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
468 720*4, 0);
469 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
470 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
471 188*4, 0);
472 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
473 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
474 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
475 188*4, 0);
476 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
477 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
478 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
479
480 cx23885_gpio_setup(dev);
481 }
482
483
484 static int cx23885_pci_quirks(struct cx23885_dev *dev)
485 {
486 dprintk(1, "%s()\n", __func__);
487
488 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
489 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
490 * occur on the cx23887 bridge.
491 */
492 if(dev->bridge == CX23885_BRIDGE_885)
493 cx_clear(RDR_TLCTL0, 1 << 4);
494
495 return 0;
496 }
497
498 static int get_resources(struct cx23885_dev *dev)
499 {
500 if (request_mem_region(pci_resource_start(dev->pci,0),
501 pci_resource_len(dev->pci,0),
502 dev->name))
503 return 0;
504
505 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
506 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
507
508 return -EBUSY;
509 }
510
511 static void cx23885_timeout(unsigned long data);
512 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
513 u32 reg, u32 mask, u32 value);
514
515 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
516 {
517 dprintk(1, "%s(portno=%d)\n", __func__, portno);
518
519 /* Transport bus init dma queue - Common settings */
520 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
521 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
522 port->vld_misc_val = 0x0;
523 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
524
525 spin_lock_init(&port->slock);
526 port->dev = dev;
527 port->nr = portno;
528
529 INIT_LIST_HEAD(&port->mpegq.active);
530 INIT_LIST_HEAD(&port->mpegq.queued);
531 port->mpegq.timeout.function = cx23885_timeout;
532 port->mpegq.timeout.data = (unsigned long)port;
533 init_timer(&port->mpegq.timeout);
534
535 switch(portno) {
536 case 1:
537 port->reg_gpcnt = VID_B_GPCNT;
538 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
539 port->reg_dma_ctl = VID_B_DMA_CTL;
540 port->reg_lngth = VID_B_LNGTH;
541 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
542 port->reg_gen_ctrl = VID_B_GEN_CTL;
543 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
544 port->reg_sop_status = VID_B_SOP_STATUS;
545 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
546 port->reg_vld_misc = VID_B_VLD_MISC;
547 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
548 port->reg_src_sel = VID_B_SRC_SEL;
549 port->reg_ts_int_msk = VID_B_INT_MSK;
550 port->reg_ts_int_stat = VID_B_INT_STAT;
551 port->sram_chno = SRAM_CH03; /* VID_B */
552 port->pci_irqmask = 0x02; /* VID_B bit1 */
553 break;
554 case 2:
555 port->reg_gpcnt = VID_C_GPCNT;
556 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
557 port->reg_dma_ctl = VID_C_DMA_CTL;
558 port->reg_lngth = VID_C_LNGTH;
559 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
560 port->reg_gen_ctrl = VID_C_GEN_CTL;
561 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
562 port->reg_sop_status = VID_C_SOP_STATUS;
563 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
564 port->reg_vld_misc = VID_C_VLD_MISC;
565 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
566 port->reg_src_sel = 0;
567 port->reg_ts_int_msk = VID_C_INT_MSK;
568 port->reg_ts_int_stat = VID_C_INT_STAT;
569 port->sram_chno = SRAM_CH06; /* VID_C */
570 port->pci_irqmask = 0x04; /* VID_C bit2 */
571 break;
572 default:
573 BUG();
574 }
575
576 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
577 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
578
579 return 0;
580 }
581
582 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
583 {
584 switch (cx_read(RDR_CFG2) & 0xff) {
585 case 0x00:
586 /* cx23885 */
587 dev->hwrevision = 0xa0;
588 break;
589 case 0x01:
590 /* CX23885-12Z */
591 dev->hwrevision = 0xa1;
592 break;
593 case 0x02:
594 /* CX23885-13Z */
595 dev->hwrevision = 0xb0;
596 break;
597 case 0x03:
598 /* CX23888-22Z */
599 dev->hwrevision = 0xc0;
600 break;
601 case 0x0e:
602 /* CX23887-15Z */
603 dev->hwrevision = 0xc0;
604 case 0x0f:
605 /* CX23887-14Z */
606 dev->hwrevision = 0xb1;
607 break;
608 default:
609 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
610 __func__, dev->hwrevision);
611 }
612 if (dev->hwrevision)
613 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
614 __func__, dev->hwrevision);
615 else
616 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
617 __func__, dev->hwrevision);
618 }
619
620 static int cx23885_dev_setup(struct cx23885_dev *dev)
621 {
622 int i;
623
624 mutex_init(&dev->lock);
625
626 atomic_inc(&dev->refcount);
627
628 dev->nr = cx23885_devcount++;
629 dev->sram_channels = cx23887_sram_channels;
630 sprintf(dev->name, "cx23885[%d]", dev->nr);
631
632 mutex_lock(&devlist);
633 list_add_tail(&dev->devlist, &cx23885_devlist);
634 mutex_unlock(&devlist);
635
636 /* Configure the internal memory */
637 if(dev->pci->device == 0x8880) {
638 dev->bridge = CX23885_BRIDGE_887;
639 /* Apply a sensible clock frequency for the PCIe bridge */
640 dev->clk_freq = 25000000;
641 } else
642 if(dev->pci->device == 0x8852) {
643 dev->bridge = CX23885_BRIDGE_885;
644 /* Apply a sensible clock frequency for the PCIe bridge */
645 dev->clk_freq = 28000000;
646 } else
647 BUG();
648
649 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
650 __func__, dev->bridge);
651
652 /* board config */
653 dev->board = UNSET;
654 if (card[dev->nr] < cx23885_bcount)
655 dev->board = card[dev->nr];
656 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
657 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
658 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
659 dev->board = cx23885_subids[i].card;
660 if (UNSET == dev->board) {
661 dev->board = CX23885_BOARD_UNKNOWN;
662 cx23885_card_list(dev);
663 }
664
665 /* If the user specific a clk freq override, apply it */
666 if (cx23885_boards[dev->board].clk_freq > 0)
667 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
668
669 dev->pci_bus = dev->pci->bus->number;
670 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
671 dev->pci_irqmask = 0x001f00;
672
673 /* External Master 1 Bus */
674 dev->i2c_bus[0].nr = 0;
675 dev->i2c_bus[0].dev = dev;
676 dev->i2c_bus[0].reg_stat = I2C1_STAT;
677 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
678 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
679 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
680 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
681 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
682
683 /* External Master 2 Bus */
684 dev->i2c_bus[1].nr = 1;
685 dev->i2c_bus[1].dev = dev;
686 dev->i2c_bus[1].reg_stat = I2C2_STAT;
687 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
688 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
689 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
690 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
691 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
692
693 /* Internal Master 3 Bus */
694 dev->i2c_bus[2].nr = 2;
695 dev->i2c_bus[2].dev = dev;
696 dev->i2c_bus[2].reg_stat = I2C3_STAT;
697 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
698 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
699 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
700 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
701 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
702
703 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
704 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
705 cx23885_init_tsport(dev, &dev->ts1, 1);
706
707 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
708 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
709 cx23885_init_tsport(dev, &dev->ts2, 2);
710
711 if (get_resources(dev) < 0) {
712 printk(KERN_ERR "CORE %s No more PCIe resources for "
713 "subsystem: %04x:%04x\n",
714 dev->name, dev->pci->subsystem_vendor,
715 dev->pci->subsystem_device);
716
717 cx23885_devcount--;
718 return -ENODEV;
719 }
720
721 /* PCIe stuff */
722 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
723 pci_resource_len(dev->pci,0));
724
725 dev->bmmio = (u8 __iomem *)dev->lmmio;
726
727 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
728 dev->name, dev->pci->subsystem_vendor,
729 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
730 dev->board, card[dev->nr] == dev->board ?
731 "insmod option" : "autodetected");
732
733 cx23885_pci_quirks(dev);
734
735 /* Assume some sensible defaults */
736 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
737 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
738 dev->radio_type = cx23885_boards[dev->board].radio_type;
739 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
740
741 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
742 __func__, dev->tuner_type, dev->tuner_addr);
743 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
744 __func__, dev->radio_type, dev->radio_addr);
745
746 /* init hardware */
747 cx23885_reset(dev);
748
749 cx23885_i2c_register(&dev->i2c_bus[0]);
750 cx23885_i2c_register(&dev->i2c_bus[1]);
751 cx23885_i2c_register(&dev->i2c_bus[2]);
752 cx23885_card_setup(dev);
753 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
754 cx23885_ir_init(dev);
755
756 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
757 if (cx23885_video_register(dev) < 0) {
758 printk(KERN_ERR "%s() Failed to register analog "
759 "video adapters on VID_A\n", __func__);
760 }
761 }
762
763 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
764 if (cx23885_dvb_register(&dev->ts1) < 0) {
765 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
766 __func__);
767 }
768 } else
769 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
770 if (cx23885_417_register(dev) < 0) {
771 printk(KERN_ERR
772 "%s() Failed to register 417 on VID_B\n",
773 __func__);
774 }
775 }
776
777 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
778 if (cx23885_dvb_register(&dev->ts2) < 0) {
779 printk(KERN_ERR
780 "%s() Failed to register dvb on VID_C\n",
781 __func__);
782 }
783 } else
784 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
785 if (cx23885_417_register(dev) < 0) {
786 printk(KERN_ERR
787 "%s() Failed to register 417 on VID_C\n",
788 __func__);
789 }
790 }
791
792 cx23885_dev_checkrevision(dev);
793
794 return 0;
795 }
796
797 static void cx23885_dev_unregister(struct cx23885_dev *dev)
798 {
799 release_mem_region(pci_resource_start(dev->pci,0),
800 pci_resource_len(dev->pci,0));
801
802 if (!atomic_dec_and_test(&dev->refcount))
803 return;
804
805 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
806 cx23885_video_unregister(dev);
807
808 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
809 cx23885_dvb_unregister(&dev->ts1);
810
811 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
812 cx23885_417_unregister(dev);
813
814 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
815 cx23885_dvb_unregister(&dev->ts2);
816
817 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
818 cx23885_417_unregister(dev);
819
820 cx23885_i2c_unregister(&dev->i2c_bus[2]);
821 cx23885_i2c_unregister(&dev->i2c_bus[1]);
822 cx23885_i2c_unregister(&dev->i2c_bus[0]);
823
824 iounmap(dev->lmmio);
825 }
826
827 static __le32* cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
828 unsigned int offset, u32 sync_line,
829 unsigned int bpl, unsigned int padding,
830 unsigned int lines)
831 {
832 struct scatterlist *sg;
833 unsigned int line, todo;
834
835 /* sync instruction */
836 if (sync_line != NO_SYNC_LINE)
837 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
838
839 /* scan lines */
840 sg = sglist;
841 for (line = 0; line < lines; line++) {
842 while (offset && offset >= sg_dma_len(sg)) {
843 offset -= sg_dma_len(sg);
844 sg++;
845 }
846 if (bpl <= sg_dma_len(sg)-offset) {
847 /* fits into current chunk */
848 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
849 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
850 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
851 offset+=bpl;
852 } else {
853 /* scanline needs to be split */
854 todo = bpl;
855 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
856 (sg_dma_len(sg)-offset));
857 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
858 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
859 todo -= (sg_dma_len(sg)-offset);
860 offset = 0;
861 sg++;
862 while (todo > sg_dma_len(sg)) {
863 *(rp++)=cpu_to_le32(RISC_WRITE|
864 sg_dma_len(sg));
865 *(rp++)=cpu_to_le32(sg_dma_address(sg));
866 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
867 todo -= sg_dma_len(sg);
868 sg++;
869 }
870 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
871 *(rp++)=cpu_to_le32(sg_dma_address(sg));
872 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
873 offset += todo;
874 }
875 offset += padding;
876 }
877
878 return rp;
879 }
880
881 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
882 struct scatterlist *sglist, unsigned int top_offset,
883 unsigned int bottom_offset, unsigned int bpl,
884 unsigned int padding, unsigned int lines)
885 {
886 u32 instructions, fields;
887 __le32 *rp;
888 int rc;
889
890 fields = 0;
891 if (UNSET != top_offset)
892 fields++;
893 if (UNSET != bottom_offset)
894 fields++;
895
896 /* estimate risc mem: worst case is one write per page border +
897 one write per scan line + syncs + jump (all 2 dwords). Padding
898 can cause next bpl to start close to a page border. First DMA
899 region may be smaller than PAGE_SIZE */
900 /* write and jump need and extra dword */
901 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
902 instructions += 2;
903 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
904 return rc;
905
906 /* write risc instructions */
907 rp = risc->cpu;
908 if (UNSET != top_offset)
909 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
910 bpl, padding, lines);
911 if (UNSET != bottom_offset)
912 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
913 bpl, padding, lines);
914
915 /* save pointer to jmp instruction address */
916 risc->jmp = rp;
917 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
918 return 0;
919 }
920
921 static int cx23885_risc_databuffer(struct pci_dev *pci,
922 struct btcx_riscmem *risc,
923 struct scatterlist *sglist,
924 unsigned int bpl,
925 unsigned int lines)
926 {
927 u32 instructions;
928 __le32 *rp;
929 int rc;
930
931 /* estimate risc mem: worst case is one write per page border +
932 one write per scan line + syncs + jump (all 2 dwords). Here
933 there is no padding and no sync. First DMA region may be smaller
934 than PAGE_SIZE */
935 /* Jump and write need an extra dword */
936 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
937 instructions += 1;
938
939 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
940 return rc;
941
942 /* write risc instructions */
943 rp = risc->cpu;
944 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
945
946 /* save pointer to jmp instruction address */
947 risc->jmp = rp;
948 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
949 return 0;
950 }
951
952 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
953 u32 reg, u32 mask, u32 value)
954 {
955 __le32 *rp;
956 int rc;
957
958 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
959 return rc;
960
961 /* write risc instructions */
962 rp = risc->cpu;
963 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
964 *(rp++) = cpu_to_le32(reg);
965 *(rp++) = cpu_to_le32(value);
966 *(rp++) = cpu_to_le32(mask);
967 *(rp++) = cpu_to_le32(RISC_JUMP);
968 *(rp++) = cpu_to_le32(risc->dma);
969 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
970 return 0;
971 }
972
973 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
974 {
975 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
976
977 BUG_ON(in_interrupt());
978 videobuf_waiton(&buf->vb, 0, 0);
979 videobuf_dma_unmap(q, dma);
980 videobuf_dma_free(dma);
981 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
982 buf->vb.state = VIDEOBUF_NEEDS_INIT;
983 }
984
985 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
986 {
987 struct cx23885_dev *dev = port->dev;
988
989 dprintk(1, "%s() Register Dump\n", __func__);
990 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
991 cx_read(DEV_CNTRL2));
992 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
993 cx_read(PCI_INT_MSK));
994 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
995 cx_read(AUDIO_INT_INT_MSK));
996 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
997 cx_read(AUD_INT_DMA_CTL));
998 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
999 cx_read(AUDIO_EXT_INT_MSK));
1000 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
1001 cx_read(AUD_EXT_DMA_CTL));
1002 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
1003 cx_read(PAD_CTRL));
1004 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
1005 cx_read(ALT_PIN_OUT_SEL));
1006 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
1007 cx_read(GPIO2));
1008 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
1009 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1010 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
1011 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1012 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
1013 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1014 if (port->reg_src_sel)
1015 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
1016 port->reg_src_sel, cx_read(port->reg_src_sel));
1017 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
1018 port->reg_lngth, cx_read(port->reg_lngth));
1019 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
1020 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1021 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
1022 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1023 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
1024 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1025 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
1026 port->reg_sop_status, cx_read(port->reg_sop_status));
1027 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1028 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1029 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
1030 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1031 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
1032 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1033 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
1034 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1035 }
1036
1037 static int cx23885_start_dma(struct cx23885_tsport *port,
1038 struct cx23885_dmaqueue *q,
1039 struct cx23885_buffer *buf)
1040 {
1041 struct cx23885_dev *dev = port->dev;
1042 u32 reg;
1043
1044 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1045 buf->vb.width, buf->vb.height, buf->vb.field);
1046
1047 /* Stop the fifo and risc engine for this port */
1048 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1049
1050 /* setup fifo + format */
1051 cx23885_sram_channel_setup(dev,
1052 &dev->sram_channels[ port->sram_chno ],
1053 port->ts_packet_size, buf->risc.dma);
1054 if(debug > 5) {
1055 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1056 cx23885_risc_disasm(port, &buf->risc);
1057 }
1058
1059 /* write TS length to chip */
1060 cx_write(port->reg_lngth, buf->vb.width);
1061
1062 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1063 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1064 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1065 __func__,
1066 cx23885_boards[dev->board].portb,
1067 cx23885_boards[dev->board].portc );
1068 return -EINVAL;
1069 }
1070
1071 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1072 cx23885_av_clk(dev, 0);
1073
1074 udelay(100);
1075
1076 /* If the port supports SRC SELECT, configure it */
1077 if(port->reg_src_sel)
1078 cx_write(port->reg_src_sel, port->src_sel_val);
1079
1080 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1081 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1082 cx_write(port->reg_vld_misc, port->vld_misc_val);
1083 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1084 udelay(100);
1085
1086 // NOTE: this is 2 (reserved) for portb, does it matter?
1087 /* reset counter to zero */
1088 cx_write(port->reg_gpcnt_ctl, 3);
1089 q->count = 1;
1090
1091 /* Set VIDB pins to input */
1092 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1093 reg = cx_read(PAD_CTRL);
1094 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1095 cx_write(PAD_CTRL, reg);
1096 }
1097
1098 /* Set VIDC pins to input */
1099 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1100 reg = cx_read(PAD_CTRL);
1101 reg &= ~0x4; /* Clear TS2_SOP_OE */
1102 cx_write(PAD_CTRL, reg);
1103 }
1104
1105 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1106
1107 reg = cx_read(PAD_CTRL);
1108 reg = reg & ~0x1; /* Clear TS1_OE */
1109
1110 /* FIXME, bit 2 writing here is questionable */
1111 /* set TS1_SOP_OE and TS1_OE_HI */
1112 reg = reg | 0xa;
1113 cx_write(PAD_CTRL, reg);
1114
1115 /* FIXME and these two registers should be documented. */
1116 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1117 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1118 }
1119
1120 switch(dev->bridge) {
1121 case CX23885_BRIDGE_885:
1122 case CX23885_BRIDGE_887:
1123 /* enable irqs */
1124 dprintk(1, "%s() enabling TS int's and DMA\n", __func__ );
1125 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1126 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1127 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1128 break;
1129 default:
1130 BUG();
1131 }
1132
1133 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1134
1135 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1136 cx23885_av_clk(dev, 1);
1137
1138 if (debug > 4)
1139 cx23885_tsport_reg_dump(port);
1140
1141 return 0;
1142 }
1143
1144 static int cx23885_stop_dma(struct cx23885_tsport *port)
1145 {
1146 struct cx23885_dev *dev = port->dev;
1147 u32 reg;
1148
1149 dprintk(1, "%s()\n", __func__);
1150
1151 /* Stop interrupts and DMA */
1152 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1153 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1154
1155 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1156
1157 reg = cx_read(PAD_CTRL);
1158
1159 /* Set TS1_OE */
1160 reg = reg | 0x1;
1161
1162 /* clear TS1_SOP_OE and TS1_OE_HI */
1163 reg = reg & ~0xa;
1164 cx_write(PAD_CTRL, reg);
1165 cx_write(port->reg_src_sel, 0);
1166 cx_write(port->reg_gen_ctrl, 8);
1167
1168 }
1169
1170 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1171 cx23885_av_clk(dev, 0);
1172
1173 return 0;
1174 }
1175
1176 int cx23885_restart_queue(struct cx23885_tsport *port,
1177 struct cx23885_dmaqueue *q)
1178 {
1179 struct cx23885_dev *dev = port->dev;
1180 struct cx23885_buffer *buf;
1181
1182 dprintk(5, "%s()\n", __func__);
1183 if (list_empty(&q->active))
1184 {
1185 struct cx23885_buffer *prev;
1186 prev = NULL;
1187
1188 dprintk(5, "%s() queue is empty\n", __func__);
1189
1190 for (;;) {
1191 if (list_empty(&q->queued))
1192 return 0;
1193 buf = list_entry(q->queued.next, struct cx23885_buffer,
1194 vb.queue);
1195 if (NULL == prev) {
1196 list_del(&buf->vb.queue);
1197 list_add_tail(&buf->vb.queue, &q->active);
1198 cx23885_start_dma(port, q, buf);
1199 buf->vb.state = VIDEOBUF_ACTIVE;
1200 buf->count = q->count++;
1201 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1202 dprintk(5, "[%p/%d] restart_queue - first active\n",
1203 buf, buf->vb.i);
1204
1205 } else if (prev->vb.width == buf->vb.width &&
1206 prev->vb.height == buf->vb.height &&
1207 prev->fmt == buf->fmt) {
1208 list_del(&buf->vb.queue);
1209 list_add_tail(&buf->vb.queue, &q->active);
1210 buf->vb.state = VIDEOBUF_ACTIVE;
1211 buf->count = q->count++;
1212 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1213 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1214 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1215 buf, buf->vb.i);
1216 } else {
1217 return 0;
1218 }
1219 prev = buf;
1220 }
1221 return 0;
1222 }
1223
1224 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1225 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1226 buf, buf->vb.i);
1227 cx23885_start_dma(port, q, buf);
1228 list_for_each_entry(buf, &q->active, vb.queue)
1229 buf->count = q->count++;
1230 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1231 return 0;
1232 }
1233
1234 /* ------------------------------------------------------------------ */
1235
1236 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1237 struct cx23885_buffer *buf, enum v4l2_field field)
1238 {
1239 struct cx23885_dev *dev = port->dev;
1240 int size = port->ts_packet_size * port->ts_packet_count;
1241 int rc;
1242
1243 dprintk(1, "%s: %p\n", __func__, buf);
1244 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1245 return -EINVAL;
1246
1247 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1248 buf->vb.width = port->ts_packet_size;
1249 buf->vb.height = port->ts_packet_count;
1250 buf->vb.size = size;
1251 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1252
1253 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1254 goto fail;
1255 cx23885_risc_databuffer(dev->pci, &buf->risc,
1256 videobuf_to_dma(&buf->vb)->sglist,
1257 buf->vb.width, buf->vb.height);
1258 }
1259 buf->vb.state = VIDEOBUF_PREPARED;
1260 return 0;
1261
1262 fail:
1263 cx23885_free_buffer(q, buf);
1264 return rc;
1265 }
1266
1267 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1268 {
1269 struct cx23885_buffer *prev;
1270 struct cx23885_dev *dev = port->dev;
1271 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1272
1273 /* add jump to stopper */
1274 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1275 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1276 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1277
1278 if (list_empty(&cx88q->active)) {
1279 dprintk( 1, "queue is empty - first active\n" );
1280 list_add_tail(&buf->vb.queue, &cx88q->active);
1281 cx23885_start_dma(port, cx88q, buf);
1282 buf->vb.state = VIDEOBUF_ACTIVE;
1283 buf->count = cx88q->count++;
1284 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1285 dprintk(1, "[%p/%d] %s - first active\n",
1286 buf, buf->vb.i, __func__);
1287 } else {
1288 dprintk( 1, "queue is not empty - append to active\n" );
1289 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1290 vb.queue);
1291 list_add_tail(&buf->vb.queue, &cx88q->active);
1292 buf->vb.state = VIDEOBUF_ACTIVE;
1293 buf->count = cx88q->count++;
1294 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1295 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1296 dprintk( 1, "[%p/%d] %s - append to active\n",
1297 buf, buf->vb.i, __func__);
1298 }
1299 }
1300
1301 /* ----------------------------------------------------------- */
1302
1303 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1304 int restart)
1305 {
1306 struct cx23885_dev *dev = port->dev;
1307 struct cx23885_dmaqueue *q = &port->mpegq;
1308 struct cx23885_buffer *buf;
1309 unsigned long flags;
1310
1311 spin_lock_irqsave(&port->slock, flags);
1312 while (!list_empty(&q->active)) {
1313 buf = list_entry(q->active.next, struct cx23885_buffer,
1314 vb.queue);
1315 list_del(&buf->vb.queue);
1316 buf->vb.state = VIDEOBUF_ERROR;
1317 wake_up(&buf->vb.done);
1318 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1319 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1320 }
1321 if (restart) {
1322 dprintk(1, "restarting queue\n" );
1323 cx23885_restart_queue(port, q);
1324 }
1325 spin_unlock_irqrestore(&port->slock, flags);
1326 }
1327
1328 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1329 {
1330 struct cx23885_dev *dev = port->dev;
1331 struct cx23885_dmaqueue *q = &port->mpegq;
1332
1333 dprintk(1, "%s()\n", __FUNCTION__);
1334 del_timer_sync(&q->timeout);
1335 cx23885_stop_dma(port);
1336 do_cancel_buffers(port, "cancel", 0);
1337 }
1338
1339 static void cx23885_timeout(unsigned long data)
1340 {
1341 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1342 struct cx23885_dev *dev = port->dev;
1343
1344 dprintk(1, "%s()\n",__func__);
1345
1346 if (debug > 5)
1347 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1348
1349 cx23885_stop_dma(port);
1350 do_cancel_buffers(port, "timeout", 1);
1351 }
1352
1353 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1354 {
1355 /* FIXME: port1 assumption here. */
1356 struct cx23885_tsport *port = &dev->ts1;
1357 int count = 0;
1358 int handled = 0;
1359
1360 if (status == 0)
1361 return handled;
1362
1363 count = cx_read(port->reg_gpcnt);
1364 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1365 status, cx_read(port->reg_ts_int_msk), count);
1366
1367 if ((status & VID_B_MSK_BAD_PKT) ||
1368 (status & VID_B_MSK_OPC_ERR) ||
1369 (status & VID_B_MSK_VBI_OPC_ERR) ||
1370 (status & VID_B_MSK_SYNC) ||
1371 (status & VID_B_MSK_VBI_SYNC) ||
1372 (status & VID_B_MSK_OF) ||
1373 (status & VID_B_MSK_VBI_OF)) {
1374 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1375 "= 0x%x\n", dev->name, status);
1376 if (status & VID_B_MSK_BAD_PKT)
1377 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1378 if (status & VID_B_MSK_OPC_ERR)
1379 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1380 if (status & VID_B_MSK_VBI_OPC_ERR)
1381 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1382 if (status & VID_B_MSK_SYNC)
1383 dprintk(1, " VID_B_MSK_SYNC\n");
1384 if (status & VID_B_MSK_VBI_SYNC)
1385 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1386 if (status & VID_B_MSK_OF)
1387 dprintk(1, " VID_B_MSK_OF\n");
1388 if (status & VID_B_MSK_VBI_OF)
1389 dprintk(1, " VID_B_MSK_VBI_OF\n");
1390
1391 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1392 cx23885_sram_channel_dump(dev,
1393 &dev->sram_channels[port->sram_chno]);
1394 cx23885_417_check_encoder(dev);
1395 } else if (status & VID_B_MSK_RISCI1) {
1396 dprintk(7, " VID_B_MSK_RISCI1\n");
1397 spin_lock(&port->slock);
1398 cx23885_wakeup(port, &port->mpegq, count);
1399 spin_unlock(&port->slock);
1400 } else if (status & VID_B_MSK_RISCI2) {
1401 dprintk(7, " VID_B_MSK_RISCI2\n");
1402 spin_lock(&port->slock);
1403 cx23885_restart_queue(port, &port->mpegq);
1404 spin_unlock(&port->slock);
1405 }
1406 if (status) {
1407 cx_write(port->reg_ts_int_stat, status);
1408 handled = 1;
1409 }
1410
1411 return handled;
1412 }
1413
1414 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1415 {
1416 struct cx23885_dev *dev = port->dev;
1417 int handled = 0;
1418 u32 count;
1419
1420 if ((status & VID_BC_MSK_OPC_ERR) ||
1421 (status & VID_BC_MSK_BAD_PKT) ||
1422 (status & VID_BC_MSK_SYNC) ||
1423 (status & VID_BC_MSK_OF))
1424 {
1425 if (status & VID_BC_MSK_OPC_ERR)
1426 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1427 if (status & VID_BC_MSK_BAD_PKT)
1428 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1429 if (status & VID_BC_MSK_SYNC)
1430 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC);
1431 if (status & VID_BC_MSK_OF)
1432 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF);
1433
1434 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1435
1436 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1437 cx23885_sram_channel_dump(dev,
1438 &dev->sram_channels[port->sram_chno]);
1439
1440 } else if (status & VID_BC_MSK_RISCI1) {
1441
1442 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1443
1444 spin_lock(&port->slock);
1445 count = cx_read(port->reg_gpcnt);
1446 cx23885_wakeup(port, &port->mpegq, count);
1447 spin_unlock(&port->slock);
1448
1449 } else if (status & VID_BC_MSK_RISCI2) {
1450
1451 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1452
1453 spin_lock(&port->slock);
1454 cx23885_restart_queue(port, &port->mpegq);
1455 spin_unlock(&port->slock);
1456
1457 }
1458 if (status) {
1459 cx_write(port->reg_ts_int_stat, status);
1460 handled = 1;
1461 }
1462
1463 return handled;
1464 }
1465
1466 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1467 {
1468 struct cx23885_dev *dev = dev_id;
1469 struct cx23885_tsport *ts1 = &dev->ts1;
1470 struct cx23885_tsport *ts2 = &dev->ts2;
1471 u32 pci_status, pci_mask;
1472 u32 vida_status, vida_mask;
1473 u32 ts1_status, ts1_mask;
1474 u32 ts2_status, ts2_mask;
1475 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1476
1477 pci_status = cx_read(PCI_INT_STAT);
1478 pci_mask = cx_read(PCI_INT_MSK);
1479 vida_status = cx_read(VID_A_INT_STAT);
1480 vida_mask = cx_read(VID_A_INT_MSK);
1481 ts1_status = cx_read(VID_B_INT_STAT);
1482 ts1_mask = cx_read(VID_B_INT_MSK);
1483 ts2_status = cx_read(VID_C_INT_STAT);
1484 ts2_mask = cx_read(VID_C_INT_MSK);
1485
1486 if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1487 goto out;
1488
1489 vida_count = cx_read(VID_A_GPCNT);
1490 ts1_count = cx_read(ts1->reg_gpcnt);
1491 ts2_count = cx_read(ts2->reg_gpcnt);
1492 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1493 pci_status, pci_mask);
1494 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1495 vida_status, vida_mask, vida_count);
1496 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1497 ts1_status, ts1_mask, ts1_count);
1498 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1499 ts2_status, ts2_mask, ts2_count);
1500
1501 if ( (pci_status & PCI_MSK_RISC_RD) ||
1502 (pci_status & PCI_MSK_RISC_WR) ||
1503 (pci_status & PCI_MSK_AL_RD) ||
1504 (pci_status & PCI_MSK_AL_WR) ||
1505 (pci_status & PCI_MSK_APB_DMA) ||
1506 (pci_status & PCI_MSK_VID_C) ||
1507 (pci_status & PCI_MSK_VID_B) ||
1508 (pci_status & PCI_MSK_VID_A) ||
1509 (pci_status & PCI_MSK_AUD_INT) ||
1510 (pci_status & PCI_MSK_AUD_EXT) )
1511 {
1512
1513 if (pci_status & PCI_MSK_RISC_RD)
1514 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1515 if (pci_status & PCI_MSK_RISC_WR)
1516 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1517 if (pci_status & PCI_MSK_AL_RD)
1518 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1519 if (pci_status & PCI_MSK_AL_WR)
1520 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1521 if (pci_status & PCI_MSK_APB_DMA)
1522 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1523 if (pci_status & PCI_MSK_VID_C)
1524 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1525 if (pci_status & PCI_MSK_VID_B)
1526 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1527 if (pci_status & PCI_MSK_VID_A)
1528 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1529 if (pci_status & PCI_MSK_AUD_INT)
1530 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1531 if (pci_status & PCI_MSK_AUD_EXT)
1532 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1533
1534 }
1535
1536 if (ts1_status) {
1537 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1538 handled += cx23885_irq_ts(ts1, ts1_status);
1539 else
1540 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1541 handled += cx23885_irq_417(dev, ts1_status);
1542 }
1543
1544 if (ts2_status) {
1545 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1546 handled += cx23885_irq_ts(ts2, ts2_status);
1547 else
1548 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1549 handled += cx23885_irq_417(dev, ts2_status);
1550 }
1551
1552 if (vida_status)
1553 handled += cx23885_video_irq(dev, vida_status);
1554
1555 if (handled)
1556 cx_write(PCI_INT_STAT, pci_status);
1557 out:
1558 return IRQ_RETVAL(handled);
1559 }
1560
1561 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1562 const struct pci_device_id *pci_id)
1563 {
1564 struct cx23885_dev *dev;
1565 int err;
1566
1567 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1568 if (NULL == dev)
1569 return -ENOMEM;
1570
1571 /* pci init */
1572 dev->pci = pci_dev;
1573 if (pci_enable_device(pci_dev)) {
1574 err = -EIO;
1575 goto fail_free;
1576 }
1577
1578 if (cx23885_dev_setup(dev) < 0) {
1579 err = -EINVAL;
1580 goto fail_free;
1581 }
1582
1583 /* print pci info */
1584 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1585 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1586 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1587 "latency: %d, mmio: 0x%llx\n", dev->name,
1588 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1589 dev->pci_lat,
1590 (unsigned long long)pci_resource_start(pci_dev, 0));
1591
1592 pci_set_master(pci_dev);
1593 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1594 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1595 err = -EIO;
1596 goto fail_irq;
1597 }
1598
1599 err = request_irq(pci_dev->irq, cx23885_irq,
1600 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1601 if (err < 0) {
1602 printk(KERN_ERR "%s: can't get IRQ %d\n",
1603 dev->name, pci_dev->irq);
1604 goto fail_irq;
1605 }
1606
1607 pci_set_drvdata(pci_dev, dev);
1608 return 0;
1609
1610 fail_irq:
1611 cx23885_dev_unregister(dev);
1612 fail_free:
1613 kfree(dev);
1614 return err;
1615 }
1616
1617 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1618 {
1619 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1620
1621 cx23885_shutdown(dev);
1622
1623 pci_disable_device(pci_dev);
1624
1625 /* unregister stuff */
1626 free_irq(pci_dev->irq, dev);
1627 pci_set_drvdata(pci_dev, NULL);
1628
1629 mutex_lock(&devlist);
1630 list_del(&dev->devlist);
1631 mutex_unlock(&devlist);
1632
1633 cx23885_dev_unregister(dev);
1634 kfree(dev);
1635 }
1636
1637 static struct pci_device_id cx23885_pci_tbl[] = {
1638 {
1639 /* CX23885 */
1640 .vendor = 0x14f1,
1641 .device = 0x8852,
1642 .subvendor = PCI_ANY_ID,
1643 .subdevice = PCI_ANY_ID,
1644 },{
1645 /* CX23887 Rev 2 */
1646 .vendor = 0x14f1,
1647 .device = 0x8880,
1648 .subvendor = PCI_ANY_ID,
1649 .subdevice = PCI_ANY_ID,
1650 },{
1651 /* --- end of list --- */
1652 }
1653 };
1654 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1655
1656 static struct pci_driver cx23885_pci_driver = {
1657 .name = "cx23885",
1658 .id_table = cx23885_pci_tbl,
1659 .probe = cx23885_initdev,
1660 .remove = __devexit_p(cx23885_finidev),
1661 /* TODO */
1662 .suspend = NULL,
1663 .resume = NULL,
1664 };
1665
1666 static int cx23885_init(void)
1667 {
1668 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1669 (CX23885_VERSION_CODE >> 16) & 0xff,
1670 (CX23885_VERSION_CODE >> 8) & 0xff,
1671 CX23885_VERSION_CODE & 0xff);
1672 #ifdef SNAPSHOT
1673 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1674 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1675 #endif
1676 return pci_register_driver(&cx23885_pci_driver);
1677 }
1678
1679 static void cx23885_fini(void)
1680 {
1681 pci_unregister_driver(&cx23885_pci_driver);
1682 }
1683
1684 module_init(cx23885_init);
1685 module_exit(cx23885_fini);
1686
1687 /* ----------------------------------------------------------- */
1688 /*
1689 * Local variables:
1690 * c-basic-offset: 8
1691 * End:
1692 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off
1693 */
Verdex Pro support