4 * Copyright (C) 1999 Intel Corp.
5 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
7 * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
12 * 00/04/19 D. Mosberger Rewritten to mirror more closely the x86 I/O
13 * APIC code. In particular, we now have separate
14 * handlers for edge and level triggered
16 * 00/10/27 Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
17 * allocation PCI to vector mapping, shared PCI
19 * 00/10/27 D. Mosberger Document things a bit more to make them more
20 * understandable. Clean up much of the old
22 * 01/07/27 J.I. Lee PCI irq routing, Platform/Legacy interrupts
23 * and fixes for ACPI S5(SoftOff) support.
24 * 02/01/23 J.I. Lee iosapic pgm fixes for PCI irq routing from _PRT
25 * 02/01/07 E. Focht <efocht@ess.nec.de> Redirectable interrupt
26 * vectors in iosapic_set_affinity(),
27 * initializations for /proc/irq/#/smp_affinity
28 * 02/04/02 P. Diefenbaugh Cleaned up ACPI PCI IRQ routing.
29 * 02/04/18 J.I. Lee bug fix in iosapic_init_pci_irq
30 * 02/04/30 J.I. Lee bug fix in find_iosapic to fix ACPI PCI IRQ to
31 * IOSAPIC mapping error
32 * 02/07/29 T. Kochi Allocate interrupt vectors dynamically
33 * 02/08/04 T. Kochi Cleaned up terminology (irq, global system
34 * interrupt, vector, etc.)
35 * 02/09/20 D. Mosberger Simplified by taking advantage of ACPI's
37 * 03/02/19 B. Helgaas Make pcat_compat system-wide, not per-IOSAPIC.
38 * Remove iosapic_address & gsi_base from
39 * external interfaces. Rationalize
40 * __init/__devinit attributes.
41 * 04/12/04 Ashok Raj <ashok.raj@intel.com> Intel Corporation 2004
42 * Updated to work with irq migration necessary
46 * Here is what the interrupt logic between a PCI device and the kernel looks
49 * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
50 * INTD). The device is uniquely identified by its bus-, and slot-number
51 * (the function number does not matter here because all functions share
52 * the same interrupt lines).
54 * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
55 * controller. Multiple interrupt lines may have to share the same
56 * IOSAPIC pin (if they're level triggered and use the same polarity).
57 * Each interrupt line has a unique Global System Interrupt (GSI) number
58 * which can be calculated as the sum of the controller's base GSI number
59 * and the IOSAPIC pin number to which the line connects.
61 * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
62 * IOSAPIC pin into the IA-64 interrupt vector. This interrupt vector is then
65 * (4) The kernel recognizes an interrupt as an IRQ. The IRQ interface is
66 * used as architecture-independent interrupt handling mechanism in Linux.
67 * As an IRQ is a number, we have to have
68 * IA-64 interrupt vector number <-> IRQ number mapping. On smaller
69 * systems, we use one-to-one mapping between IA-64 vector and IRQ. A
70 * platform can implement platform_irq_to_vector(irq) and
71 * platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
72 * Please see also include/asm-ia64/hw_irq.h for those APIs.
74 * To sum up, there are three levels of mappings involved:
76 * PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
78 * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
79 * describeinterrupts. Now we use "IRQ" only for Linux IRQ's. ISA IRQ
80 * (isa_irq) is the only exception in this source code.
82 #include <linux/config.h>
84 #include <linux/acpi.h>
85 #include <linux/init.h>
86 #include <linux/irq.h>
87 #include <linux/kernel.h>
88 #include <linux/list.h>
89 #include <linux/pci.h>
90 #include <linux/smp.h>
91 #include <linux/smp_lock.h>
92 #include <linux/string.h>
93 #include <linux/bootmem.h>
95 #include <asm/delay.h>
96 #include <asm/hw_irq.h>
98 #include <asm/iosapic.h>
99 #include <asm/machvec.h>
100 #include <asm/processor.h>
101 #include <asm/ptrace.h>
102 #include <asm/system.h>
104 #undef DEBUG_INTERRUPT_ROUTING
106 #ifdef DEBUG_INTERRUPT_ROUTING
107 #define DBG(fmt...) printk(fmt)
112 #define NR_PREALLOCATE_RTE_ENTRIES \
113 (PAGE_SIZE / sizeof(struct iosapic_rte_info))
114 #define RTE_PREALLOCATED (1)
116 static DEFINE_SPINLOCK(iosapic_lock
);
119 * These tables map IA-64 vectors to the IOSAPIC pin that generates this
123 struct iosapic_rte_info
{
124 struct list_head rte_list
; /* node in list of RTEs sharing the
126 char __iomem
*addr
; /* base address of IOSAPIC */
127 unsigned int gsi_base
; /* first GSI assigned to this
129 char rte_index
; /* IOSAPIC RTE index */
130 int refcnt
; /* reference counter */
131 unsigned int flags
; /* flags */
132 } ____cacheline_aligned
;
134 static struct iosapic_intr_info
{
135 struct list_head rtes
; /* RTEs using this vector (empty =>
136 * not an IOSAPIC interrupt) */
137 int count
; /* # of RTEs that shares this vector */
138 u32 low32
; /* current value of low word of
139 * Redirection table entry */
140 unsigned int dest
; /* destination CPU physical ID */
141 unsigned char dmode
: 3; /* delivery mode (see iosapic.h) */
142 unsigned char polarity
: 1; /* interrupt polarity
144 unsigned char trigger
: 1; /* trigger mode (see iosapic.h) */
145 } iosapic_intr_info
[IA64_NUM_VECTORS
];
147 static struct iosapic
{
148 char __iomem
*addr
; /* base address of IOSAPIC */
149 unsigned int gsi_base
; /* first GSI assigned to this
151 unsigned short num_rte
; /* # of RTEs on this IOSAPIC */
152 int rtes_inuse
; /* # of RTEs in use on this IOSAPIC */
154 unsigned short node
; /* numa node association via pxm */
156 } iosapic_lists
[NR_IOSAPICS
];
158 static unsigned char pcat_compat __devinitdata
; /* 8259 compatibility flag */
160 static int iosapic_kmalloc_ok
;
161 static LIST_HEAD(free_rte_list
);
164 * Find an IOSAPIC associated with a GSI
167 find_iosapic (unsigned int gsi
)
171 for (i
= 0; i
< NR_IOSAPICS
; i
++) {
172 if ((unsigned) (gsi
- iosapic_lists
[i
].gsi_base
) <
173 iosapic_lists
[i
].num_rte
)
181 _gsi_to_vector (unsigned int gsi
)
183 struct iosapic_intr_info
*info
;
184 struct iosapic_rte_info
*rte
;
186 for (info
= iosapic_intr_info
; info
<
187 iosapic_intr_info
+ IA64_NUM_VECTORS
; ++info
)
188 list_for_each_entry(rte
, &info
->rtes
, rte_list
)
189 if (rte
->gsi_base
+ rte
->rte_index
== gsi
)
190 return info
- iosapic_intr_info
;
195 * Translate GSI number to the corresponding IA-64 interrupt vector. If no
196 * entry exists, return -1.
199 gsi_to_vector (unsigned int gsi
)
201 return _gsi_to_vector(gsi
);
205 gsi_to_irq (unsigned int gsi
)
210 * XXX fix me: this assumes an identity mapping between IA-64 vector
211 * and Linux irq numbers...
213 spin_lock_irqsave(&iosapic_lock
, flags
);
215 irq
= _gsi_to_vector(gsi
);
217 spin_unlock_irqrestore(&iosapic_lock
, flags
);
222 static struct iosapic_rte_info
*gsi_vector_to_rte(unsigned int gsi
,
225 struct iosapic_rte_info
*rte
;
227 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
)
228 if (rte
->gsi_base
+ rte
->rte_index
== gsi
)
234 set_rte (unsigned int gsi
, unsigned int vector
, unsigned int dest
, int mask
)
236 unsigned long pol
, trigger
, dmode
;
241 struct iosapic_rte_info
*rte
;
243 DBG(KERN_DEBUG
"IOSAPIC: routing vector %d to 0x%x\n", vector
, dest
);
245 rte
= gsi_vector_to_rte(gsi
, vector
);
247 return; /* not an IOSAPIC interrupt */
249 rte_index
= rte
->rte_index
;
251 pol
= iosapic_intr_info
[vector
].polarity
;
252 trigger
= iosapic_intr_info
[vector
].trigger
;
253 dmode
= iosapic_intr_info
[vector
].dmode
;
255 redir
= (dmode
== IOSAPIC_LOWEST_PRIORITY
) ? 1 : 0;
261 for (irq
= 0; irq
< NR_IRQS
; ++irq
)
262 if (irq_to_vector(irq
) == vector
) {
263 set_irq_affinity_info(irq
,
264 (int)(dest
& 0xffff),
271 low32
= ((pol
<< IOSAPIC_POLARITY_SHIFT
) |
272 (trigger
<< IOSAPIC_TRIGGER_SHIFT
) |
273 (dmode
<< IOSAPIC_DELIVERY_SHIFT
) |
274 ((mask
? 1 : 0) << IOSAPIC_MASK_SHIFT
) |
277 /* dest contains both id and eid */
278 high32
= (dest
<< IOSAPIC_DEST_SHIFT
);
280 iosapic_write(addr
, IOSAPIC_RTE_HIGH(rte_index
), high32
);
281 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
282 iosapic_intr_info
[vector
].low32
= low32
;
283 iosapic_intr_info
[vector
].dest
= dest
;
287 nop (unsigned int irq
)
293 mask_irq (unsigned int irq
)
299 ia64_vector vec
= irq_to_vector(irq
);
300 struct iosapic_rte_info
*rte
;
302 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
303 return; /* not an IOSAPIC interrupt! */
305 spin_lock_irqsave(&iosapic_lock
, flags
);
307 /* set only the mask bit */
308 low32
= iosapic_intr_info
[vec
].low32
|= IOSAPIC_MASK
;
309 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
,
312 rte_index
= rte
->rte_index
;
313 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
316 spin_unlock_irqrestore(&iosapic_lock
, flags
);
320 unmask_irq (unsigned int irq
)
326 ia64_vector vec
= irq_to_vector(irq
);
327 struct iosapic_rte_info
*rte
;
329 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
330 return; /* not an IOSAPIC interrupt! */
332 spin_lock_irqsave(&iosapic_lock
, flags
);
334 low32
= iosapic_intr_info
[vec
].low32
&= ~IOSAPIC_MASK
;
335 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
,
338 rte_index
= rte
->rte_index
;
339 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
342 spin_unlock_irqrestore(&iosapic_lock
, flags
);
347 iosapic_set_affinity (unsigned int irq
, cpumask_t mask
)
354 int redir
= (irq
& IA64_IRQ_REDIRECTED
) ? 1 : 0;
356 struct iosapic_rte_info
*rte
;
358 irq
&= (~IA64_IRQ_REDIRECTED
);
359 vec
= irq_to_vector(irq
);
361 if (cpus_empty(mask
))
364 dest
= cpu_physical_id(first_cpu(mask
));
366 if (list_empty(&iosapic_intr_info
[vec
].rtes
))
367 return; /* not an IOSAPIC interrupt */
369 set_irq_affinity_info(irq
, dest
, redir
);
371 /* dest contains both id and eid */
372 high32
= dest
<< IOSAPIC_DEST_SHIFT
;
374 spin_lock_irqsave(&iosapic_lock
, flags
);
376 low32
= iosapic_intr_info
[vec
].low32
&
377 ~(7 << IOSAPIC_DELIVERY_SHIFT
);
380 /* change delivery mode to lowest priority */
381 low32
|= (IOSAPIC_LOWEST_PRIORITY
<<
382 IOSAPIC_DELIVERY_SHIFT
);
384 /* change delivery mode to fixed */
385 low32
|= (IOSAPIC_FIXED
<< IOSAPIC_DELIVERY_SHIFT
);
387 iosapic_intr_info
[vec
].low32
= low32
;
388 iosapic_intr_info
[vec
].dest
= dest
;
389 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
,
392 rte_index
= rte
->rte_index
;
393 iosapic_write(addr
, IOSAPIC_RTE_HIGH(rte_index
),
395 iosapic_write(addr
, IOSAPIC_RTE_LOW(rte_index
), low32
);
398 spin_unlock_irqrestore(&iosapic_lock
, flags
);
403 * Handlers for level-triggered interrupts.
407 iosapic_startup_level_irq (unsigned int irq
)
414 iosapic_end_level_irq (unsigned int irq
)
416 ia64_vector vec
= irq_to_vector(irq
);
417 struct iosapic_rte_info
*rte
;
419 move_native_irq(irq
);
420 list_for_each_entry(rte
, &iosapic_intr_info
[vec
].rtes
, rte_list
)
421 iosapic_eoi(rte
->addr
, vec
);
424 #define iosapic_shutdown_level_irq mask_irq
425 #define iosapic_enable_level_irq unmask_irq
426 #define iosapic_disable_level_irq mask_irq
427 #define iosapic_ack_level_irq nop
429 struct hw_interrupt_type irq_type_iosapic_level
= {
430 .typename
= "IO-SAPIC-level",
431 .startup
= iosapic_startup_level_irq
,
432 .shutdown
= iosapic_shutdown_level_irq
,
433 .enable
= iosapic_enable_level_irq
,
434 .disable
= iosapic_disable_level_irq
,
435 .ack
= iosapic_ack_level_irq
,
436 .end
= iosapic_end_level_irq
,
437 .set_affinity
= iosapic_set_affinity
441 * Handlers for edge-triggered interrupts.
445 iosapic_startup_edge_irq (unsigned int irq
)
449 * IOSAPIC simply drops interrupts pended while the
450 * corresponding pin was masked, so we can't know if an
451 * interrupt is pending already. Let's hope not...
457 iosapic_ack_edge_irq (unsigned int irq
)
459 irq_desc_t
*idesc
= irq_descp(irq
);
461 move_native_irq(irq
);
463 * Once we have recorded IRQ_PENDING already, we can mask the
464 * interrupt for real. This prevents IRQ storms from unhandled
467 if ((idesc
->status
& (IRQ_PENDING
|IRQ_DISABLED
)) ==
468 (IRQ_PENDING
|IRQ_DISABLED
))
472 #define iosapic_enable_edge_irq unmask_irq
473 #define iosapic_disable_edge_irq nop
474 #define iosapic_end_edge_irq nop
476 struct hw_interrupt_type irq_type_iosapic_edge
= {
477 .typename
= "IO-SAPIC-edge",
478 .startup
= iosapic_startup_edge_irq
,
479 .shutdown
= iosapic_disable_edge_irq
,
480 .enable
= iosapic_enable_edge_irq
,
481 .disable
= iosapic_disable_edge_irq
,
482 .ack
= iosapic_ack_edge_irq
,
483 .end
= iosapic_end_edge_irq
,
484 .set_affinity
= iosapic_set_affinity
488 iosapic_version (char __iomem
*addr
)
491 * IOSAPIC Version Register return 32 bit structure like:
493 * unsigned int version : 8;
494 * unsigned int reserved1 : 8;
495 * unsigned int max_redir : 8;
496 * unsigned int reserved2 : 8;
499 return iosapic_read(addr
, IOSAPIC_VERSION
);
502 static int iosapic_find_sharable_vector (unsigned long trigger
,
505 int i
, vector
= -1, min_count
= -1;
506 struct iosapic_intr_info
*info
;
509 * shared vectors for edge-triggered interrupts are not
512 if (trigger
== IOSAPIC_EDGE
)
515 for (i
= IA64_FIRST_DEVICE_VECTOR
; i
<= IA64_LAST_DEVICE_VECTOR
; i
++) {
516 info
= &iosapic_intr_info
[i
];
517 if (info
->trigger
== trigger
&& info
->polarity
== pol
&&
518 (info
->dmode
== IOSAPIC_FIXED
|| info
->dmode
==
519 IOSAPIC_LOWEST_PRIORITY
)) {
520 if (min_count
== -1 || info
->count
< min_count
) {
522 min_count
= info
->count
;
531 * if the given vector is already owned by other,
532 * assign a new vector for the other and make the vector available
535 iosapic_reassign_vector (int vector
)
539 if (!list_empty(&iosapic_intr_info
[vector
].rtes
)) {
540 new_vector
= assign_irq_vector(AUTO_ASSIGN
);
542 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
543 printk(KERN_INFO
"Reassigning vector %d to %d\n",
545 memcpy(&iosapic_intr_info
[new_vector
], &iosapic_intr_info
[vector
],
546 sizeof(struct iosapic_intr_info
));
547 INIT_LIST_HEAD(&iosapic_intr_info
[new_vector
].rtes
);
548 list_move(iosapic_intr_info
[vector
].rtes
.next
,
549 &iosapic_intr_info
[new_vector
].rtes
);
550 memset(&iosapic_intr_info
[vector
], 0,
551 sizeof(struct iosapic_intr_info
));
552 iosapic_intr_info
[vector
].low32
= IOSAPIC_MASK
;
553 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
557 static struct iosapic_rte_info
*iosapic_alloc_rte (void)
560 struct iosapic_rte_info
*rte
;
561 int preallocated
= 0;
563 if (!iosapic_kmalloc_ok
&& list_empty(&free_rte_list
)) {
564 rte
= alloc_bootmem(sizeof(struct iosapic_rte_info
) *
565 NR_PREALLOCATE_RTE_ENTRIES
);
568 for (i
= 0; i
< NR_PREALLOCATE_RTE_ENTRIES
; i
++, rte
++)
569 list_add(&rte
->rte_list
, &free_rte_list
);
572 if (!list_empty(&free_rte_list
)) {
573 rte
= list_entry(free_rte_list
.next
, struct iosapic_rte_info
,
575 list_del(&rte
->rte_list
);
578 rte
= kmalloc(sizeof(struct iosapic_rte_info
), GFP_ATOMIC
);
583 memset(rte
, 0, sizeof(struct iosapic_rte_info
));
585 rte
->flags
|= RTE_PREALLOCATED
;
590 static void iosapic_free_rte (struct iosapic_rte_info
*rte
)
592 if (rte
->flags
& RTE_PREALLOCATED
)
593 list_add_tail(&rte
->rte_list
, &free_rte_list
);
598 static inline int vector_is_shared (int vector
)
600 return (iosapic_intr_info
[vector
].count
> 1);
604 register_intr (unsigned int gsi
, int vector
, unsigned char delivery
,
605 unsigned long polarity
, unsigned long trigger
)
608 struct hw_interrupt_type
*irq_type
;
611 unsigned long gsi_base
;
612 void __iomem
*iosapic_address
;
613 struct iosapic_rte_info
*rte
;
615 index
= find_iosapic(gsi
);
617 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
622 iosapic_address
= iosapic_lists
[index
].addr
;
623 gsi_base
= iosapic_lists
[index
].gsi_base
;
625 rte
= gsi_vector_to_rte(gsi
, vector
);
627 rte
= iosapic_alloc_rte();
629 printk(KERN_WARNING
"%s: cannot allocate memory\n",
634 rte_index
= gsi
- gsi_base
;
635 rte
->rte_index
= rte_index
;
636 rte
->addr
= iosapic_address
;
637 rte
->gsi_base
= gsi_base
;
639 list_add_tail(&rte
->rte_list
, &iosapic_intr_info
[vector
].rtes
);
640 iosapic_intr_info
[vector
].count
++;
641 iosapic_lists
[index
].rtes_inuse
++;
643 else if (vector_is_shared(vector
)) {
644 struct iosapic_intr_info
*info
= &iosapic_intr_info
[vector
];
645 if (info
->trigger
!= trigger
|| info
->polarity
!= polarity
) {
647 "%s: cannot override the interrupt\n",
653 iosapic_intr_info
[vector
].polarity
= polarity
;
654 iosapic_intr_info
[vector
].dmode
= delivery
;
655 iosapic_intr_info
[vector
].trigger
= trigger
;
657 if (trigger
== IOSAPIC_EDGE
)
658 irq_type
= &irq_type_iosapic_edge
;
660 irq_type
= &irq_type_iosapic_level
;
662 idesc
= irq_descp(vector
);
663 if (idesc
->handler
!= irq_type
) {
664 if (idesc
->handler
!= &no_irq_type
)
666 "%s: changing vector %d from %s to %s\n",
667 __FUNCTION__
, vector
,
668 idesc
->handler
->typename
, irq_type
->typename
);
669 idesc
->handler
= irq_type
;
675 get_target_cpu (unsigned int gsi
, int vector
)
679 extern int cpe_vector
;
682 * In case of vector shared by multiple RTEs, all RTEs that
683 * share the vector need to use the same destination CPU.
685 if (!list_empty(&iosapic_intr_info
[vector
].rtes
))
686 return iosapic_intr_info
[vector
].dest
;
689 * If the platform supports redirection via XTP, let it
690 * distribute interrupts.
692 if (smp_int_redirect
& SMP_IRQ_REDIRECTION
)
693 return cpu_physical_id(smp_processor_id());
696 * Some interrupts (ACPI SCI, for instance) are registered
697 * before the BSP is marked as online.
699 if (!cpu_online(smp_processor_id()))
700 return cpu_physical_id(smp_processor_id());
703 if (cpe_vector
> 0 && vector
== IA64_CPEP_VECTOR
)
704 return get_cpei_target_cpu();
709 int num_cpus
, cpu_index
, iosapic_index
, numa_cpu
, i
= 0;
712 iosapic_index
= find_iosapic(gsi
);
713 if (iosapic_index
< 0 ||
714 iosapic_lists
[iosapic_index
].node
== MAX_NUMNODES
)
715 goto skip_numa_setup
;
717 cpu_mask
= node_to_cpumask(iosapic_lists
[iosapic_index
].node
);
719 for_each_cpu_mask(numa_cpu
, cpu_mask
) {
720 if (!cpu_online(numa_cpu
))
721 cpu_clear(numa_cpu
, cpu_mask
);
724 num_cpus
= cpus_weight(cpu_mask
);
727 goto skip_numa_setup
;
729 /* Use vector assignment to distribute across cpus in node */
730 cpu_index
= vector
% num_cpus
;
732 for (numa_cpu
= first_cpu(cpu_mask
) ; i
< cpu_index
; i
++)
733 numa_cpu
= next_cpu(numa_cpu
, cpu_mask
);
735 if (numa_cpu
!= NR_CPUS
)
736 return cpu_physical_id(numa_cpu
);
741 * Otherwise, round-robin interrupt vectors across all the
742 * processors. (It'd be nice if we could be smarter in the
746 if (++cpu
>= NR_CPUS
)
748 } while (!cpu_online(cpu
));
750 return cpu_physical_id(cpu
);
751 #else /* CONFIG_SMP */
752 return cpu_physical_id(smp_processor_id());
757 * ACPI can describe IOSAPIC interrupts via static tables and namespace
758 * methods. This provides an interface to register those interrupts and
759 * program the IOSAPIC RTE.
762 iosapic_register_intr (unsigned int gsi
,
763 unsigned long polarity
, unsigned long trigger
)
765 int vector
, mask
= 1, err
;
768 struct iosapic_rte_info
*rte
;
772 * If this GSI has already been registered (i.e., it's a
773 * shared interrupt, or we lost a race to register it),
774 * don't touch the RTE.
776 spin_lock_irqsave(&iosapic_lock
, flags
);
778 vector
= gsi_to_vector(gsi
);
780 rte
= gsi_vector_to_rte(gsi
, vector
);
782 spin_unlock_irqrestore(&iosapic_lock
, flags
);
786 spin_unlock_irqrestore(&iosapic_lock
, flags
);
788 /* If vector is running out, we try to find a sharable vector */
789 vector
= assign_irq_vector(AUTO_ASSIGN
);
791 vector
= iosapic_find_sharable_vector(trigger
, polarity
);
796 spin_lock_irqsave(&irq_descp(vector
)->lock
, flags
);
797 spin_lock(&iosapic_lock
);
799 if (gsi_to_vector(gsi
) > 0) {
800 if (list_empty(&iosapic_intr_info
[vector
].rtes
))
801 free_irq_vector(vector
);
802 spin_unlock(&iosapic_lock
);
803 spin_unlock_irqrestore(&irq_descp(vector
)->lock
,
808 dest
= get_target_cpu(gsi
, vector
);
809 err
= register_intr(gsi
, vector
, IOSAPIC_LOWEST_PRIORITY
,
812 spin_unlock(&iosapic_lock
);
813 spin_unlock_irqrestore(&irq_descp(vector
)->lock
,
819 * If the vector is shared and already unmasked for
820 * other interrupt sources, don't mask it.
822 low32
= iosapic_intr_info
[vector
].low32
;
823 if (vector_is_shared(vector
) && !(low32
& IOSAPIC_MASK
))
825 set_rte(gsi
, vector
, dest
, mask
);
827 spin_unlock(&iosapic_lock
);
828 spin_unlock_irqrestore(&irq_descp(vector
)->lock
, flags
);
830 printk(KERN_INFO
"GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
831 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
832 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
833 cpu_logical_id(dest
), dest
, vector
);
839 iosapic_unregister_intr (unsigned int gsi
)
842 int irq
, vector
, index
;
845 unsigned long trigger
, polarity
;
847 struct iosapic_rte_info
*rte
;
850 * If the irq associated with the gsi is not found,
851 * iosapic_unregister_intr() is unbalanced. We need to check
852 * this again after getting locks.
854 irq
= gsi_to_irq(gsi
);
856 printk(KERN_ERR
"iosapic_unregister_intr(%u) unbalanced\n",
861 vector
= irq_to_vector(irq
);
863 idesc
= irq_descp(irq
);
864 spin_lock_irqsave(&idesc
->lock
, flags
);
865 spin_lock(&iosapic_lock
);
867 if ((rte
= gsi_vector_to_rte(gsi
, vector
)) == NULL
) {
869 "iosapic_unregister_intr(%u) unbalanced\n",
875 if (--rte
->refcnt
> 0)
878 /* Mask the interrupt */
879 low32
= iosapic_intr_info
[vector
].low32
| IOSAPIC_MASK
;
880 iosapic_write(rte
->addr
, IOSAPIC_RTE_LOW(rte
->rte_index
),
883 /* Remove the rte entry from the list */
884 list_del(&rte
->rte_list
);
885 iosapic_intr_info
[vector
].count
--;
886 iosapic_free_rte(rte
);
887 index
= find_iosapic(gsi
);
888 iosapic_lists
[index
].rtes_inuse
--;
889 WARN_ON(iosapic_lists
[index
].rtes_inuse
< 0);
891 trigger
= iosapic_intr_info
[vector
].trigger
;
892 polarity
= iosapic_intr_info
[vector
].polarity
;
893 dest
= iosapic_intr_info
[vector
].dest
;
895 "GSI %u (%s, %s) -> CPU %d (0x%04x)"
896 " vector %d unregistered\n",
897 gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
898 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
899 cpu_logical_id(dest
), dest
, vector
);
901 if (list_empty(&iosapic_intr_info
[vector
].rtes
)) {
903 BUG_ON(iosapic_intr_info
[vector
].count
);
905 /* Clear the interrupt controller descriptor */
906 idesc
->handler
= &no_irq_type
;
908 /* Clear the interrupt information */
909 memset(&iosapic_intr_info
[vector
], 0,
910 sizeof(struct iosapic_intr_info
));
911 iosapic_intr_info
[vector
].low32
|= IOSAPIC_MASK
;
912 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
916 "interrupt handlers still exist on"
921 /* Free the interrupt vector */
922 free_irq_vector(vector
);
926 spin_unlock(&iosapic_lock
);
927 spin_unlock_irqrestore(&idesc
->lock
, flags
);
931 * ACPI calls this when it finds an entry for a platform interrupt.
934 iosapic_register_platform_intr (u32 int_type
, unsigned int gsi
,
935 int iosapic_vector
, u16 eid
, u16 id
,
936 unsigned long polarity
, unsigned long trigger
)
938 static const char * const name
[] = {"unknown", "PMI", "INIT", "CPEI"};
939 unsigned char delivery
;
940 int vector
, mask
= 0;
941 unsigned int dest
= ((id
<< 8) | eid
) & 0xffff;
944 case ACPI_INTERRUPT_PMI
:
945 vector
= iosapic_vector
;
947 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
948 * we need to make sure the vector is available
950 iosapic_reassign_vector(vector
);
951 delivery
= IOSAPIC_PMI
;
953 case ACPI_INTERRUPT_INIT
:
954 vector
= assign_irq_vector(AUTO_ASSIGN
);
956 panic("%s: out of interrupt vectors!\n", __FUNCTION__
);
957 delivery
= IOSAPIC_INIT
;
959 case ACPI_INTERRUPT_CPEI
:
960 vector
= IA64_CPE_VECTOR
;
961 delivery
= IOSAPIC_LOWEST_PRIORITY
;
965 printk(KERN_ERR
"%s: invalid int type 0x%x\n", __FUNCTION__
,
970 register_intr(gsi
, vector
, delivery
, polarity
, trigger
);
973 "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
975 int_type
< ARRAY_SIZE(name
) ? name
[int_type
] : "unknown",
976 int_type
, gsi
, (trigger
== IOSAPIC_EDGE
? "edge" : "level"),
977 (polarity
== IOSAPIC_POL_HIGH
? "high" : "low"),
978 cpu_logical_id(dest
), dest
, vector
);
980 set_rte(gsi
, vector
, dest
, mask
);
985 * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
988 iosapic_override_isa_irq (unsigned int isa_irq
, unsigned int gsi
,
989 unsigned long polarity
,
990 unsigned long trigger
)
993 unsigned int dest
= cpu_physical_id(smp_processor_id());
995 vector
= isa_irq_to_vector(isa_irq
);
997 register_intr(gsi
, vector
, IOSAPIC_LOWEST_PRIORITY
, polarity
, trigger
);
999 DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
1000 isa_irq
, gsi
, trigger
== IOSAPIC_EDGE
? "edge" : "level",
1001 polarity
== IOSAPIC_POL_HIGH
? "high" : "low",
1002 cpu_logical_id(dest
), dest
, vector
);
1004 set_rte(gsi
, vector
, dest
, 1);
1008 iosapic_system_init (int system_pcat_compat
)
1012 for (vector
= 0; vector
< IA64_NUM_VECTORS
; ++vector
) {
1013 iosapic_intr_info
[vector
].low32
= IOSAPIC_MASK
;
1014 /* mark as unused */
1015 INIT_LIST_HEAD(&iosapic_intr_info
[vector
].rtes
);
1018 pcat_compat
= system_pcat_compat
;
1021 * Disable the compatibility mode interrupts (8259 style),
1022 * needs IN/OUT support enabled.
1025 "%s: Disabling PC-AT compatible 8259 interrupts\n",
1033 iosapic_alloc (void)
1037 for (index
= 0; index
< NR_IOSAPICS
; index
++)
1038 if (!iosapic_lists
[index
].addr
)
1041 printk(KERN_WARNING
"%s: failed to allocate iosapic\n", __FUNCTION__
);
1046 iosapic_free (int index
)
1048 memset(&iosapic_lists
[index
], 0, sizeof(iosapic_lists
[0]));
1052 iosapic_check_gsi_range (unsigned int gsi_base
, unsigned int ver
)
1055 unsigned int gsi_end
, base
, end
;
1057 /* check gsi range */
1058 gsi_end
= gsi_base
+ ((ver
>> 16) & 0xff);
1059 for (index
= 0; index
< NR_IOSAPICS
; index
++) {
1060 if (!iosapic_lists
[index
].addr
)
1063 base
= iosapic_lists
[index
].gsi_base
;
1064 end
= base
+ iosapic_lists
[index
].num_rte
- 1;
1066 if (gsi_end
< base
|| end
< gsi_base
)
1075 iosapic_init (unsigned long phys_addr
, unsigned int gsi_base
)
1077 int num_rte
, err
, index
;
1078 unsigned int isa_irq
, ver
;
1080 unsigned long flags
;
1082 spin_lock_irqsave(&iosapic_lock
, flags
);
1084 addr
= ioremap(phys_addr
, 0);
1085 ver
= iosapic_version(addr
);
1087 if ((err
= iosapic_check_gsi_range(gsi_base
, ver
))) {
1089 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1094 * The MAX_REDIR register holds the highest input pin
1095 * number (starting from 0).
1096 * We add 1 so that we can use it for number of pins (= RTEs)
1098 num_rte
= ((ver
>> 16) & 0xff) + 1;
1100 index
= iosapic_alloc();
1101 iosapic_lists
[index
].addr
= addr
;
1102 iosapic_lists
[index
].gsi_base
= gsi_base
;
1103 iosapic_lists
[index
].num_rte
= num_rte
;
1105 iosapic_lists
[index
].node
= MAX_NUMNODES
;
1108 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1110 if ((gsi_base
== 0) && pcat_compat
) {
1112 * Map the legacy ISA devices into the IOSAPIC data. Some of
1113 * these may get reprogrammed later on with data from the ACPI
1114 * Interrupt Source Override table.
1116 for (isa_irq
= 0; isa_irq
< 16; ++isa_irq
)
1117 iosapic_override_isa_irq(isa_irq
, isa_irq
,
1124 #ifdef CONFIG_HOTPLUG
1126 iosapic_remove (unsigned int gsi_base
)
1129 unsigned long flags
;
1131 spin_lock_irqsave(&iosapic_lock
, flags
);
1133 index
= find_iosapic(gsi_base
);
1135 printk(KERN_WARNING
"%s: No IOSAPIC for GSI base %u\n",
1136 __FUNCTION__
, gsi_base
);
1140 if (iosapic_lists
[index
].rtes_inuse
) {
1143 "%s: IOSAPIC for GSI base %u is busy\n",
1144 __FUNCTION__
, gsi_base
);
1148 iounmap(iosapic_lists
[index
].addr
);
1149 iosapic_free(index
);
1152 spin_unlock_irqrestore(&iosapic_lock
, flags
);
1155 #endif /* CONFIG_HOTPLUG */
1159 map_iosapic_to_node(unsigned int gsi_base
, int node
)
1163 index
= find_iosapic(gsi_base
);
1165 printk(KERN_WARNING
"%s: No IOSAPIC for GSI %u\n",
1166 __FUNCTION__
, gsi_base
);
1169 iosapic_lists
[index
].node
= node
;
1174 static int __init
iosapic_enable_kmalloc (void)
1176 iosapic_kmalloc_ok
= 1;
1179 core_initcall (iosapic_enable_kmalloc
);