2 * Support for IDE interfaces on Celleb platform
4 * (C) Copyright 2006 TOSHIBA CORPORATION
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
45 #define DRV_NAME "pata_scc"
46 #define DRV_VERSION "0.2"
48 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
51 #define SCC_CTRL_BAR 0
52 #define SCC_BMID_BAR 1
54 /* offset of CTRL registers */
55 #define SCC_CTL_PIOSHT 0x000
56 #define SCC_CTL_PIOCT 0x004
57 #define SCC_CTL_MDMACT 0x008
58 #define SCC_CTL_MCRCST 0x00C
59 #define SCC_CTL_SDMACT 0x010
60 #define SCC_CTL_SCRCST 0x014
61 #define SCC_CTL_UDENVT 0x018
62 #define SCC_CTL_TDVHSEL 0x020
63 #define SCC_CTL_MODEREG 0x024
64 #define SCC_CTL_ECMODE 0xF00
65 #define SCC_CTL_MAEA0 0xF50
66 #define SCC_CTL_MAEC0 0xF54
67 #define SCC_CTL_CCKCTRL 0xFF0
69 /* offset of BMID registers */
70 #define SCC_DMA_CMD 0x000
71 #define SCC_DMA_STATUS 0x004
72 #define SCC_DMA_TABLE_OFS 0x008
73 #define SCC_DMA_INTMASK 0x010
74 #define SCC_DMA_INTST 0x014
75 #define SCC_DMA_PTERADD 0x018
76 #define SCC_REG_CMD_ADDR 0x020
77 #define SCC_REG_DATA 0x000
78 #define SCC_REG_ERR 0x004
79 #define SCC_REG_FEATURE 0x004
80 #define SCC_REG_NSECT 0x008
81 #define SCC_REG_LBAL 0x00C
82 #define SCC_REG_LBAM 0x010
83 #define SCC_REG_LBAH 0x014
84 #define SCC_REG_DEVICE 0x018
85 #define SCC_REG_STATUS 0x01C
86 #define SCC_REG_CMD 0x01C
87 #define SCC_REG_ALTSTATUS 0x020
90 #define TDVHSEL_MASTER 0x00000001
91 #define TDVHSEL_SLAVE 0x00000004
93 #define MODE_JCUSFEN 0x00000080
95 #define ECMODE_VALUE 0x01
97 #define CCKCTRL_ATARESET 0x00040000
98 #define CCKCTRL_BUFCNT 0x00020000
99 #define CCKCTRL_CRST 0x00010000
100 #define CCKCTRL_OCLKEN 0x00000100
101 #define CCKCTRL_ATACLKOEN 0x00000002
102 #define CCKCTRL_LCLKEN 0x00000001
104 #define QCHCD_IOS_SS 0x00000001
106 #define QCHSD_STPDIAG 0x00020000
108 #define INTMASK_MSK 0xD1000012
109 #define INTSTS_SERROR 0x80000000
110 #define INTSTS_PRERR 0x40000000
111 #define INTSTS_RERR 0x10000000
112 #define INTSTS_ICERR 0x01000000
113 #define INTSTS_BMSINT 0x00000010
114 #define INTSTS_BMHE 0x00000008
115 #define INTSTS_IOIRQS 0x00000004
116 #define INTSTS_INTRQ 0x00000002
117 #define INTSTS_ACTEINT 0x00000001
120 /* PIO transfer mode table */
122 static const unsigned long JCHSTtbl
[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
128 static const unsigned long JCHHTtbl
[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
134 static const unsigned long JCHCTtbl
[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
139 /* DMA transfer mode table */
140 /* JCHDCTM/JCHDCTS */
141 static const unsigned long JCHDCTxtbl
[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
146 /* JCSTWTM/JCSTWTS */
147 static const unsigned long JCSTWTxtbl
[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
153 static const unsigned long JCTSStbl
[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
159 static const unsigned long JCENVTtbl
[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
164 /* JCACTSELS/JCACTSELM */
165 static const unsigned long JCACTSELtbl
[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
170 static const struct pci_device_id scc_pci_tbl
[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2
, PCI_DEVICE_ID_TOSHIBA_SCC_ATA
,
172 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
173 { } /* terminate list */
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
181 * Set PIO mode for device.
184 * None (inherited from caller).
187 static void scc_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
)
189 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
190 void __iomem
*ctrl_base
= ap
->host
->iomap
[SCC_CTRL_BAR
];
191 void __iomem
*cckctrl_port
= ctrl_base
+ SCC_CTL_CCKCTRL
;
192 void __iomem
*piosht_port
= ctrl_base
+ SCC_CTL_PIOSHT
;
193 void __iomem
*pioct_port
= ctrl_base
+ SCC_CTL_PIOCT
;
197 reg
= in_be32(cckctrl_port
);
198 if (reg
& CCKCTRL_ATACLKOEN
)
199 offset
= 1; /* 133MHz */
201 offset
= 0; /* 100MHz */
203 reg
= JCHSTtbl
[offset
][pio
] << 16 | JCHHTtbl
[offset
][pio
];
204 out_be32(piosht_port
, reg
);
205 reg
= JCHCTtbl
[offset
][pio
];
206 out_be32(pioct_port
, reg
);
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
213 * @udma: udma mode, 0 - 6
215 * Set UDMA mode for device.
218 * None (inherited from caller).
221 static void scc_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
223 unsigned int udma
= adev
->dma_mode
;
224 unsigned int is_slave
= (adev
->devno
!= 0);
226 void __iomem
*ctrl_base
= ap
->host
->iomap
[SCC_CTRL_BAR
];
227 void __iomem
*cckctrl_port
= ctrl_base
+ SCC_CTL_CCKCTRL
;
228 void __iomem
*mdmact_port
= ctrl_base
+ SCC_CTL_MDMACT
;
229 void __iomem
*mcrcst_port
= ctrl_base
+ SCC_CTL_MCRCST
;
230 void __iomem
*sdmact_port
= ctrl_base
+ SCC_CTL_SDMACT
;
231 void __iomem
*scrcst_port
= ctrl_base
+ SCC_CTL_SCRCST
;
232 void __iomem
*udenvt_port
= ctrl_base
+ SCC_CTL_UDENVT
;
233 void __iomem
*tdvhsel_port
= ctrl_base
+ SCC_CTL_TDVHSEL
;
236 if (in_be32(cckctrl_port
) & CCKCTRL_ATACLKOEN
)
237 offset
= 1; /* 133MHz */
239 offset
= 0; /* 100MHz */
241 if (speed
>= XFER_UDMA_0
)
242 idx
= speed
- XFER_UDMA_0
;
247 out_be32(sdmact_port
, JCHDCTxtbl
[offset
][idx
]);
248 out_be32(scrcst_port
, JCSTWTxtbl
[offset
][idx
]);
249 out_be32(tdvhsel_port
,
250 (in_be32(tdvhsel_port
) & ~TDVHSEL_SLAVE
) | (JCACTSELtbl
[offset
][idx
] << 2));
252 out_be32(mdmact_port
, JCHDCTxtbl
[offset
][idx
]);
253 out_be32(mcrcst_port
, JCSTWTxtbl
[offset
][idx
]);
254 out_be32(tdvhsel_port
,
255 (in_be32(tdvhsel_port
) & ~TDVHSEL_MASTER
) | JCACTSELtbl
[offset
][idx
]);
257 out_be32(udenvt_port
,
258 JCTSStbl
[offset
][idx
] << 16 | JCENVTtbl
[offset
][idx
]);
261 unsigned long scc_mode_filter(struct ata_device
*adev
, unsigned long mask
)
263 /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
264 if (adev
->class == ATA_DEV_ATAPI
&&
265 (mask
& (0xE0 << ATA_SHIFT_UDMA
))) {
266 printk(KERN_INFO
"%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME
);
267 mask
&= ~(0xE0 << ATA_SHIFT_UDMA
);
269 return ata_pci_default_filter(adev
, mask
);
273 * scc_tf_load - send taskfile registers to host controller
274 * @ap: Port to which output is sent
275 * @tf: ATA taskfile register set
277 * Note: Original code is ata_tf_load().
280 static void scc_tf_load (struct ata_port
*ap
, const struct ata_taskfile
*tf
)
282 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
283 unsigned int is_addr
= tf
->flags
& ATA_TFLAG_ISADDR
;
285 if (tf
->ctl
!= ap
->last_ctl
) {
286 out_be32(ioaddr
->ctl_addr
, tf
->ctl
);
287 ap
->last_ctl
= tf
->ctl
;
291 if (is_addr
&& (tf
->flags
& ATA_TFLAG_LBA48
)) {
292 out_be32(ioaddr
->feature_addr
, tf
->hob_feature
);
293 out_be32(ioaddr
->nsect_addr
, tf
->hob_nsect
);
294 out_be32(ioaddr
->lbal_addr
, tf
->hob_lbal
);
295 out_be32(ioaddr
->lbam_addr
, tf
->hob_lbam
);
296 out_be32(ioaddr
->lbah_addr
, tf
->hob_lbah
);
297 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
306 out_be32(ioaddr
->feature_addr
, tf
->feature
);
307 out_be32(ioaddr
->nsect_addr
, tf
->nsect
);
308 out_be32(ioaddr
->lbal_addr
, tf
->lbal
);
309 out_be32(ioaddr
->lbam_addr
, tf
->lbam
);
310 out_be32(ioaddr
->lbah_addr
, tf
->lbah
);
311 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
319 if (tf
->flags
& ATA_TFLAG_DEVICE
) {
320 out_be32(ioaddr
->device_addr
, tf
->device
);
321 VPRINTK("device 0x%X\n", tf
->device
);
328 * scc_check_status - Read device status reg & clear interrupt
329 * @ap: port where the device is
331 * Note: Original code is ata_check_status().
334 static u8
scc_check_status (struct ata_port
*ap
)
336 return in_be32(ap
->ioaddr
.status_addr
);
340 * scc_tf_read - input device's ATA taskfile shadow registers
341 * @ap: Port from which input is read
342 * @tf: ATA taskfile register set for storing input
344 * Note: Original code is ata_tf_read().
347 static void scc_tf_read (struct ata_port
*ap
, struct ata_taskfile
*tf
)
349 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
351 tf
->command
= scc_check_status(ap
);
352 tf
->feature
= in_be32(ioaddr
->error_addr
);
353 tf
->nsect
= in_be32(ioaddr
->nsect_addr
);
354 tf
->lbal
= in_be32(ioaddr
->lbal_addr
);
355 tf
->lbam
= in_be32(ioaddr
->lbam_addr
);
356 tf
->lbah
= in_be32(ioaddr
->lbah_addr
);
357 tf
->device
= in_be32(ioaddr
->device_addr
);
359 if (tf
->flags
& ATA_TFLAG_LBA48
) {
360 out_be32(ioaddr
->ctl_addr
, tf
->ctl
| ATA_HOB
);
361 tf
->hob_feature
= in_be32(ioaddr
->error_addr
);
362 tf
->hob_nsect
= in_be32(ioaddr
->nsect_addr
);
363 tf
->hob_lbal
= in_be32(ioaddr
->lbal_addr
);
364 tf
->hob_lbam
= in_be32(ioaddr
->lbam_addr
);
365 tf
->hob_lbah
= in_be32(ioaddr
->lbah_addr
);
370 * scc_exec_command - issue ATA command to host controller
371 * @ap: port to which command is being issued
372 * @tf: ATA taskfile register set
374 * Note: Original code is ata_exec_command().
377 static void scc_exec_command (struct ata_port
*ap
,
378 const struct ata_taskfile
*tf
)
380 DPRINTK("ata%u: cmd 0x%X\n", ap
->print_id
, tf
->command
);
382 out_be32(ap
->ioaddr
.command_addr
, tf
->command
);
387 * scc_check_altstatus - Read device alternate status reg
388 * @ap: port where the device is
391 static u8
scc_check_altstatus (struct ata_port
*ap
)
393 return in_be32(ap
->ioaddr
.altstatus_addr
);
397 * scc_std_dev_select - Select device 0/1 on ATA bus
398 * @ap: ATA channel to manipulate
399 * @device: ATA device (numbered from zero) to select
401 * Note: Original code is ata_std_dev_select().
404 static void scc_std_dev_select (struct ata_port
*ap
, unsigned int device
)
409 tmp
= ATA_DEVICE_OBS
;
411 tmp
= ATA_DEVICE_OBS
| ATA_DEV1
;
413 out_be32(ap
->ioaddr
.device_addr
, tmp
);
418 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
419 * @qc: Info associated with this ATA transaction.
421 * Note: Original code is ata_bmdma_setup().
424 static void scc_bmdma_setup (struct ata_queued_cmd
*qc
)
426 struct ata_port
*ap
= qc
->ap
;
427 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
429 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
431 /* load PRD table addr */
432 out_be32(mmio
+ SCC_DMA_TABLE_OFS
, ap
->prd_dma
);
434 /* specify data direction, triple-check start bit is clear */
435 dmactl
= in_be32(mmio
+ SCC_DMA_CMD
);
436 dmactl
&= ~(ATA_DMA_WR
| ATA_DMA_START
);
438 dmactl
|= ATA_DMA_WR
;
439 out_be32(mmio
+ SCC_DMA_CMD
, dmactl
);
441 /* issue r/w command */
442 ap
->ops
->exec_command(ap
, &qc
->tf
);
446 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
447 * @qc: Info associated with this ATA transaction.
449 * Note: Original code is ata_bmdma_start().
452 static void scc_bmdma_start (struct ata_queued_cmd
*qc
)
454 struct ata_port
*ap
= qc
->ap
;
456 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
458 /* start host DMA transaction */
459 dmactl
= in_be32(mmio
+ SCC_DMA_CMD
);
460 out_be32(mmio
+ SCC_DMA_CMD
, dmactl
| ATA_DMA_START
);
464 * scc_devchk - PATA device presence detection
465 * @ap: ATA channel to examine
466 * @device: Device to examine (starting at zero)
468 * Note: Original code is ata_devchk().
471 static unsigned int scc_devchk (struct ata_port
*ap
,
474 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
477 ap
->ops
->dev_select(ap
, device
);
479 out_be32(ioaddr
->nsect_addr
, 0x55);
480 out_be32(ioaddr
->lbal_addr
, 0xaa);
482 out_be32(ioaddr
->nsect_addr
, 0xaa);
483 out_be32(ioaddr
->lbal_addr
, 0x55);
485 out_be32(ioaddr
->nsect_addr
, 0x55);
486 out_be32(ioaddr
->lbal_addr
, 0xaa);
488 nsect
= in_be32(ioaddr
->nsect_addr
);
489 lbal
= in_be32(ioaddr
->lbal_addr
);
491 if ((nsect
== 0x55) && (lbal
== 0xaa))
492 return 1; /* we found a device */
494 return 0; /* nothing found */
498 * scc_bus_post_reset - PATA device post reset
500 * Note: Original code is ata_bus_post_reset().
503 static int scc_bus_post_reset(struct ata_port
*ap
, unsigned int devmask
,
504 unsigned long deadline
)
506 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
507 unsigned int dev0
= devmask
& (1 << 0);
508 unsigned int dev1
= devmask
& (1 << 1);
511 /* if device 0 was found in ata_devchk, wait for its
515 rc
= ata_wait_ready(ap
, deadline
);
516 if (rc
&& rc
!= -ENODEV
)
520 /* if device 1 was found in ata_devchk, wait for
521 * register access, then wait for BSY to clear
526 ap
->ops
->dev_select(ap
, 1);
527 nsect
= in_be32(ioaddr
->nsect_addr
);
528 lbal
= in_be32(ioaddr
->lbal_addr
);
529 if ((nsect
== 1) && (lbal
== 1))
531 if (time_after(jiffies
, deadline
))
533 msleep(50); /* give drive a breather */
536 rc
= ata_wait_ready(ap
, deadline
);
537 if (rc
&& rc
!= -ENODEV
)
541 /* is all this really necessary? */
542 ap
->ops
->dev_select(ap
, 0);
544 ap
->ops
->dev_select(ap
, 1);
546 ap
->ops
->dev_select(ap
, 0);
552 * scc_bus_softreset - PATA device software reset
554 * Note: Original code is ata_bus_softreset().
557 static unsigned int scc_bus_softreset(struct ata_port
*ap
, unsigned int devmask
,
558 unsigned long deadline
)
560 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
562 DPRINTK("ata%u: bus reset via SRST\n", ap
->print_id
);
564 /* software reset. causes dev0 to be selected */
565 out_be32(ioaddr
->ctl_addr
, ap
->ctl
);
567 out_be32(ioaddr
->ctl_addr
, ap
->ctl
| ATA_SRST
);
569 out_be32(ioaddr
->ctl_addr
, ap
->ctl
);
571 /* spec mandates ">= 2ms" before checking status.
572 * We wait 150ms, because that was the magic delay used for
573 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
574 * between when the ATA command register is written, and then
575 * status is checked. Because waiting for "a while" before
576 * checking status is fine, post SRST, we perform this magic
577 * delay here as well.
579 * Old drivers/ide uses the 2mS rule and then waits for ready
583 /* Before we perform post reset processing we want to see if
584 * the bus shows 0xFF because the odd clown forgets the D7
587 if (scc_check_status(ap
) == 0xFF)
590 scc_bus_post_reset(ap
, devmask
, deadline
);
596 * scc_std_softreset - reset host port via ATA SRST
598 * @classes: resulting classes of attached devices
599 * @deadline: deadline jiffies for the operation
601 * Note: Original code is ata_std_softreset().
604 static int scc_std_softreset (struct ata_port
*ap
, unsigned int *classes
,
605 unsigned long deadline
)
607 unsigned int slave_possible
= ap
->flags
& ATA_FLAG_SLAVE_POSS
;
608 unsigned int devmask
= 0, err_mask
;
613 if (ata_port_offline(ap
)) {
614 classes
[0] = ATA_DEV_NONE
;
618 /* determine if device 0/1 are present */
619 if (scc_devchk(ap
, 0))
621 if (slave_possible
&& scc_devchk(ap
, 1))
624 /* select device 0 again */
625 ap
->ops
->dev_select(ap
, 0);
627 /* issue bus reset */
628 DPRINTK("about to softreset, devmask=%x\n", devmask
);
629 err_mask
= scc_bus_softreset(ap
, devmask
, deadline
);
631 ata_port_printk(ap
, KERN_ERR
, "SRST failed (err_mask=0x%x)\n",
636 /* determine by signature whether we have ATA or ATAPI devices */
637 classes
[0] = ata_dev_try_classify(ap
, 0, &err
);
638 if (slave_possible
&& err
!= 0x81)
639 classes
[1] = ata_dev_try_classify(ap
, 1, &err
);
642 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes
[0], classes
[1]);
647 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
648 * @qc: Command we are ending DMA for
651 static void scc_bmdma_stop (struct ata_queued_cmd
*qc
)
653 struct ata_port
*ap
= qc
->ap
;
654 void __iomem
*ctrl_base
= ap
->host
->iomap
[SCC_CTRL_BAR
];
655 void __iomem
*bmid_base
= ap
->host
->iomap
[SCC_BMID_BAR
];
659 reg
= in_be32(bmid_base
+ SCC_DMA_INTST
);
661 if (reg
& INTSTS_SERROR
) {
662 printk(KERN_WARNING
"%s: SERROR\n", DRV_NAME
);
663 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_SERROR
|INTSTS_BMSINT
);
664 out_be32(bmid_base
+ SCC_DMA_CMD
,
665 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
669 if (reg
& INTSTS_PRERR
) {
671 maea0
= in_be32(ctrl_base
+ SCC_CTL_MAEA0
);
672 maec0
= in_be32(ctrl_base
+ SCC_CTL_MAEC0
);
673 printk(KERN_WARNING
"%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME
, maea0
, maec0
);
674 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_PRERR
|INTSTS_BMSINT
);
675 out_be32(bmid_base
+ SCC_DMA_CMD
,
676 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
680 if (reg
& INTSTS_RERR
) {
681 printk(KERN_WARNING
"%s: Response Error\n", DRV_NAME
);
682 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_RERR
|INTSTS_BMSINT
);
683 out_be32(bmid_base
+ SCC_DMA_CMD
,
684 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
688 if (reg
& INTSTS_ICERR
) {
689 out_be32(bmid_base
+ SCC_DMA_CMD
,
690 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
691 printk(KERN_WARNING
"%s: Illegal Configuration\n", DRV_NAME
);
692 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_ICERR
|INTSTS_BMSINT
);
696 if (reg
& INTSTS_BMSINT
) {
697 unsigned int classes
;
698 unsigned long deadline
= jiffies
+ ATA_TMOUT_BOOT
;
699 printk(KERN_WARNING
"%s: Internal Bus Error\n", DRV_NAME
);
700 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_BMSINT
);
702 scc_std_softreset(ap
, &classes
, deadline
);
706 if (reg
& INTSTS_BMHE
) {
707 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_BMHE
);
711 if (reg
& INTSTS_ACTEINT
) {
712 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_ACTEINT
);
716 if (reg
& INTSTS_IOIRQS
) {
717 out_be32(bmid_base
+ SCC_DMA_INTST
, INTSTS_IOIRQS
);
723 /* clear start/stop bit */
724 out_be32(bmid_base
+ SCC_DMA_CMD
,
725 in_be32(bmid_base
+ SCC_DMA_CMD
) & ~ATA_DMA_START
);
727 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
728 ata_altstatus(ap
); /* dummy read */
732 * scc_bmdma_status - Read PCI IDE BMDMA status
733 * @ap: Port associated with this ATA transaction.
736 static u8
scc_bmdma_status (struct ata_port
*ap
)
738 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
739 u8 host_stat
= in_be32(mmio
+ SCC_DMA_STATUS
);
740 u32 int_status
= in_be32(mmio
+ SCC_DMA_INTST
);
741 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
742 static int retry
= 0;
744 /* return if IOS_SS is cleared */
745 if (!(in_be32(mmio
+ SCC_DMA_CMD
) & ATA_DMA_START
))
748 /* errata A252,A308 workaround: Step4 */
749 if ((ata_altstatus(ap
) & ATA_ERR
) && (int_status
& INTSTS_INTRQ
))
750 return (host_stat
| ATA_DMA_INTR
);
752 /* errata A308 workaround Step5 */
753 if (int_status
& INTSTS_IOIRQS
) {
754 host_stat
|= ATA_DMA_INTR
;
756 /* We don't check ATAPI DMA because it is limited to UDMA4 */
757 if ((qc
->tf
.protocol
== ATA_PROT_DMA
&&
758 qc
->dev
->xfer_mode
> XFER_UDMA_4
)) {
759 if (!(int_status
& INTSTS_ACTEINT
)) {
760 printk(KERN_WARNING
"ata%u: operation failed (transfer data loss)\n",
762 host_stat
|= ATA_DMA_ERR
;
764 ap
->udma_mask
&= ~(1 << qc
->dev
->xfer_mode
);
774 * scc_data_xfer - Transfer data by PIO
775 * @adev: device for this I/O
777 * @buflen: buffer length
778 * @write_data: read/write
780 * Note: Original code is ata_data_xfer().
783 static void scc_data_xfer (struct ata_device
*adev
, unsigned char *buf
,
784 unsigned int buflen
, int write_data
)
786 struct ata_port
*ap
= adev
->ap
;
787 unsigned int words
= buflen
>> 1;
789 u16
*buf16
= (u16
*) buf
;
790 void __iomem
*mmio
= ap
->ioaddr
.data_addr
;
792 /* Transfer multiple of 2 bytes */
794 for (i
= 0; i
< words
; i
++)
795 out_be32(mmio
, cpu_to_le16(buf16
[i
]));
797 for (i
= 0; i
< words
; i
++)
798 buf16
[i
] = le16_to_cpu(in_be32(mmio
));
801 /* Transfer trailing 1 byte, if any. */
802 if (unlikely(buflen
& 0x01)) {
803 u16 align_buf
[1] = { 0 };
804 unsigned char *trailing_buf
= buf
+ buflen
- 1;
807 memcpy(align_buf
, trailing_buf
, 1);
808 out_be32(mmio
, cpu_to_le16(align_buf
[0]));
810 align_buf
[0] = le16_to_cpu(in_be32(mmio
));
811 memcpy(trailing_buf
, align_buf
, 1);
817 * scc_irq_on - Enable interrupts on a port.
818 * @ap: Port on which interrupts are enabled.
820 * Note: Original code is ata_irq_on().
823 static u8
scc_irq_on (struct ata_port
*ap
)
825 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
828 ap
->ctl
&= ~ATA_NIEN
;
829 ap
->last_ctl
= ap
->ctl
;
831 out_be32(ioaddr
->ctl_addr
, ap
->ctl
);
832 tmp
= ata_wait_idle(ap
);
834 ap
->ops
->irq_clear(ap
);
840 * scc_irq_ack - Acknowledge a device interrupt.
841 * @ap: Port on which interrupts are enabled.
843 * Note: Original code is ata_irq_ack().
846 static u8
scc_irq_ack (struct ata_port
*ap
, unsigned int chk_drq
)
848 unsigned int bits
= chk_drq
? ATA_BUSY
| ATA_DRQ
: ATA_BUSY
;
849 u8 host_stat
, post_stat
, status
;
851 status
= ata_busy_wait(ap
, bits
, 1000);
854 printk(KERN_ERR
"abnormal status 0x%X\n", status
);
856 /* get controller status; clear intr, err bits */
857 host_stat
= in_be32(ap
->ioaddr
.bmdma_addr
+ SCC_DMA_STATUS
);
858 out_be32(ap
->ioaddr
.bmdma_addr
+ SCC_DMA_STATUS
,
859 host_stat
| ATA_DMA_INTR
| ATA_DMA_ERR
);
861 post_stat
= in_be32(ap
->ioaddr
.bmdma_addr
+ SCC_DMA_STATUS
);
863 if (ata_msg_intr(ap
))
864 printk(KERN_INFO
"%s: irq ack: host_stat 0x%X, new host_stat 0x%X, drv_stat 0x%X\n",
866 host_stat
, post_stat
, status
);
872 * scc_bmdma_freeze - Freeze BMDMA controller port
873 * @ap: port to freeze
875 * Note: Original code is ata_bmdma_freeze().
878 static void scc_bmdma_freeze (struct ata_port
*ap
)
880 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
883 ap
->last_ctl
= ap
->ctl
;
885 out_be32(ioaddr
->ctl_addr
, ap
->ctl
);
887 /* Under certain circumstances, some controllers raise IRQ on
888 * ATA_NIEN manipulation. Also, many controllers fail to mask
889 * previously pending IRQ on ATA_NIEN assertion. Clear it.
893 ap
->ops
->irq_clear(ap
);
897 * scc_pata_prereset - prepare for reset
898 * @ap: ATA port to be reset
899 * @deadline: deadline jiffies for the operation
902 static int scc_pata_prereset(struct ata_port
*ap
, unsigned long deadline
)
904 ap
->cbl
= ATA_CBL_PATA80
;
905 return ata_std_prereset(ap
, deadline
);
909 * scc_std_postreset - standard postreset callback
910 * @ap: the target ata_port
911 * @classes: classes of attached devices
913 * Note: Original code is ata_std_postreset().
916 static void scc_std_postreset (struct ata_port
*ap
, unsigned int *classes
)
920 /* is double-select really necessary? */
921 if (classes
[0] != ATA_DEV_NONE
)
922 ap
->ops
->dev_select(ap
, 1);
923 if (classes
[1] != ATA_DEV_NONE
)
924 ap
->ops
->dev_select(ap
, 0);
926 /* bail out if no device is present */
927 if (classes
[0] == ATA_DEV_NONE
&& classes
[1] == ATA_DEV_NONE
) {
928 DPRINTK("EXIT, no device\n");
932 /* set up device control */
933 if (ap
->ioaddr
.ctl_addr
)
934 out_be32(ap
->ioaddr
.ctl_addr
, ap
->ctl
);
940 * scc_error_handler - Stock error handler for BMDMA controller
941 * @ap: port to handle error for
944 static void scc_error_handler (struct ata_port
*ap
)
946 ata_bmdma_drive_eh(ap
, scc_pata_prereset
, scc_std_softreset
, NULL
,
951 * scc_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
952 * @ap: Port associated with this ATA transaction.
954 * Note: Original code is ata_bmdma_irq_clear().
957 static void scc_bmdma_irq_clear (struct ata_port
*ap
)
959 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
964 out_be32(mmio
+ SCC_DMA_STATUS
, in_be32(mmio
+ SCC_DMA_STATUS
));
968 * scc_port_start - Set port up for dma.
969 * @ap: Port to initialize
971 * Allocate space for PRD table using ata_port_start().
972 * Set PRD table address for PTERADD. (PRD Transfer End Read)
975 static int scc_port_start (struct ata_port
*ap
)
977 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
980 rc
= ata_port_start(ap
);
984 out_be32(mmio
+ SCC_DMA_PTERADD
, ap
->prd_dma
);
989 * scc_port_stop - Undo scc_port_start()
990 * @ap: Port to shut down
995 static void scc_port_stop (struct ata_port
*ap
)
997 void __iomem
*mmio
= ap
->ioaddr
.bmdma_addr
;
999 out_be32(mmio
+ SCC_DMA_PTERADD
, 0);
1002 static struct scsi_host_template scc_sht
= {
1003 .module
= THIS_MODULE
,
1005 .ioctl
= ata_scsi_ioctl
,
1006 .queuecommand
= ata_scsi_queuecmd
,
1007 .can_queue
= ATA_DEF_QUEUE
,
1008 .this_id
= ATA_SHT_THIS_ID
,
1009 .sg_tablesize
= LIBATA_MAX_PRD
,
1010 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
1011 .emulated
= ATA_SHT_EMULATED
,
1012 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
1013 .proc_name
= DRV_NAME
,
1014 .dma_boundary
= ATA_DMA_BOUNDARY
,
1015 .slave_configure
= ata_scsi_slave_config
,
1016 .slave_destroy
= ata_scsi_slave_destroy
,
1017 .bios_param
= ata_std_bios_param
,
1020 static const struct ata_port_operations scc_pata_ops
= {
1021 .port_disable
= ata_port_disable
,
1022 .set_piomode
= scc_set_piomode
,
1023 .set_dmamode
= scc_set_dmamode
,
1024 .mode_filter
= scc_mode_filter
,
1026 .tf_load
= scc_tf_load
,
1027 .tf_read
= scc_tf_read
,
1028 .exec_command
= scc_exec_command
,
1029 .check_status
= scc_check_status
,
1030 .check_altstatus
= scc_check_altstatus
,
1031 .dev_select
= scc_std_dev_select
,
1033 .bmdma_setup
= scc_bmdma_setup
,
1034 .bmdma_start
= scc_bmdma_start
,
1035 .bmdma_stop
= scc_bmdma_stop
,
1036 .bmdma_status
= scc_bmdma_status
,
1037 .data_xfer
= scc_data_xfer
,
1039 .qc_prep
= ata_qc_prep
,
1040 .qc_issue
= ata_qc_issue_prot
,
1042 .freeze
= scc_bmdma_freeze
,
1043 .error_handler
= scc_error_handler
,
1044 .post_internal_cmd
= scc_bmdma_stop
,
1046 .irq_clear
= scc_bmdma_irq_clear
,
1047 .irq_on
= scc_irq_on
,
1048 .irq_ack
= scc_irq_ack
,
1050 .port_start
= scc_port_start
,
1051 .port_stop
= scc_port_stop
,
1054 static struct ata_port_info scc_port_info
[] = {
1056 .flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_MMIO
| ATA_FLAG_NO_LEGACY
,
1057 .pio_mask
= 0x1f, /* pio0-4 */
1059 .udma_mask
= ATA_UDMA6
,
1060 .port_ops
= &scc_pata_ops
,
1065 * scc_reset_controller - initialize SCC PATA controller.
1068 static int scc_reset_controller(struct ata_host
*host
)
1070 void __iomem
*ctrl_base
= host
->iomap
[SCC_CTRL_BAR
];
1071 void __iomem
*bmid_base
= host
->iomap
[SCC_BMID_BAR
];
1072 void __iomem
*cckctrl_port
= ctrl_base
+ SCC_CTL_CCKCTRL
;
1073 void __iomem
*mode_port
= ctrl_base
+ SCC_CTL_MODEREG
;
1074 void __iomem
*ecmode_port
= ctrl_base
+ SCC_CTL_ECMODE
;
1075 void __iomem
*intmask_port
= bmid_base
+ SCC_DMA_INTMASK
;
1076 void __iomem
*dmastatus_port
= bmid_base
+ SCC_DMA_STATUS
;
1079 out_be32(cckctrl_port
, reg
);
1080 reg
|= CCKCTRL_ATACLKOEN
;
1081 out_be32(cckctrl_port
, reg
);
1082 reg
|= CCKCTRL_LCLKEN
| CCKCTRL_OCLKEN
;
1083 out_be32(cckctrl_port
, reg
);
1084 reg
|= CCKCTRL_CRST
;
1085 out_be32(cckctrl_port
, reg
);
1088 reg
= in_be32(cckctrl_port
);
1089 if (reg
& CCKCTRL_CRST
)
1094 reg
|= CCKCTRL_ATARESET
;
1095 out_be32(cckctrl_port
, reg
);
1096 out_be32(ecmode_port
, ECMODE_VALUE
);
1097 out_be32(mode_port
, MODE_JCUSFEN
);
1098 out_be32(intmask_port
, INTMASK_MSK
);
1100 if (in_be32(dmastatus_port
) & QCHSD_STPDIAG
) {
1101 printk(KERN_WARNING
"%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME
);
1109 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1110 * @ioaddr: IO address structure to be initialized
1111 * @base: base address of BMID region
1114 static void scc_setup_ports (struct ata_ioports
*ioaddr
, void __iomem
*base
)
1116 ioaddr
->cmd_addr
= base
+ SCC_REG_CMD_ADDR
;
1117 ioaddr
->altstatus_addr
= ioaddr
->cmd_addr
+ SCC_REG_ALTSTATUS
;
1118 ioaddr
->ctl_addr
= ioaddr
->cmd_addr
+ SCC_REG_ALTSTATUS
;
1119 ioaddr
->bmdma_addr
= base
;
1120 ioaddr
->data_addr
= ioaddr
->cmd_addr
+ SCC_REG_DATA
;
1121 ioaddr
->error_addr
= ioaddr
->cmd_addr
+ SCC_REG_ERR
;
1122 ioaddr
->feature_addr
= ioaddr
->cmd_addr
+ SCC_REG_FEATURE
;
1123 ioaddr
->nsect_addr
= ioaddr
->cmd_addr
+ SCC_REG_NSECT
;
1124 ioaddr
->lbal_addr
= ioaddr
->cmd_addr
+ SCC_REG_LBAL
;
1125 ioaddr
->lbam_addr
= ioaddr
->cmd_addr
+ SCC_REG_LBAM
;
1126 ioaddr
->lbah_addr
= ioaddr
->cmd_addr
+ SCC_REG_LBAH
;
1127 ioaddr
->device_addr
= ioaddr
->cmd_addr
+ SCC_REG_DEVICE
;
1128 ioaddr
->status_addr
= ioaddr
->cmd_addr
+ SCC_REG_STATUS
;
1129 ioaddr
->command_addr
= ioaddr
->cmd_addr
+ SCC_REG_CMD
;
1132 static int scc_host_init(struct ata_host
*host
)
1134 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1137 rc
= scc_reset_controller(host
);
1141 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
1144 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
1148 scc_setup_ports(&host
->ports
[0]->ioaddr
, host
->iomap
[SCC_BMID_BAR
]);
1150 pci_set_master(pdev
);
1156 * scc_init_one - Register SCC PATA device with kernel services
1157 * @pdev: PCI device to register
1158 * @ent: Entry in scc_pci_tbl matching with @pdev
1161 * Inherited from PCI layer (may sleep).
1164 * Zero on success, or -ERRNO value.
1167 static int scc_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1169 static int printed_version
;
1170 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1171 const struct ata_port_info
*ppi
[] = { &scc_port_info
[board_idx
], NULL
};
1172 struct ata_host
*host
;
1175 if (!printed_version
++)
1176 dev_printk(KERN_DEBUG
, &pdev
->dev
,
1177 "version " DRV_VERSION
"\n");
1179 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, 1);
1183 rc
= pcim_enable_device(pdev
);
1187 rc
= pcim_iomap_regions(pdev
, (1 << SCC_CTRL_BAR
) | (1 << SCC_BMID_BAR
), DRV_NAME
);
1189 pcim_pin_device(pdev
);
1192 host
->iomap
= pcim_iomap_table(pdev
);
1194 rc
= scc_host_init(host
);
1198 return ata_host_activate(host
, pdev
->irq
, ata_interrupt
, IRQF_SHARED
,
1202 static struct pci_driver scc_pci_driver
= {
1204 .id_table
= scc_pci_tbl
,
1205 .probe
= scc_init_one
,
1206 .remove
= ata_pci_remove_one
,
1208 .suspend
= ata_pci_device_suspend
,
1209 .resume
= ata_pci_device_resume
,
1213 static int __init
scc_init (void)
1217 DPRINTK("pci_register_driver\n");
1218 rc
= pci_register_driver(&scc_pci_driver
);
1226 static void __exit
scc_exit (void)
1228 pci_unregister_driver(&scc_pci_driver
);
1231 module_init(scc_init
);
1232 module_exit(scc_exit
);
1234 MODULE_AUTHOR("Toshiba corp");
1235 MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1236 MODULE_LICENSE("GPL");
1237 MODULE_DEVICE_TABLE(pci
, scc_pci_tbl
);
1238 MODULE_VERSION(DRV_VERSION
);