drivers/char/drm/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 /* General customization:
  34  */
  35
  36 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  37
  38 #define DRIVER_NAME             "i915"
  39 #define DRIVER_DESC             "Intel Graphics"
  40 #define DRIVER_DATE             "20060119"
  41
  42 /* Interface history:
  43  *
  44  * 1.1: Original.
  45  * 1.2: Add Power Management
  46  * 1.3: Add vblank support
  47  * 1.4: Fix cmdbuffer path, add heap destroy
  48  * 1.5: Add vblank pipe configuration
  49  */
  50 #define DRIVER_MAJOR            1
  51 #define DRIVER_MINOR            5
  52 #define DRIVER_PATCHLEVEL       0
  53
  54 typedef struct _drm_i915_ring_buffer {
  55         int tail_mask;
  56         unsigned long Start;
  57         unsigned long End;
  58         unsigned long Size;
  59         u8 *virtual_start;
  60         int head;
  61         int tail;
  62         int space;
  63         drm_local_map_t map;
  64 } drm_i915_ring_buffer_t;
  65
  66 struct mem_block {
  67         struct mem_block *next;
  68         struct mem_block *prev;
  69         int start;
  70         int size;
  71         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
  72 };
  73
  74 typedef struct drm_i915_private {
  75         drm_local_map_t *sarea;
  76         drm_local_map_t *mmio_map;
  77
  78         drm_i915_sarea_t *sarea_priv;
  79         drm_i915_ring_buffer_t ring;
  80
  81         drm_dma_handle_t *status_page_dmah;
  82         void *hw_status_page;
  83         dma_addr_t dma_status_page;
  84         unsigned long counter;
  85
  86         int back_offset;
  87         int front_offset;
  88         int current_page;
  89         int page_flipping;
  90         int use_mi_batchbuffer_start;
  91
  92         wait_queue_head_t irq_queue;
  93         atomic_t irq_received;
  94         atomic_t irq_emitted;
  95
  96         int tex_lru_log_granularity;
  97         int allow_batchbuffer;
  98         struct mem_block *agp_heap;
  99         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 100         int vblank_pipe;
 101 } drm_i915_private_t;
 102
 103 extern drm_ioctl_desc_t i915_ioctls[];
 104 extern int i915_max_ioctl;
 105
 106                                 /* i915_dma.c */
 107 extern void i915_kernel_lost_context(drm_device_t * dev);
 108 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 109 extern void i915_driver_lastclose(drm_device_t * dev);
 110 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);
 111 extern int i915_driver_device_is_agp(drm_device_t * dev);
 112 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 113                               unsigned long arg);
 114
 115 /* i915_irq.c */
 116 extern int i915_irq_emit(DRM_IOCTL_ARGS);
 117 extern int i915_irq_wait(DRM_IOCTL_ARGS);
 118
 119 extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
 120 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 121 extern void i915_driver_irq_preinstall(drm_device_t * dev);
 122 extern void i915_driver_irq_postinstall(drm_device_t * dev);
 123 extern void i915_driver_irq_uninstall(drm_device_t * dev);
 124 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);
 125 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);
 126
 127 /* i915_mem.c */
 128 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
 129 extern int i915_mem_free(DRM_IOCTL_ARGS);
 130 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
 131 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
 132 extern void i915_mem_takedown(struct mem_block **heap);
 133 extern void i915_mem_release(drm_device_t * dev,
 134                              DRMFILE filp, struct mem_block *heap);
 135
 136 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
 137 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 138 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
 139 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
 140
 141 #define I915_VERBOSE 0
 142
 143 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 144                         volatile char *virt;
 145
 146 #define BEGIN_LP_RING(n) do {                           \
 147         if (I915_VERBOSE)                               \
 148                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
 149                           n, __FUNCTION__);             \
 150         if (dev_priv->ring.space < n*4)                 \
 151                 i915_wait_ring(dev, n*4, __FUNCTION__);         \
 152         outcount = 0;                                   \
 153         outring = dev_priv->ring.tail;                  \
 154         ringmask = dev_priv->ring.tail_mask;            \
 155         virt = dev_priv->ring.virtual_start;            \
 156 } while (0)
 157
 158 #define OUT_RING(n) do {                                        \
 159         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 160         *(volatile unsigned int *)(virt + outring) = n;         \
 161         outcount++;                                             \
 162         outring += 4;                                           \
 163         outring &= ringmask;                                    \
 164 } while (0)
 165
 166 #define ADVANCE_LP_RING() do {                                          \
 167         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 168         dev_priv->ring.tail = outring;                                  \
 169         dev_priv->ring.space -= outcount * 4;                           \
 170         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
 171 } while(0)
 172
 173 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
 174
 175 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
 176 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
 177 #define CMD_REPORT_HEAD                 (7<<23)
 178 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
 179 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
 180
 181 #define INST_PARSER_CLIENT   0x00000000
 182 #define INST_OP_FLUSH        0x02000000
 183 #define INST_FLUSH_MAP_CACHE 0x00000001
 184
 185 #define BB1_START_ADDR_MASK   (~0x7)
 186 #define BB1_PROTECTED         (1<<0)
 187 #define BB1_UNPROTECTED       (0<<0)
 188 #define BB2_END_ADDR_MASK     (~0x7)
 189
 190 #define I915REG_HWSTAM          0x02098
 191 #define I915REG_INT_IDENTITY_R  0x020a4
 192 #define I915REG_INT_MASK_R      0x020a8
 193 #define I915REG_INT_ENABLE_R    0x020a0
 194
 195 #define SRX_INDEX               0x3c4
 196 #define SRX_DATA                0x3c5
 197 #define SR01                    1
 198 #define SR01_SCREEN_OFF         (1<<5)
 199
 200 #define PPCR                    0x61204
 201 #define PPCR_ON                 (1<<0)
 202
 203 #define DVOB                    0x61140
 204 #define DVOB_ON                 (1<<31)
 205 #define DVOC                    0x61160
 206 #define DVOC_ON                 (1<<31)
 207 #define LVDS                    0x61180
 208 #define LVDS_ON                 (1<<31)
 209
 210 #define ADPA                    0x61100
 211 #define ADPA_DPMS_MASK          (~(3<<10))
 212 #define ADPA_DPMS_ON            (0<<10)
 213 #define ADPA_DPMS_SUSPEND       (1<<10)
 214 #define ADPA_DPMS_STANDBY       (2<<10)
 215 #define ADPA_DPMS_OFF           (3<<10)
 216
 217 #define NOPID                   0x2094
 218 #define LP_RING                 0x2030
 219 #define HP_RING                 0x2040
 220 #define RING_TAIL               0x00
 221 #define TAIL_ADDR               0x001FFFF8
 222 #define RING_HEAD               0x04
 223 #define HEAD_WRAP_COUNT         0xFFE00000
 224 #define HEAD_WRAP_ONE           0x00200000
 225 #define HEAD_ADDR               0x001FFFFC
 226 #define RING_START              0x08
 227 #define START_ADDR              0x0xFFFFF000
 228 #define RING_LEN                0x0C
 229 #define RING_NR_PAGES           0x001FF000
 230 #define RING_REPORT_MASK        0x00000006
 231 #define RING_REPORT_64K         0x00000002
 232 #define RING_REPORT_128K        0x00000004
 233 #define RING_NO_REPORT          0x00000000
 234 #define RING_VALID_MASK         0x00000001
 235 #define RING_VALID              0x00000001
 236 #define RING_INVALID            0x00000000
 237
 238 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 239 #define SC_UPDATE_SCISSOR       (0x1<<1)
 240 #define SC_ENABLE_MASK          (0x1<<0)
 241 #define SC_ENABLE               (0x1<<0)
 242
 243 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 244 #define SCI_YMIN_MASK      (0xffff<<16)
 245 #define SCI_XMIN_MASK      (0xffff<<0)
 246 #define SCI_YMAX_MASK      (0xffff<<16)
 247 #define SCI_XMAX_MASK      (0xffff<<0)
 248
 249 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 250 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 251 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 252 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 253 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 254 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 255 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 256
 257 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
 258 #define MI_BATCH_BUFFER_START   (0x31<<23)
 259 #define MI_BATCH_BUFFER_END     (0xA<<23)
 260 #define MI_BATCH_NON_SECURE     (1)
 261
 262 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
 263 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
 264 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
 265
 266 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
 267
 268 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 269 #define ASYNC_FLIP                (1<<22)
 270
 271 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 272
 273 #define READ_BREADCRUMB(dev_priv) (((u32 *)(dev_priv->hw_status_page))[5])
 274
 275 #endif