2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name
[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version
[] = "1.3";
60 #define MV643XX_ETH_TX_FAST_REFILL
63 * Registers shared between all ports.
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
84 #define UNICAST_PROMISCUOUS_MODE 0x00000001
85 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
91 #define TX_FIFO_EMPTY 0x00000400
92 #define TX_IN_PROGRESS 0x00000080
93 #define PORT_SPEED_MASK 0x00000030
94 #define PORT_SPEED_1000 0x00000010
95 #define PORT_SPEED_100 0x00000020
96 #define PORT_SPEED_10 0x00000000
97 #define FLOW_CONTROL_ENABLED 0x00000008
98 #define FULL_DUPLEX 0x00000004
99 #define LINK_UP 0x00000002
100 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
101 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
103 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
104 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
105 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
106 #define INT_TX_END_0 0x00080000
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x000003fc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
111 #define INT_EXT_LINK_PHY 0x00110000
112 #define INT_EXT_TX 0x000000ff
113 #define INT_MASK(p) (0x0468 + ((p) << 10))
114 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
115 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
116 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
117 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
118 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
119 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
120 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
121 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
122 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
123 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
124 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
125 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
126 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
127 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
128 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
129 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
133 * SDMA configuration register.
135 #define RX_BURST_SIZE_16_64BIT (4 << 1)
136 #define BLM_RX_NO_SWAP (1 << 4)
137 #define BLM_TX_NO_SWAP (1 << 5)
138 #define TX_BURST_SIZE_16_64BIT (4 << 22)
140 #if defined(__BIG_ENDIAN)
141 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
142 RX_BURST_SIZE_16_64BIT | \
143 TX_BURST_SIZE_16_64BIT
144 #elif defined(__LITTLE_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 RX_BURST_SIZE_16_64BIT | \
149 TX_BURST_SIZE_16_64BIT
151 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156 * Port serial control register.
158 #define SET_MII_SPEED_TO_100 (1 << 24)
159 #define SET_GMII_SPEED_TO_1000 (1 << 23)
160 #define SET_FULL_DUPLEX_MODE (1 << 21)
161 #define MAX_RX_PACKET_9700BYTE (5 << 17)
162 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167 #define FORCE_LINK_PASS (1 << 1)
168 #define SERIAL_PORT_ENABLE (1 << 0)
170 #define DEFAULT_RX_QUEUE_SIZE 400
171 #define DEFAULT_TX_QUEUE_SIZE 800
177 #if defined(__BIG_ENDIAN)
179 u16 byte_cnt
; /* Descriptor buffer byte count */
180 u16 buf_size
; /* Buffer size */
181 u32 cmd_sts
; /* Descriptor command status */
182 u32 next_desc_ptr
; /* Next descriptor pointer */
183 u32 buf_ptr
; /* Descriptor buffer pointer */
187 u16 byte_cnt
; /* buffer byte count */
188 u16 l4i_chk
; /* CPU provided TCP checksum */
189 u32 cmd_sts
; /* Command/status field */
190 u32 next_desc_ptr
; /* Pointer to next descriptor */
191 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
193 #elif defined(__LITTLE_ENDIAN)
195 u32 cmd_sts
; /* Descriptor command status */
196 u16 buf_size
; /* Buffer size */
197 u16 byte_cnt
; /* Descriptor buffer byte count */
198 u32 buf_ptr
; /* Descriptor buffer pointer */
199 u32 next_desc_ptr
; /* Next descriptor pointer */
203 u32 cmd_sts
; /* Command/status field */
204 u16 l4i_chk
; /* CPU provided TCP checksum */
205 u16 byte_cnt
; /* buffer byte count */
206 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
207 u32 next_desc_ptr
; /* Pointer to next descriptor */
210 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
213 /* RX & TX descriptor command */
214 #define BUFFER_OWNED_BY_DMA 0x80000000
216 /* RX & TX descriptor status */
217 #define ERROR_SUMMARY 0x00000001
219 /* RX descriptor status */
220 #define LAYER_4_CHECKSUM_OK 0x40000000
221 #define RX_ENABLE_INTERRUPT 0x20000000
222 #define RX_FIRST_DESC 0x08000000
223 #define RX_LAST_DESC 0x04000000
225 /* TX descriptor command */
226 #define TX_ENABLE_INTERRUPT 0x00800000
227 #define GEN_CRC 0x00400000
228 #define TX_FIRST_DESC 0x00200000
229 #define TX_LAST_DESC 0x00100000
230 #define ZERO_PADDING 0x00080000
231 #define GEN_IP_V4_CHECKSUM 0x00040000
232 #define GEN_TCP_UDP_CHECKSUM 0x00020000
233 #define UDP_FRAME 0x00010000
234 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
235 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
237 #define TX_IHL_SHIFT 11
240 /* global *******************************************************************/
241 struct mv643xx_eth_shared_private
{
243 * Ethernet controller base address.
248 * Points at the right SMI instance to use.
250 struct mv643xx_eth_shared_private
*smi
;
253 * Protects access to SMI_REG, which is shared between ports.
255 struct mutex phy_lock
;
258 * If we have access to the error interrupt pin (which is
259 * somewhat misnamed as it not only reflects internal errors
260 * but also reflects SMI completion), use that to wait for
261 * SMI access completion instead of polling the SMI busy bit.
264 wait_queue_head_t smi_busy_wait
;
267 * Per-port MBUS window access register value.
272 * Hardware-specific parameters.
275 int extended_rx_coal_limit
;
276 int tx_bw_control_moved
;
280 /* per-port *****************************************************************/
281 struct mib_counters
{
282 u64 good_octets_received
;
283 u32 bad_octets_received
;
284 u32 internal_mac_transmit_err
;
285 u32 good_frames_received
;
286 u32 bad_frames_received
;
287 u32 broadcast_frames_received
;
288 u32 multicast_frames_received
;
289 u32 frames_64_octets
;
290 u32 frames_65_to_127_octets
;
291 u32 frames_128_to_255_octets
;
292 u32 frames_256_to_511_octets
;
293 u32 frames_512_to_1023_octets
;
294 u32 frames_1024_to_max_octets
;
295 u64 good_octets_sent
;
296 u32 good_frames_sent
;
297 u32 excessive_collision
;
298 u32 multicast_frames_sent
;
299 u32 broadcast_frames_sent
;
300 u32 unrec_mac_control_received
;
302 u32 good_fc_received
;
304 u32 undersize_received
;
305 u32 fragments_received
;
306 u32 oversize_received
;
308 u32 mac_receive_error
;
323 struct rx_desc
*rx_desc_area
;
324 dma_addr_t rx_desc_dma
;
325 int rx_desc_area_size
;
326 struct sk_buff
**rx_skb
;
338 struct tx_desc
*tx_desc_area
;
339 dma_addr_t tx_desc_dma
;
340 int tx_desc_area_size
;
341 struct sk_buff
**tx_skb
;
344 struct mv643xx_eth_private
{
345 struct mv643xx_eth_shared_private
*shared
;
348 struct net_device
*dev
;
354 struct mib_counters mib_counters
;
355 struct work_struct tx_timeout_task
;
356 struct mii_if_info mii
;
361 int default_rx_ring_size
;
362 unsigned long rx_desc_sram_addr
;
363 int rx_desc_sram_size
;
365 struct napi_struct napi
;
366 struct timer_list rx_oom
;
367 struct rx_queue rxq
[8];
372 int default_tx_ring_size
;
373 unsigned long tx_desc_sram_addr
;
374 int tx_desc_sram_size
;
376 struct tx_queue txq
[8];
377 #ifdef MV643XX_ETH_TX_FAST_REFILL
378 int tx_clean_threshold
;
383 /* port register accessors **************************************************/
384 static inline u32
rdl(struct mv643xx_eth_private
*mp
, int offset
)
386 return readl(mp
->shared
->base
+ offset
);
389 static inline void wrl(struct mv643xx_eth_private
*mp
, int offset
, u32 data
)
391 writel(data
, mp
->shared
->base
+ offset
);
395 /* rxq/txq helper functions *************************************************/
396 static struct mv643xx_eth_private
*rxq_to_mp(struct rx_queue
*rxq
)
398 return container_of(rxq
, struct mv643xx_eth_private
, rxq
[rxq
->index
]);
401 static struct mv643xx_eth_private
*txq_to_mp(struct tx_queue
*txq
)
403 return container_of(txq
, struct mv643xx_eth_private
, txq
[txq
->index
]);
406 static void rxq_enable(struct rx_queue
*rxq
)
408 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
409 wrl(mp
, RXQ_COMMAND(mp
->port_num
), 1 << rxq
->index
);
412 static void rxq_disable(struct rx_queue
*rxq
)
414 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
415 u8 mask
= 1 << rxq
->index
;
417 wrl(mp
, RXQ_COMMAND(mp
->port_num
), mask
<< 8);
418 while (rdl(mp
, RXQ_COMMAND(mp
->port_num
)) & mask
)
422 static void txq_reset_hw_ptr(struct tx_queue
*txq
)
424 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
425 int off
= TXQ_CURRENT_DESC_PTR(mp
->port_num
, txq
->index
);
428 addr
= (u32
)txq
->tx_desc_dma
;
429 addr
+= txq
->tx_curr_desc
* sizeof(struct tx_desc
);
433 static void txq_enable(struct tx_queue
*txq
)
435 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
436 wrl(mp
, TXQ_COMMAND(mp
->port_num
), 1 << txq
->index
);
439 static void txq_disable(struct tx_queue
*txq
)
441 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
442 u8 mask
= 1 << txq
->index
;
444 wrl(mp
, TXQ_COMMAND(mp
->port_num
), mask
<< 8);
445 while (rdl(mp
, TXQ_COMMAND(mp
->port_num
)) & mask
)
449 static void __txq_maybe_wake(struct tx_queue
*txq
)
451 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
452 struct netdev_queue
*nq
= netdev_get_tx_queue(mp
->dev
, txq
->index
);
454 if (txq
->tx_ring_size
- txq
->tx_desc_count
>= MAX_SKB_FRAGS
+ 1)
455 netif_tx_wake_queue(nq
);
459 /* rx ***********************************************************************/
460 static void txq_reclaim(struct tx_queue
*txq
, int force
);
462 static int rxq_refill(struct rx_queue
*rxq
, int budget
, int *oom
)
468 * Reserve 2+14 bytes for an ethernet header (the hardware
469 * automatically prepends 2 bytes of dummy data to each
470 * received packet), 16 bytes for up to four VLAN tags, and
471 * 4 bytes for the trailing FCS -- 36 bytes total.
473 skb_size
= rxq_to_mp(rxq
)->dev
->mtu
+ 36;
476 * Make sure that the skb size is a multiple of 8 bytes, as
477 * the lower three bits of the receive descriptor's buffer
478 * size field are ignored by the hardware.
480 skb_size
= (skb_size
+ 7) & ~7;
483 while (refilled
< budget
&& rxq
->rx_desc_count
< rxq
->rx_ring_size
) {
488 skb
= dev_alloc_skb(skb_size
+ dma_get_cache_alignment() - 1);
494 unaligned
= (u32
)skb
->data
& (dma_get_cache_alignment() - 1);
496 skb_reserve(skb
, dma_get_cache_alignment() - unaligned
);
499 rxq
->rx_desc_count
++;
501 rx
= rxq
->rx_used_desc
++;
502 if (rxq
->rx_used_desc
== rxq
->rx_ring_size
)
503 rxq
->rx_used_desc
= 0;
505 rxq
->rx_desc_area
[rx
].buf_ptr
= dma_map_single(NULL
, skb
->data
,
506 skb_size
, DMA_FROM_DEVICE
);
507 rxq
->rx_desc_area
[rx
].buf_size
= skb_size
;
508 rxq
->rx_skb
[rx
] = skb
;
510 rxq
->rx_desc_area
[rx
].cmd_sts
= BUFFER_OWNED_BY_DMA
|
515 * The hardware automatically prepends 2 bytes of
516 * dummy data to each received packet, so that the
517 * IP header ends up 16-byte aligned.
525 static int rxq_process(struct rx_queue
*rxq
, int budget
)
527 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
528 struct net_device_stats
*stats
= &mp
->dev
->stats
;
532 while (rx
< budget
&& rxq
->rx_desc_count
) {
533 struct rx_desc
*rx_desc
;
534 unsigned int cmd_sts
;
537 rx_desc
= &rxq
->rx_desc_area
[rxq
->rx_curr_desc
];
539 cmd_sts
= rx_desc
->cmd_sts
;
540 if (cmd_sts
& BUFFER_OWNED_BY_DMA
)
544 skb
= rxq
->rx_skb
[rxq
->rx_curr_desc
];
545 rxq
->rx_skb
[rxq
->rx_curr_desc
] = NULL
;
548 if (rxq
->rx_curr_desc
== rxq
->rx_ring_size
)
549 rxq
->rx_curr_desc
= 0;
551 dma_unmap_single(NULL
, rx_desc
->buf_ptr
,
552 rx_desc
->buf_size
, DMA_FROM_DEVICE
);
553 rxq
->rx_desc_count
--;
559 * Note that the descriptor byte count includes 2 dummy
560 * bytes automatically inserted by the hardware at the
561 * start of the packet (which we don't count), and a 4
562 * byte CRC at the end of the packet (which we do count).
565 stats
->rx_bytes
+= rx_desc
->byte_cnt
- 2;
568 * In case we received a packet without first / last bits
569 * on, or the error summary bit is set, the packet needs
572 if (((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
573 (RX_FIRST_DESC
| RX_LAST_DESC
))
574 || (cmd_sts
& ERROR_SUMMARY
)) {
577 if ((cmd_sts
& (RX_FIRST_DESC
| RX_LAST_DESC
)) !=
578 (RX_FIRST_DESC
| RX_LAST_DESC
)) {
580 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
581 "received packet spanning "
582 "multiple descriptors\n");
585 if (cmd_sts
& ERROR_SUMMARY
)
591 * The -4 is for the CRC in the trailer of the
594 skb_put(skb
, rx_desc
->byte_cnt
- 2 - 4);
596 if (cmd_sts
& LAYER_4_CHECKSUM_OK
) {
597 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
599 (cmd_sts
& 0x0007fff8) >> 3);
601 skb
->protocol
= eth_type_trans(skb
, mp
->dev
);
602 netif_receive_skb(skb
);
605 mp
->dev
->last_rx
= jiffies
;
611 static int mv643xx_eth_poll(struct napi_struct
*napi
, int budget
)
613 struct mv643xx_eth_private
*mp
;
618 mp
= container_of(napi
, struct mv643xx_eth_private
, napi
);
620 #ifdef MV643XX_ETH_TX_FAST_REFILL
621 if (++mp
->tx_clean_threshold
> 5) {
622 mp
->tx_clean_threshold
= 0;
623 for (i
= 0; i
< mp
->txq_count
; i
++)
624 txq_reclaim(mp
->txq
+ i
, 0);
626 spin_lock_irq(&mp
->lock
);
627 __txq_maybe_wake(mp
->txq
);
628 spin_unlock_irq(&mp
->lock
);
634 for (i
= mp
->rxq_count
- 1; work_done
< budget
&& i
>= 0; i
--) {
635 struct rx_queue
*rxq
= mp
->rxq
+ i
;
637 work_done
+= rxq_process(rxq
, budget
- work_done
);
638 work_done
+= rxq_refill(rxq
, budget
- work_done
, &oom
);
641 if (work_done
< budget
) {
643 mod_timer(&mp
->rx_oom
, jiffies
+ (HZ
/ 10));
644 netif_rx_complete(mp
->dev
, napi
);
645 wrl(mp
, INT_MASK(mp
->port_num
), INT_TX_END
| INT_RX
| INT_EXT
);
651 static inline void oom_timer_wrapper(unsigned long data
)
653 struct mv643xx_eth_private
*mp
= (void *)data
;
655 napi_schedule(&mp
->napi
);
659 /* tx ***********************************************************************/
660 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
664 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
665 skb_frag_t
*fragp
= &skb_shinfo(skb
)->frags
[frag
];
666 if (fragp
->size
<= 8 && fragp
->page_offset
& 7)
673 static int txq_alloc_desc_index(struct tx_queue
*txq
)
677 BUG_ON(txq
->tx_desc_count
>= txq
->tx_ring_size
);
679 tx_desc_curr
= txq
->tx_curr_desc
++;
680 if (txq
->tx_curr_desc
== txq
->tx_ring_size
)
681 txq
->tx_curr_desc
= 0;
683 BUG_ON(txq
->tx_curr_desc
== txq
->tx_used_desc
);
688 static void txq_submit_frag_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
690 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
693 for (frag
= 0; frag
< nr_frags
; frag
++) {
694 skb_frag_t
*this_frag
;
696 struct tx_desc
*desc
;
698 this_frag
= &skb_shinfo(skb
)->frags
[frag
];
699 tx_index
= txq_alloc_desc_index(txq
);
700 desc
= &txq
->tx_desc_area
[tx_index
];
703 * The last fragment will generate an interrupt
704 * which will free the skb on TX completion.
706 if (frag
== nr_frags
- 1) {
707 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
|
708 ZERO_PADDING
| TX_LAST_DESC
|
710 txq
->tx_skb
[tx_index
] = skb
;
712 desc
->cmd_sts
= BUFFER_OWNED_BY_DMA
;
713 txq
->tx_skb
[tx_index
] = NULL
;
717 desc
->byte_cnt
= this_frag
->size
;
718 desc
->buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
719 this_frag
->page_offset
,
725 static inline __be16
sum16_as_be(__sum16 sum
)
727 return (__force __be16
)sum
;
730 static void txq_submit_skb(struct tx_queue
*txq
, struct sk_buff
*skb
)
732 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
733 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
735 struct tx_desc
*desc
;
739 cmd_sts
= TX_FIRST_DESC
| GEN_CRC
| BUFFER_OWNED_BY_DMA
;
741 tx_index
= txq_alloc_desc_index(txq
);
742 desc
= &txq
->tx_desc_area
[tx_index
];
745 txq_submit_frag_skb(txq
, skb
);
747 length
= skb_headlen(skb
);
748 txq
->tx_skb
[tx_index
] = NULL
;
750 cmd_sts
|= ZERO_PADDING
| TX_LAST_DESC
| TX_ENABLE_INTERRUPT
;
752 txq
->tx_skb
[tx_index
] = skb
;
755 desc
->byte_cnt
= length
;
756 desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
, length
, DMA_TO_DEVICE
);
758 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
761 BUG_ON(skb
->protocol
!= htons(ETH_P_IP
) &&
762 skb
->protocol
!= htons(ETH_P_8021Q
));
764 cmd_sts
|= GEN_TCP_UDP_CHECKSUM
|
766 ip_hdr(skb
)->ihl
<< TX_IHL_SHIFT
;
768 mac_hdr_len
= (void *)ip_hdr(skb
) - (void *)skb
->data
;
769 switch (mac_hdr_len
- ETH_HLEN
) {
773 cmd_sts
|= MAC_HDR_EXTRA_4_BYTES
;
776 cmd_sts
|= MAC_HDR_EXTRA_8_BYTES
;
779 cmd_sts
|= MAC_HDR_EXTRA_4_BYTES
;
780 cmd_sts
|= MAC_HDR_EXTRA_8_BYTES
;
784 dev_printk(KERN_ERR
, &txq_to_mp(txq
)->dev
->dev
,
785 "mac header length is %d?!\n", mac_hdr_len
);
789 switch (ip_hdr(skb
)->protocol
) {
791 cmd_sts
|= UDP_FRAME
;
792 desc
->l4i_chk
= ntohs(sum16_as_be(udp_hdr(skb
)->check
));
795 desc
->l4i_chk
= ntohs(sum16_as_be(tcp_hdr(skb
)->check
));
801 /* Errata BTS #50, IHL must be 5 if no HW checksum */
802 cmd_sts
|= 5 << TX_IHL_SHIFT
;
806 /* ensure all other descriptors are written before first cmd_sts */
808 desc
->cmd_sts
= cmd_sts
;
810 /* clear TX_END interrupt status */
811 wrl(mp
, INT_CAUSE(mp
->port_num
), ~(INT_TX_END_0
<< txq
->index
));
812 rdl(mp
, INT_CAUSE(mp
->port_num
));
814 /* ensure all descriptors are written before poking hardware */
818 txq
->tx_desc_count
+= nr_frags
+ 1;
821 static int mv643xx_eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
823 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
824 struct net_device_stats
*stats
= &dev
->stats
;
826 struct tx_queue
*txq
;
827 struct netdev_queue
*nq
;
831 if (has_tiny_unaligned_frags(skb
) && __skb_linearize(skb
)) {
833 dev_printk(KERN_DEBUG
, &dev
->dev
,
834 "failed to linearize skb with tiny "
835 "unaligned fragment\n");
836 return NETDEV_TX_BUSY
;
839 queue
= skb_get_queue_mapping(skb
);
840 txq
= mp
->txq
+ queue
;
841 nq
= netdev_get_tx_queue(dev
, queue
);
843 spin_lock_irqsave(&mp
->lock
, flags
);
845 if (txq
->tx_ring_size
- txq
->tx_desc_count
< MAX_SKB_FRAGS
+ 1) {
846 spin_unlock_irqrestore(&mp
->lock
, flags
);
848 dev_printk(KERN_ERR
, &dev
->dev
, "tx queue full?!\n");
853 txq_submit_skb(txq
, skb
);
854 stats
->tx_bytes
+= skb
->len
;
856 dev
->trans_start
= jiffies
;
858 entries_left
= txq
->tx_ring_size
- txq
->tx_desc_count
;
859 if (entries_left
< MAX_SKB_FRAGS
+ 1)
860 netif_tx_stop_queue(nq
);
862 spin_unlock_irqrestore(&mp
->lock
, flags
);
868 /* tx rate control **********************************************************/
870 * Set total maximum TX rate (shared by all TX queues for this port)
871 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
873 static void tx_set_rate(struct mv643xx_eth_private
*mp
, int rate
, int burst
)
879 token_rate
= ((rate
/ 1000) * 64) / (mp
->shared
->t_clk
/ 1000);
880 if (token_rate
> 1023)
883 mtu
= (mp
->dev
->mtu
+ 255) >> 8;
887 bucket_size
= (burst
+ 255) >> 8;
888 if (bucket_size
> 65535)
891 if (mp
->shared
->tx_bw_control_moved
) {
892 wrl(mp
, TX_BW_RATE_MOVED(mp
->port_num
), token_rate
);
893 wrl(mp
, TX_BW_MTU_MOVED(mp
->port_num
), mtu
);
894 wrl(mp
, TX_BW_BURST_MOVED(mp
->port_num
), bucket_size
);
896 wrl(mp
, TX_BW_RATE(mp
->port_num
), token_rate
);
897 wrl(mp
, TX_BW_MTU(mp
->port_num
), mtu
);
898 wrl(mp
, TX_BW_BURST(mp
->port_num
), bucket_size
);
902 static void txq_set_rate(struct tx_queue
*txq
, int rate
, int burst
)
904 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
908 token_rate
= ((rate
/ 1000) * 64) / (mp
->shared
->t_clk
/ 1000);
909 if (token_rate
> 1023)
912 bucket_size
= (burst
+ 255) >> 8;
913 if (bucket_size
> 65535)
916 wrl(mp
, TXQ_BW_TOKENS(mp
->port_num
, txq
->index
), token_rate
<< 14);
917 wrl(mp
, TXQ_BW_CONF(mp
->port_num
, txq
->index
),
918 (bucket_size
<< 10) | token_rate
);
921 static void txq_set_fixed_prio_mode(struct tx_queue
*txq
)
923 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
928 * Turn on fixed priority mode.
930 if (mp
->shared
->tx_bw_control_moved
)
931 off
= TXQ_FIX_PRIO_CONF_MOVED(mp
->port_num
);
933 off
= TXQ_FIX_PRIO_CONF(mp
->port_num
);
936 val
|= 1 << txq
->index
;
940 static void txq_set_wrr(struct tx_queue
*txq
, int weight
)
942 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
947 * Turn off fixed priority mode.
949 if (mp
->shared
->tx_bw_control_moved
)
950 off
= TXQ_FIX_PRIO_CONF_MOVED(mp
->port_num
);
952 off
= TXQ_FIX_PRIO_CONF(mp
->port_num
);
955 val
&= ~(1 << txq
->index
);
959 * Configure WRR weight for this queue.
961 off
= TXQ_BW_WRR_CONF(mp
->port_num
, txq
->index
);
964 val
= (val
& ~0xff) | (weight
& 0xff);
969 /* mii management interface *************************************************/
970 static irqreturn_t
mv643xx_eth_err_irq(int irq
, void *dev_id
)
972 struct mv643xx_eth_shared_private
*msp
= dev_id
;
974 if (readl(msp
->base
+ ERR_INT_CAUSE
) & ERR_INT_SMI_DONE
) {
975 writel(~ERR_INT_SMI_DONE
, msp
->base
+ ERR_INT_CAUSE
);
976 wake_up(&msp
->smi_busy_wait
);
983 static int smi_is_done(struct mv643xx_eth_shared_private
*msp
)
985 return !(readl(msp
->base
+ SMI_REG
) & SMI_BUSY
);
988 static int smi_wait_ready(struct mv643xx_eth_shared_private
*msp
)
990 if (msp
->err_interrupt
== NO_IRQ
) {
993 for (i
= 0; !smi_is_done(msp
); i
++) {
1002 if (!wait_event_timeout(msp
->smi_busy_wait
, smi_is_done(msp
),
1003 msecs_to_jiffies(100)))
1009 static int smi_reg_read(struct mv643xx_eth_private
*mp
,
1010 unsigned int addr
, unsigned int reg
)
1012 struct mv643xx_eth_shared_private
*msp
= mp
->shared
->smi
;
1013 void __iomem
*smi_reg
= msp
->base
+ SMI_REG
;
1016 mutex_lock(&msp
->phy_lock
);
1018 if (smi_wait_ready(msp
)) {
1019 printk("%s: SMI bus busy timeout\n", mp
->dev
->name
);
1024 writel(SMI_OPCODE_READ
| (reg
<< 21) | (addr
<< 16), smi_reg
);
1026 if (smi_wait_ready(msp
)) {
1027 printk("%s: SMI bus busy timeout\n", mp
->dev
->name
);
1032 ret
= readl(smi_reg
);
1033 if (!(ret
& SMI_READ_VALID
)) {
1034 printk("%s: SMI bus read not valid\n", mp
->dev
->name
);
1042 mutex_unlock(&msp
->phy_lock
);
1047 static int smi_reg_write(struct mv643xx_eth_private
*mp
, unsigned int addr
,
1048 unsigned int reg
, unsigned int value
)
1050 struct mv643xx_eth_shared_private
*msp
= mp
->shared
->smi
;
1051 void __iomem
*smi_reg
= msp
->base
+ SMI_REG
;
1053 mutex_lock(&msp
->phy_lock
);
1055 if (smi_wait_ready(msp
)) {
1056 printk("%s: SMI bus busy timeout\n", mp
->dev
->name
);
1057 mutex_unlock(&msp
->phy_lock
);
1061 writel(SMI_OPCODE_WRITE
| (reg
<< 21) |
1062 (addr
<< 16) | (value
& 0xffff), smi_reg
);
1064 mutex_unlock(&msp
->phy_lock
);
1070 /* mib counters *************************************************************/
1071 static inline u32
mib_read(struct mv643xx_eth_private
*mp
, int offset
)
1073 return rdl(mp
, MIB_COUNTERS(mp
->port_num
) + offset
);
1076 static void mib_counters_clear(struct mv643xx_eth_private
*mp
)
1080 for (i
= 0; i
< 0x80; i
+= 4)
1084 static void mib_counters_update(struct mv643xx_eth_private
*mp
)
1086 struct mib_counters
*p
= &mp
->mib_counters
;
1088 p
->good_octets_received
+= mib_read(mp
, 0x00);
1089 p
->good_octets_received
+= (u64
)mib_read(mp
, 0x04) << 32;
1090 p
->bad_octets_received
+= mib_read(mp
, 0x08);
1091 p
->internal_mac_transmit_err
+= mib_read(mp
, 0x0c);
1092 p
->good_frames_received
+= mib_read(mp
, 0x10);
1093 p
->bad_frames_received
+= mib_read(mp
, 0x14);
1094 p
->broadcast_frames_received
+= mib_read(mp
, 0x18);
1095 p
->multicast_frames_received
+= mib_read(mp
, 0x1c);
1096 p
->frames_64_octets
+= mib_read(mp
, 0x20);
1097 p
->frames_65_to_127_octets
+= mib_read(mp
, 0x24);
1098 p
->frames_128_to_255_octets
+= mib_read(mp
, 0x28);
1099 p
->frames_256_to_511_octets
+= mib_read(mp
, 0x2c);
1100 p
->frames_512_to_1023_octets
+= mib_read(mp
, 0x30);
1101 p
->frames_1024_to_max_octets
+= mib_read(mp
, 0x34);
1102 p
->good_octets_sent
+= mib_read(mp
, 0x38);
1103 p
->good_octets_sent
+= (u64
)mib_read(mp
, 0x3c) << 32;
1104 p
->good_frames_sent
+= mib_read(mp
, 0x40);
1105 p
->excessive_collision
+= mib_read(mp
, 0x44);
1106 p
->multicast_frames_sent
+= mib_read(mp
, 0x48);
1107 p
->broadcast_frames_sent
+= mib_read(mp
, 0x4c);
1108 p
->unrec_mac_control_received
+= mib_read(mp
, 0x50);
1109 p
->fc_sent
+= mib_read(mp
, 0x54);
1110 p
->good_fc_received
+= mib_read(mp
, 0x58);
1111 p
->bad_fc_received
+= mib_read(mp
, 0x5c);
1112 p
->undersize_received
+= mib_read(mp
, 0x60);
1113 p
->fragments_received
+= mib_read(mp
, 0x64);
1114 p
->oversize_received
+= mib_read(mp
, 0x68);
1115 p
->jabber_received
+= mib_read(mp
, 0x6c);
1116 p
->mac_receive_error
+= mib_read(mp
, 0x70);
1117 p
->bad_crc_event
+= mib_read(mp
, 0x74);
1118 p
->collision
+= mib_read(mp
, 0x78);
1119 p
->late_collision
+= mib_read(mp
, 0x7c);
1123 /* ethtool ******************************************************************/
1124 struct mv643xx_eth_stats
{
1125 char stat_string
[ETH_GSTRING_LEN
];
1132 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1133 offsetof(struct net_device, stats.m), -1 }
1135 #define MIBSTAT(m) \
1136 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1137 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1139 static const struct mv643xx_eth_stats mv643xx_eth_stats
[] = {
1148 MIBSTAT(good_octets_received
),
1149 MIBSTAT(bad_octets_received
),
1150 MIBSTAT(internal_mac_transmit_err
),
1151 MIBSTAT(good_frames_received
),
1152 MIBSTAT(bad_frames_received
),
1153 MIBSTAT(broadcast_frames_received
),
1154 MIBSTAT(multicast_frames_received
),
1155 MIBSTAT(frames_64_octets
),
1156 MIBSTAT(frames_65_to_127_octets
),
1157 MIBSTAT(frames_128_to_255_octets
),
1158 MIBSTAT(frames_256_to_511_octets
),
1159 MIBSTAT(frames_512_to_1023_octets
),
1160 MIBSTAT(frames_1024_to_max_octets
),
1161 MIBSTAT(good_octets_sent
),
1162 MIBSTAT(good_frames_sent
),
1163 MIBSTAT(excessive_collision
),
1164 MIBSTAT(multicast_frames_sent
),
1165 MIBSTAT(broadcast_frames_sent
),
1166 MIBSTAT(unrec_mac_control_received
),
1168 MIBSTAT(good_fc_received
),
1169 MIBSTAT(bad_fc_received
),
1170 MIBSTAT(undersize_received
),
1171 MIBSTAT(fragments_received
),
1172 MIBSTAT(oversize_received
),
1173 MIBSTAT(jabber_received
),
1174 MIBSTAT(mac_receive_error
),
1175 MIBSTAT(bad_crc_event
),
1177 MIBSTAT(late_collision
),
1180 static int mv643xx_eth_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1182 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1185 err
= mii_ethtool_gset(&mp
->mii
, cmd
);
1188 * The MAC does not support 1000baseT_Half.
1190 cmd
->supported
&= ~SUPPORTED_1000baseT_Half
;
1191 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1196 static int mv643xx_eth_get_settings_phyless(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1198 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1201 port_status
= rdl(mp
, PORT_STATUS(mp
->port_num
));
1203 cmd
->supported
= SUPPORTED_MII
;
1204 cmd
->advertising
= ADVERTISED_MII
;
1205 switch (port_status
& PORT_SPEED_MASK
) {
1207 cmd
->speed
= SPEED_10
;
1209 case PORT_SPEED_100
:
1210 cmd
->speed
= SPEED_100
;
1212 case PORT_SPEED_1000
:
1213 cmd
->speed
= SPEED_1000
;
1219 cmd
->duplex
= (port_status
& FULL_DUPLEX
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1220 cmd
->port
= PORT_MII
;
1221 cmd
->phy_address
= 0;
1222 cmd
->transceiver
= XCVR_INTERNAL
;
1223 cmd
->autoneg
= AUTONEG_DISABLE
;
1230 static int mv643xx_eth_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1232 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1235 * The MAC does not support 1000baseT_Half.
1237 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1239 return mii_ethtool_sset(&mp
->mii
, cmd
);
1242 static int mv643xx_eth_set_settings_phyless(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1247 static void mv643xx_eth_get_drvinfo(struct net_device
*dev
,
1248 struct ethtool_drvinfo
*drvinfo
)
1250 strncpy(drvinfo
->driver
, mv643xx_eth_driver_name
, 32);
1251 strncpy(drvinfo
->version
, mv643xx_eth_driver_version
, 32);
1252 strncpy(drvinfo
->fw_version
, "N/A", 32);
1253 strncpy(drvinfo
->bus_info
, "platform", 32);
1254 drvinfo
->n_stats
= ARRAY_SIZE(mv643xx_eth_stats
);
1257 static int mv643xx_eth_nway_reset(struct net_device
*dev
)
1259 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1261 return mii_nway_restart(&mp
->mii
);
1264 static int mv643xx_eth_nway_reset_phyless(struct net_device
*dev
)
1269 static u32
mv643xx_eth_get_link(struct net_device
*dev
)
1271 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1273 return mii_link_ok(&mp
->mii
);
1276 static u32
mv643xx_eth_get_link_phyless(struct net_device
*dev
)
1281 static void mv643xx_eth_get_strings(struct net_device
*dev
,
1282 uint32_t stringset
, uint8_t *data
)
1286 if (stringset
== ETH_SS_STATS
) {
1287 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1288 memcpy(data
+ i
* ETH_GSTRING_LEN
,
1289 mv643xx_eth_stats
[i
].stat_string
,
1295 static void mv643xx_eth_get_ethtool_stats(struct net_device
*dev
,
1296 struct ethtool_stats
*stats
,
1299 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1302 mib_counters_update(mp
);
1304 for (i
= 0; i
< ARRAY_SIZE(mv643xx_eth_stats
); i
++) {
1305 const struct mv643xx_eth_stats
*stat
;
1308 stat
= mv643xx_eth_stats
+ i
;
1310 if (stat
->netdev_off
>= 0)
1311 p
= ((void *)mp
->dev
) + stat
->netdev_off
;
1313 p
= ((void *)mp
) + stat
->mp_off
;
1315 data
[i
] = (stat
->sizeof_stat
== 8) ?
1316 *(uint64_t *)p
: *(uint32_t *)p
;
1320 static int mv643xx_eth_get_sset_count(struct net_device
*dev
, int sset
)
1322 if (sset
== ETH_SS_STATS
)
1323 return ARRAY_SIZE(mv643xx_eth_stats
);
1328 static const struct ethtool_ops mv643xx_eth_ethtool_ops
= {
1329 .get_settings
= mv643xx_eth_get_settings
,
1330 .set_settings
= mv643xx_eth_set_settings
,
1331 .get_drvinfo
= mv643xx_eth_get_drvinfo
,
1332 .nway_reset
= mv643xx_eth_nway_reset
,
1333 .get_link
= mv643xx_eth_get_link
,
1334 .set_sg
= ethtool_op_set_sg
,
1335 .get_strings
= mv643xx_eth_get_strings
,
1336 .get_ethtool_stats
= mv643xx_eth_get_ethtool_stats
,
1337 .get_sset_count
= mv643xx_eth_get_sset_count
,
1340 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless
= {
1341 .get_settings
= mv643xx_eth_get_settings_phyless
,
1342 .set_settings
= mv643xx_eth_set_settings_phyless
,
1343 .get_drvinfo
= mv643xx_eth_get_drvinfo
,
1344 .nway_reset
= mv643xx_eth_nway_reset_phyless
,
1345 .get_link
= mv643xx_eth_get_link_phyless
,
1346 .set_sg
= ethtool_op_set_sg
,
1347 .get_strings
= mv643xx_eth_get_strings
,
1348 .get_ethtool_stats
= mv643xx_eth_get_ethtool_stats
,
1349 .get_sset_count
= mv643xx_eth_get_sset_count
,
1353 /* address handling *********************************************************/
1354 static void uc_addr_get(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1359 mac_h
= rdl(mp
, MAC_ADDR_HIGH(mp
->port_num
));
1360 mac_l
= rdl(mp
, MAC_ADDR_LOW(mp
->port_num
));
1362 addr
[0] = (mac_h
>> 24) & 0xff;
1363 addr
[1] = (mac_h
>> 16) & 0xff;
1364 addr
[2] = (mac_h
>> 8) & 0xff;
1365 addr
[3] = mac_h
& 0xff;
1366 addr
[4] = (mac_l
>> 8) & 0xff;
1367 addr
[5] = mac_l
& 0xff;
1370 static void init_mac_tables(struct mv643xx_eth_private
*mp
)
1374 for (i
= 0; i
< 0x100; i
+= 4) {
1375 wrl(mp
, SPECIAL_MCAST_TABLE(mp
->port_num
) + i
, 0);
1376 wrl(mp
, OTHER_MCAST_TABLE(mp
->port_num
) + i
, 0);
1379 for (i
= 0; i
< 0x10; i
+= 4)
1380 wrl(mp
, UNICAST_TABLE(mp
->port_num
) + i
, 0);
1383 static void set_filter_table_entry(struct mv643xx_eth_private
*mp
,
1384 int table
, unsigned char entry
)
1386 unsigned int table_reg
;
1388 /* Set "accepts frame bit" at specified table entry */
1389 table_reg
= rdl(mp
, table
+ (entry
& 0xfc));
1390 table_reg
|= 0x01 << (8 * (entry
& 3));
1391 wrl(mp
, table
+ (entry
& 0xfc), table_reg
);
1394 static void uc_addr_set(struct mv643xx_eth_private
*mp
, unsigned char *addr
)
1400 mac_l
= (addr
[4] << 8) | addr
[5];
1401 mac_h
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
1403 wrl(mp
, MAC_ADDR_LOW(mp
->port_num
), mac_l
);
1404 wrl(mp
, MAC_ADDR_HIGH(mp
->port_num
), mac_h
);
1406 table
= UNICAST_TABLE(mp
->port_num
);
1407 set_filter_table_entry(mp
, table
, addr
[5] & 0x0f);
1410 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
1412 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1414 /* +2 is for the offset of the HW addr type */
1415 memcpy(dev
->dev_addr
, addr
+ 2, 6);
1417 init_mac_tables(mp
);
1418 uc_addr_set(mp
, dev
->dev_addr
);
1423 static int addr_crc(unsigned char *addr
)
1428 for (i
= 0; i
< 6; i
++) {
1431 crc
= (crc
^ addr
[i
]) << 8;
1432 for (j
= 7; j
>= 0; j
--) {
1433 if (crc
& (0x100 << j
))
1441 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
1443 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1445 struct dev_addr_list
*addr
;
1448 port_config
= rdl(mp
, PORT_CONFIG(mp
->port_num
));
1449 if (dev
->flags
& IFF_PROMISC
)
1450 port_config
|= UNICAST_PROMISCUOUS_MODE
;
1452 port_config
&= ~UNICAST_PROMISCUOUS_MODE
;
1453 wrl(mp
, PORT_CONFIG(mp
->port_num
), port_config
);
1455 if (dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
)) {
1456 int port_num
= mp
->port_num
;
1457 u32 accept
= 0x01010101;
1459 for (i
= 0; i
< 0x100; i
+= 4) {
1460 wrl(mp
, SPECIAL_MCAST_TABLE(port_num
) + i
, accept
);
1461 wrl(mp
, OTHER_MCAST_TABLE(port_num
) + i
, accept
);
1466 for (i
= 0; i
< 0x100; i
+= 4) {
1467 wrl(mp
, SPECIAL_MCAST_TABLE(mp
->port_num
) + i
, 0);
1468 wrl(mp
, OTHER_MCAST_TABLE(mp
->port_num
) + i
, 0);
1471 for (addr
= dev
->mc_list
; addr
!= NULL
; addr
= addr
->next
) {
1472 u8
*a
= addr
->da_addr
;
1475 if (addr
->da_addrlen
!= 6)
1478 if (memcmp(a
, "\x01\x00\x5e\x00\x00", 5) == 0) {
1479 table
= SPECIAL_MCAST_TABLE(mp
->port_num
);
1480 set_filter_table_entry(mp
, table
, a
[5]);
1482 int crc
= addr_crc(a
);
1484 table
= OTHER_MCAST_TABLE(mp
->port_num
);
1485 set_filter_table_entry(mp
, table
, crc
);
1491 /* rx/tx queue initialisation ***********************************************/
1492 static int rxq_init(struct mv643xx_eth_private
*mp
, int index
)
1494 struct rx_queue
*rxq
= mp
->rxq
+ index
;
1495 struct rx_desc
*rx_desc
;
1501 rxq
->rx_ring_size
= mp
->default_rx_ring_size
;
1503 rxq
->rx_desc_count
= 0;
1504 rxq
->rx_curr_desc
= 0;
1505 rxq
->rx_used_desc
= 0;
1507 size
= rxq
->rx_ring_size
* sizeof(struct rx_desc
);
1509 if (index
== 0 && size
<= mp
->rx_desc_sram_size
) {
1510 rxq
->rx_desc_area
= ioremap(mp
->rx_desc_sram_addr
,
1511 mp
->rx_desc_sram_size
);
1512 rxq
->rx_desc_dma
= mp
->rx_desc_sram_addr
;
1514 rxq
->rx_desc_area
= dma_alloc_coherent(NULL
, size
,
1519 if (rxq
->rx_desc_area
== NULL
) {
1520 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1521 "can't allocate rx ring (%d bytes)\n", size
);
1524 memset(rxq
->rx_desc_area
, 0, size
);
1526 rxq
->rx_desc_area_size
= size
;
1527 rxq
->rx_skb
= kmalloc(rxq
->rx_ring_size
* sizeof(*rxq
->rx_skb
),
1529 if (rxq
->rx_skb
== NULL
) {
1530 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1531 "can't allocate rx skb ring\n");
1535 rx_desc
= (struct rx_desc
*)rxq
->rx_desc_area
;
1536 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1540 if (nexti
== rxq
->rx_ring_size
)
1543 rx_desc
[i
].next_desc_ptr
= rxq
->rx_desc_dma
+
1544 nexti
* sizeof(struct rx_desc
);
1551 if (index
== 0 && size
<= mp
->rx_desc_sram_size
)
1552 iounmap(rxq
->rx_desc_area
);
1554 dma_free_coherent(NULL
, size
,
1562 static void rxq_deinit(struct rx_queue
*rxq
)
1564 struct mv643xx_eth_private
*mp
= rxq_to_mp(rxq
);
1569 for (i
= 0; i
< rxq
->rx_ring_size
; i
++) {
1570 if (rxq
->rx_skb
[i
]) {
1571 dev_kfree_skb(rxq
->rx_skb
[i
]);
1572 rxq
->rx_desc_count
--;
1576 if (rxq
->rx_desc_count
) {
1577 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1578 "error freeing rx ring -- %d skbs stuck\n",
1579 rxq
->rx_desc_count
);
1582 if (rxq
->index
== 0 &&
1583 rxq
->rx_desc_area_size
<= mp
->rx_desc_sram_size
)
1584 iounmap(rxq
->rx_desc_area
);
1586 dma_free_coherent(NULL
, rxq
->rx_desc_area_size
,
1587 rxq
->rx_desc_area
, rxq
->rx_desc_dma
);
1592 static int txq_init(struct mv643xx_eth_private
*mp
, int index
)
1594 struct tx_queue
*txq
= mp
->txq
+ index
;
1595 struct tx_desc
*tx_desc
;
1601 txq
->tx_ring_size
= mp
->default_tx_ring_size
;
1603 txq
->tx_desc_count
= 0;
1604 txq
->tx_curr_desc
= 0;
1605 txq
->tx_used_desc
= 0;
1607 size
= txq
->tx_ring_size
* sizeof(struct tx_desc
);
1609 if (index
== 0 && size
<= mp
->tx_desc_sram_size
) {
1610 txq
->tx_desc_area
= ioremap(mp
->tx_desc_sram_addr
,
1611 mp
->tx_desc_sram_size
);
1612 txq
->tx_desc_dma
= mp
->tx_desc_sram_addr
;
1614 txq
->tx_desc_area
= dma_alloc_coherent(NULL
, size
,
1619 if (txq
->tx_desc_area
== NULL
) {
1620 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1621 "can't allocate tx ring (%d bytes)\n", size
);
1624 memset(txq
->tx_desc_area
, 0, size
);
1626 txq
->tx_desc_area_size
= size
;
1627 txq
->tx_skb
= kmalloc(txq
->tx_ring_size
* sizeof(*txq
->tx_skb
),
1629 if (txq
->tx_skb
== NULL
) {
1630 dev_printk(KERN_ERR
, &mp
->dev
->dev
,
1631 "can't allocate tx skb ring\n");
1635 tx_desc
= (struct tx_desc
*)txq
->tx_desc_area
;
1636 for (i
= 0; i
< txq
->tx_ring_size
; i
++) {
1637 struct tx_desc
*txd
= tx_desc
+ i
;
1641 if (nexti
== txq
->tx_ring_size
)
1645 txd
->next_desc_ptr
= txq
->tx_desc_dma
+
1646 nexti
* sizeof(struct tx_desc
);
1653 if (index
== 0 && size
<= mp
->tx_desc_sram_size
)
1654 iounmap(txq
->tx_desc_area
);
1656 dma_free_coherent(NULL
, size
,
1664 static void txq_reclaim(struct tx_queue
*txq
, int force
)
1666 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1667 unsigned long flags
;
1669 spin_lock_irqsave(&mp
->lock
, flags
);
1670 while (txq
->tx_desc_count
> 0) {
1672 struct tx_desc
*desc
;
1674 struct sk_buff
*skb
;
1678 tx_index
= txq
->tx_used_desc
;
1679 desc
= &txq
->tx_desc_area
[tx_index
];
1680 cmd_sts
= desc
->cmd_sts
;
1682 if (cmd_sts
& BUFFER_OWNED_BY_DMA
) {
1685 desc
->cmd_sts
= cmd_sts
& ~BUFFER_OWNED_BY_DMA
;
1688 txq
->tx_used_desc
= tx_index
+ 1;
1689 if (txq
->tx_used_desc
== txq
->tx_ring_size
)
1690 txq
->tx_used_desc
= 0;
1691 txq
->tx_desc_count
--;
1693 addr
= desc
->buf_ptr
;
1694 count
= desc
->byte_cnt
;
1695 skb
= txq
->tx_skb
[tx_index
];
1696 txq
->tx_skb
[tx_index
] = NULL
;
1698 if (cmd_sts
& ERROR_SUMMARY
) {
1699 dev_printk(KERN_INFO
, &mp
->dev
->dev
, "tx error\n");
1700 mp
->dev
->stats
.tx_errors
++;
1704 * Drop mp->lock while we free the skb.
1706 spin_unlock_irqrestore(&mp
->lock
, flags
);
1708 if (cmd_sts
& TX_FIRST_DESC
)
1709 dma_unmap_single(NULL
, addr
, count
, DMA_TO_DEVICE
);
1711 dma_unmap_page(NULL
, addr
, count
, DMA_TO_DEVICE
);
1714 dev_kfree_skb_irq(skb
);
1716 spin_lock_irqsave(&mp
->lock
, flags
);
1718 spin_unlock_irqrestore(&mp
->lock
, flags
);
1721 static void txq_deinit(struct tx_queue
*txq
)
1723 struct mv643xx_eth_private
*mp
= txq_to_mp(txq
);
1726 txq_reclaim(txq
, 1);
1728 BUG_ON(txq
->tx_used_desc
!= txq
->tx_curr_desc
);
1730 if (txq
->index
== 0 &&
1731 txq
->tx_desc_area_size
<= mp
->tx_desc_sram_size
)
1732 iounmap(txq
->tx_desc_area
);
1734 dma_free_coherent(NULL
, txq
->tx_desc_area_size
,
1735 txq
->tx_desc_area
, txq
->tx_desc_dma
);
1741 /* netdev ops and related ***************************************************/
1742 static void handle_link_event(struct mv643xx_eth_private
*mp
)
1744 struct net_device
*dev
= mp
->dev
;
1750 port_status
= rdl(mp
, PORT_STATUS(mp
->port_num
));
1751 if (!(port_status
& LINK_UP
)) {
1752 if (netif_carrier_ok(dev
)) {
1755 printk(KERN_INFO
"%s: link down\n", dev
->name
);
1757 netif_carrier_off(dev
);
1759 for (i
= 0; i
< mp
->txq_count
; i
++) {
1760 struct tx_queue
*txq
= mp
->txq
+ i
;
1762 txq_reclaim(txq
, 1);
1763 txq_reset_hw_ptr(txq
);
1769 switch (port_status
& PORT_SPEED_MASK
) {
1773 case PORT_SPEED_100
:
1776 case PORT_SPEED_1000
:
1783 duplex
= (port_status
& FULL_DUPLEX
) ? 1 : 0;
1784 fc
= (port_status
& FLOW_CONTROL_ENABLED
) ? 1 : 0;
1786 printk(KERN_INFO
"%s: link up, %d Mb/s, %s duplex, "
1787 "flow control %sabled\n", dev
->name
,
1788 speed
, duplex
? "full" : "half",
1791 if (!netif_carrier_ok(dev
))
1792 netif_carrier_on(dev
);
1795 static irqreturn_t
mv643xx_eth_irq(int irq
, void *dev_id
)
1797 struct net_device
*dev
= (struct net_device
*)dev_id
;
1798 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
1802 int_cause
= rdl(mp
, INT_CAUSE(mp
->port_num
)) &
1803 (INT_TX_END
| INT_RX
| INT_EXT
);
1808 if (int_cause
& INT_EXT
) {
1809 int_cause_ext
= rdl(mp
, INT_CAUSE_EXT(mp
->port_num
))
1810 & (INT_EXT_LINK_PHY
| INT_EXT_TX
);
1811 wrl(mp
, INT_CAUSE_EXT(mp
->port_num
), ~int_cause_ext
);
1814 if (int_cause_ext
& INT_EXT_LINK_PHY
)
1815 handle_link_event(mp
);
1818 * RxBuffer or RxError set for any of the 8 queues?
1820 if (int_cause
& INT_RX
) {
1821 wrl(mp
, INT_CAUSE(mp
->port_num
), ~(int_cause
& INT_RX
));
1822 wrl(mp
, INT_MASK(mp
->port_num
), 0x00000000);
1823 rdl(mp
, INT_MASK(mp
->port_num
));
1825 napi_schedule(&mp
->napi
);
1829 * TxBuffer or TxError set for any of the 8 queues?
1831 if (int_cause_ext
& INT_EXT_TX
) {
1834 for (i
= 0; i
< mp
->txq_count
; i
++)
1835 txq_reclaim(mp
->txq
+ i
, 0);
1838 * Enough space again in the primary TX queue for a
1841 spin_lock(&mp
->lock
);
1842 __txq_maybe_wake(mp
->txq
);
1843 spin_unlock(&mp
->lock
);
1847 * Any TxEnd interrupts?
1849 if (int_cause
& INT_TX_END
) {
1852 wrl(mp
, INT_CAUSE(mp
->port_num
), ~(int_cause
& INT_TX_END
));
1854 spin_lock(&mp
->lock
);
1855 for (i
= 0; i
< 8; i
++) {
1856 struct tx_queue
*txq
= mp
->txq
+ i
;
1860 if ((int_cause
& (INT_TX_END_0
<< i
)) == 0)
1864 rdl(mp
, TXQ_CURRENT_DESC_PTR(mp
->port_num
, i
));
1865 expected_ptr
= (u32
)txq
->tx_desc_dma
+
1866 txq
->tx_curr_desc
* sizeof(struct tx_desc
);
1868 if (hw_desc_ptr
!= expected_ptr
)
1871 spin_unlock(&mp
->lock
);
1877 static void phy_reset(struct mv643xx_eth_private
*mp
)
1881 data
= smi_reg_read(mp
, mp
->phy_addr
, MII_BMCR
);
1886 if (smi_reg_write(mp
, mp
->phy_addr
, MII_BMCR
, data
) < 0)
1890 data
= smi_reg_read(mp
, mp
->phy_addr
, MII_BMCR
);
1891 } while (data
>= 0 && data
& BMCR_RESET
);
1894 static void port_start(struct mv643xx_eth_private
*mp
)
1900 * Perform PHY reset, if there is a PHY.
1902 if (mp
->phy_addr
!= -1) {
1903 struct ethtool_cmd cmd
;
1905 mv643xx_eth_get_settings(mp
->dev
, &cmd
);
1907 mv643xx_eth_set_settings(mp
->dev
, &cmd
);
1911 * Configure basic link parameters.
1913 pscr
= rdl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
));
1915 pscr
|= SERIAL_PORT_ENABLE
;
1916 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), pscr
);
1918 pscr
|= DO_NOT_FORCE_LINK_FAIL
;
1919 if (mp
->phy_addr
== -1)
1920 pscr
|= FORCE_LINK_PASS
;
1921 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), pscr
);
1923 wrl(mp
, SDMA_CONFIG(mp
->port_num
), PORT_SDMA_CONFIG_DEFAULT_VALUE
);
1926 * Configure TX path and queues.
1928 tx_set_rate(mp
, 1000000000, 16777216);
1929 for (i
= 0; i
< mp
->txq_count
; i
++) {
1930 struct tx_queue
*txq
= mp
->txq
+ i
;
1932 txq_reset_hw_ptr(txq
);
1933 txq_set_rate(txq
, 1000000000, 16777216);
1934 txq_set_fixed_prio_mode(txq
);
1938 * Add configured unicast address to address filter table.
1940 uc_addr_set(mp
, mp
->dev
->dev_addr
);
1943 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1944 * frames to RX queue #0.
1946 wrl(mp
, PORT_CONFIG(mp
->port_num
), 0x00000000);
1949 * Treat BPDUs as normal multicasts, and disable partition mode.
1951 wrl(mp
, PORT_CONFIG_EXT(mp
->port_num
), 0x00000000);
1954 * Enable the receive queues.
1956 for (i
= 0; i
< mp
->rxq_count
; i
++) {
1957 struct rx_queue
*rxq
= mp
->rxq
+ i
;
1958 int off
= RXQ_CURRENT_DESC_PTR(mp
->port_num
, i
);
1961 addr
= (u32
)rxq
->rx_desc_dma
;
1962 addr
+= rxq
->rx_curr_desc
* sizeof(struct rx_desc
);
1969 static void set_rx_coal(struct mv643xx_eth_private
*mp
, unsigned int delay
)
1971 unsigned int coal
= ((mp
->shared
->t_clk
/ 1000000) * delay
) / 64;
1974 val
= rdl(mp
, SDMA_CONFIG(mp
->port_num
));
1975 if (mp
->shared
->extended_rx_coal_limit
) {
1979 val
|= (coal
& 0x8000) << 10;
1980 val
|= (coal
& 0x7fff) << 7;
1985 val
|= (coal
& 0x3fff) << 8;
1987 wrl(mp
, SDMA_CONFIG(mp
->port_num
), val
);
1990 static void set_tx_coal(struct mv643xx_eth_private
*mp
, unsigned int delay
)
1992 unsigned int coal
= ((mp
->shared
->t_clk
/ 1000000) * delay
) / 64;
1996 wrl(mp
, TX_FIFO_URGENT_THRESHOLD(mp
->port_num
), (coal
& 0x3fff) << 4);
1999 static int mv643xx_eth_open(struct net_device
*dev
)
2001 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2006 wrl(mp
, INT_CAUSE(mp
->port_num
), 0);
2007 wrl(mp
, INT_CAUSE_EXT(mp
->port_num
), 0);
2008 rdl(mp
, INT_CAUSE_EXT(mp
->port_num
));
2010 err
= request_irq(dev
->irq
, mv643xx_eth_irq
,
2011 IRQF_SHARED
, dev
->name
, dev
);
2013 dev_printk(KERN_ERR
, &dev
->dev
, "can't assign irq\n");
2017 init_mac_tables(mp
);
2019 napi_enable(&mp
->napi
);
2022 for (i
= 0; i
< mp
->rxq_count
; i
++) {
2023 err
= rxq_init(mp
, i
);
2026 rxq_deinit(mp
->rxq
+ i
);
2030 rxq_refill(mp
->rxq
+ i
, INT_MAX
, &oom
);
2034 mp
->rx_oom
.expires
= jiffies
+ (HZ
/ 10);
2035 add_timer(&mp
->rx_oom
);
2038 for (i
= 0; i
< mp
->txq_count
; i
++) {
2039 err
= txq_init(mp
, i
);
2042 txq_deinit(mp
->txq
+ i
);
2047 netif_carrier_off(dev
);
2054 wrl(mp
, INT_MASK_EXT(mp
->port_num
), INT_EXT_LINK_PHY
| INT_EXT_TX
);
2055 wrl(mp
, INT_MASK(mp
->port_num
), INT_TX_END
| INT_RX
| INT_EXT
);
2061 for (i
= 0; i
< mp
->rxq_count
; i
++)
2062 rxq_deinit(mp
->rxq
+ i
);
2064 free_irq(dev
->irq
, dev
);
2069 static void port_reset(struct mv643xx_eth_private
*mp
)
2074 for (i
= 0; i
< mp
->rxq_count
; i
++)
2075 rxq_disable(mp
->rxq
+ i
);
2076 for (i
= 0; i
< mp
->txq_count
; i
++)
2077 txq_disable(mp
->txq
+ i
);
2080 u32 ps
= rdl(mp
, PORT_STATUS(mp
->port_num
));
2082 if ((ps
& (TX_IN_PROGRESS
| TX_FIFO_EMPTY
)) == TX_FIFO_EMPTY
)
2087 /* Reset the Enable bit in the Configuration Register */
2088 data
= rdl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
));
2089 data
&= ~(SERIAL_PORT_ENABLE
|
2090 DO_NOT_FORCE_LINK_FAIL
|
2092 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), data
);
2095 static int mv643xx_eth_stop(struct net_device
*dev
)
2097 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2100 wrl(mp
, INT_MASK(mp
->port_num
), 0x00000000);
2101 rdl(mp
, INT_MASK(mp
->port_num
));
2103 napi_disable(&mp
->napi
);
2105 del_timer_sync(&mp
->rx_oom
);
2107 netif_carrier_off(dev
);
2109 free_irq(dev
->irq
, dev
);
2112 mib_counters_update(mp
);
2114 for (i
= 0; i
< mp
->rxq_count
; i
++)
2115 rxq_deinit(mp
->rxq
+ i
);
2116 for (i
= 0; i
< mp
->txq_count
; i
++)
2117 txq_deinit(mp
->txq
+ i
);
2122 static int mv643xx_eth_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2124 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2126 if (mp
->phy_addr
!= -1)
2127 return generic_mii_ioctl(&mp
->mii
, if_mii(ifr
), cmd
, NULL
);
2132 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
2134 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2136 if (new_mtu
< 64 || new_mtu
> 9500)
2140 tx_set_rate(mp
, 1000000000, 16777216);
2142 if (!netif_running(dev
))
2146 * Stop and then re-open the interface. This will allocate RX
2147 * skbs of the new MTU.
2148 * There is a possible danger that the open will not succeed,
2149 * due to memory being full.
2151 mv643xx_eth_stop(dev
);
2152 if (mv643xx_eth_open(dev
)) {
2153 dev_printk(KERN_ERR
, &dev
->dev
,
2154 "fatal error on re-opening device after "
2161 static void tx_timeout_task(struct work_struct
*ugly
)
2163 struct mv643xx_eth_private
*mp
;
2165 mp
= container_of(ugly
, struct mv643xx_eth_private
, tx_timeout_task
);
2166 if (netif_running(mp
->dev
)) {
2167 netif_tx_stop_all_queues(mp
->dev
);
2170 netif_tx_wake_all_queues(mp
->dev
);
2174 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
2176 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2178 dev_printk(KERN_INFO
, &dev
->dev
, "tx timeout\n");
2180 schedule_work(&mp
->tx_timeout_task
);
2183 #ifdef CONFIG_NET_POLL_CONTROLLER
2184 static void mv643xx_eth_netpoll(struct net_device
*dev
)
2186 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2188 wrl(mp
, INT_MASK(mp
->port_num
), 0x00000000);
2189 rdl(mp
, INT_MASK(mp
->port_num
));
2191 mv643xx_eth_irq(dev
->irq
, dev
);
2193 wrl(mp
, INT_MASK(mp
->port_num
), INT_TX_END
| INT_RX
| INT_EXT
);
2197 static int mv643xx_eth_mdio_read(struct net_device
*dev
, int addr
, int reg
)
2199 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2200 return smi_reg_read(mp
, addr
, reg
);
2203 static void mv643xx_eth_mdio_write(struct net_device
*dev
, int addr
, int reg
, int val
)
2205 struct mv643xx_eth_private
*mp
= netdev_priv(dev
);
2206 smi_reg_write(mp
, addr
, reg
, val
);
2210 /* platform glue ************************************************************/
2212 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private
*msp
,
2213 struct mbus_dram_target_info
*dram
)
2215 void __iomem
*base
= msp
->base
;
2220 for (i
= 0; i
< 6; i
++) {
2221 writel(0, base
+ WINDOW_BASE(i
));
2222 writel(0, base
+ WINDOW_SIZE(i
));
2224 writel(0, base
+ WINDOW_REMAP_HIGH(i
));
2230 for (i
= 0; i
< dram
->num_cs
; i
++) {
2231 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
2233 writel((cs
->base
& 0xffff0000) |
2234 (cs
->mbus_attr
<< 8) |
2235 dram
->mbus_dram_target_id
, base
+ WINDOW_BASE(i
));
2236 writel((cs
->size
- 1) & 0xffff0000, base
+ WINDOW_SIZE(i
));
2238 win_enable
&= ~(1 << i
);
2239 win_protect
|= 3 << (2 * i
);
2242 writel(win_enable
, base
+ WINDOW_BAR_ENABLE
);
2243 msp
->win_protect
= win_protect
;
2246 static void infer_hw_params(struct mv643xx_eth_shared_private
*msp
)
2249 * Check whether we have a 14-bit coal limit field in bits
2250 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2251 * SDMA config register.
2253 writel(0x02000000, msp
->base
+ SDMA_CONFIG(0));
2254 if (readl(msp
->base
+ SDMA_CONFIG(0)) & 0x02000000)
2255 msp
->extended_rx_coal_limit
= 1;
2257 msp
->extended_rx_coal_limit
= 0;
2260 * Check whether the TX rate control registers are in the
2261 * old or the new place.
2263 writel(1, msp
->base
+ TX_BW_MTU_MOVED(0));
2264 if (readl(msp
->base
+ TX_BW_MTU_MOVED(0)) & 1)
2265 msp
->tx_bw_control_moved
= 1;
2267 msp
->tx_bw_control_moved
= 0;
2270 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
2272 static int mv643xx_eth_version_printed
= 0;
2273 struct mv643xx_eth_shared_platform_data
*pd
= pdev
->dev
.platform_data
;
2274 struct mv643xx_eth_shared_private
*msp
;
2275 struct resource
*res
;
2278 if (!mv643xx_eth_version_printed
++)
2279 printk(KERN_NOTICE
"MV-643xx 10/100/1000 ethernet "
2280 "driver version %s\n", mv643xx_eth_driver_version
);
2283 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2288 msp
= kmalloc(sizeof(*msp
), GFP_KERNEL
);
2291 memset(msp
, 0, sizeof(*msp
));
2293 msp
->base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
2294 if (msp
->base
== NULL
)
2298 if (pd
!= NULL
&& pd
->shared_smi
!= NULL
)
2299 msp
->smi
= platform_get_drvdata(pd
->shared_smi
);
2301 mutex_init(&msp
->phy_lock
);
2303 msp
->err_interrupt
= NO_IRQ
;
2304 init_waitqueue_head(&msp
->smi_busy_wait
);
2307 * Check whether the error interrupt is hooked up.
2309 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2313 err
= request_irq(res
->start
, mv643xx_eth_err_irq
,
2314 IRQF_SHARED
, "mv643xx_eth", msp
);
2316 writel(ERR_INT_SMI_DONE
, msp
->base
+ ERR_INT_MASK
);
2317 msp
->err_interrupt
= res
->start
;
2322 * (Re-)program MBUS remapping windows if we are asked to.
2324 if (pd
!= NULL
&& pd
->dram
!= NULL
)
2325 mv643xx_eth_conf_mbus_windows(msp
, pd
->dram
);
2328 * Detect hardware parameters.
2330 msp
->t_clk
= (pd
!= NULL
&& pd
->t_clk
!= 0) ? pd
->t_clk
: 133000000;
2331 infer_hw_params(msp
);
2333 platform_set_drvdata(pdev
, msp
);
2343 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
2345 struct mv643xx_eth_shared_private
*msp
= platform_get_drvdata(pdev
);
2347 if (msp
->err_interrupt
!= NO_IRQ
)
2348 free_irq(msp
->err_interrupt
, msp
);
2355 static struct platform_driver mv643xx_eth_shared_driver
= {
2356 .probe
= mv643xx_eth_shared_probe
,
2357 .remove
= mv643xx_eth_shared_remove
,
2359 .name
= MV643XX_ETH_SHARED_NAME
,
2360 .owner
= THIS_MODULE
,
2364 static void phy_addr_set(struct mv643xx_eth_private
*mp
, int phy_addr
)
2366 int addr_shift
= 5 * mp
->port_num
;
2369 data
= rdl(mp
, PHY_ADDR
);
2370 data
&= ~(0x1f << addr_shift
);
2371 data
|= (phy_addr
& 0x1f) << addr_shift
;
2372 wrl(mp
, PHY_ADDR
, data
);
2375 static int phy_addr_get(struct mv643xx_eth_private
*mp
)
2379 data
= rdl(mp
, PHY_ADDR
);
2381 return (data
>> (5 * mp
->port_num
)) & 0x1f;
2384 static void set_params(struct mv643xx_eth_private
*mp
,
2385 struct mv643xx_eth_platform_data
*pd
)
2387 struct net_device
*dev
= mp
->dev
;
2389 if (is_valid_ether_addr(pd
->mac_addr
))
2390 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
2392 uc_addr_get(mp
, dev
->dev_addr
);
2394 if (pd
->phy_addr
== MV643XX_ETH_PHY_NONE
) {
2397 if (pd
->phy_addr
!= MV643XX_ETH_PHY_ADDR_DEFAULT
) {
2398 mp
->phy_addr
= pd
->phy_addr
& 0x3f;
2399 phy_addr_set(mp
, mp
->phy_addr
);
2401 mp
->phy_addr
= phy_addr_get(mp
);
2405 mp
->default_rx_ring_size
= DEFAULT_RX_QUEUE_SIZE
;
2406 if (pd
->rx_queue_size
)
2407 mp
->default_rx_ring_size
= pd
->rx_queue_size
;
2408 mp
->rx_desc_sram_addr
= pd
->rx_sram_addr
;
2409 mp
->rx_desc_sram_size
= pd
->rx_sram_size
;
2411 mp
->rxq_count
= pd
->rx_queue_count
? : 1;
2413 mp
->default_tx_ring_size
= DEFAULT_TX_QUEUE_SIZE
;
2414 if (pd
->tx_queue_size
)
2415 mp
->default_tx_ring_size
= pd
->tx_queue_size
;
2416 mp
->tx_desc_sram_addr
= pd
->tx_sram_addr
;
2417 mp
->tx_desc_sram_size
= pd
->tx_sram_size
;
2419 mp
->txq_count
= pd
->tx_queue_count
? : 1;
2422 static int phy_detect(struct mv643xx_eth_private
*mp
)
2427 data
= smi_reg_read(mp
, mp
->phy_addr
, MII_BMCR
);
2431 if (smi_reg_write(mp
, mp
->phy_addr
, MII_BMCR
, data
^ BMCR_ANENABLE
) < 0)
2434 data2
= smi_reg_read(mp
, mp
->phy_addr
, MII_BMCR
);
2438 if (((data
^ data2
) & BMCR_ANENABLE
) == 0)
2441 smi_reg_write(mp
, mp
->phy_addr
, MII_BMCR
, data
);
2446 static int phy_init(struct mv643xx_eth_private
*mp
,
2447 struct mv643xx_eth_platform_data
*pd
)
2449 struct ethtool_cmd cmd
;
2452 err
= phy_detect(mp
);
2454 dev_printk(KERN_INFO
, &mp
->dev
->dev
,
2455 "no PHY detected at addr %d\n", mp
->phy_addr
);
2460 mp
->mii
.phy_id
= mp
->phy_addr
;
2461 mp
->mii
.phy_id_mask
= 0x3f;
2462 mp
->mii
.reg_num_mask
= 0x1f;
2463 mp
->mii
.dev
= mp
->dev
;
2464 mp
->mii
.mdio_read
= mv643xx_eth_mdio_read
;
2465 mp
->mii
.mdio_write
= mv643xx_eth_mdio_write
;
2467 mp
->mii
.supports_gmii
= mii_check_gmii_support(&mp
->mii
);
2469 memset(&cmd
, 0, sizeof(cmd
));
2471 cmd
.port
= PORT_MII
;
2472 cmd
.transceiver
= XCVR_INTERNAL
;
2473 cmd
.phy_address
= mp
->phy_addr
;
2474 if (pd
->speed
== 0) {
2475 cmd
.autoneg
= AUTONEG_ENABLE
;
2476 cmd
.speed
= SPEED_100
;
2477 cmd
.advertising
= ADVERTISED_10baseT_Half
|
2478 ADVERTISED_10baseT_Full
|
2479 ADVERTISED_100baseT_Half
|
2480 ADVERTISED_100baseT_Full
;
2481 if (mp
->mii
.supports_gmii
)
2482 cmd
.advertising
|= ADVERTISED_1000baseT_Full
;
2484 cmd
.autoneg
= AUTONEG_DISABLE
;
2485 cmd
.speed
= pd
->speed
;
2486 cmd
.duplex
= pd
->duplex
;
2489 mv643xx_eth_set_settings(mp
->dev
, &cmd
);
2494 static void init_pscr(struct mv643xx_eth_private
*mp
, int speed
, int duplex
)
2498 pscr
= rdl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
));
2499 if (pscr
& SERIAL_PORT_ENABLE
) {
2500 pscr
&= ~SERIAL_PORT_ENABLE
;
2501 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), pscr
);
2504 pscr
= MAX_RX_PACKET_9700BYTE
| SERIAL_PORT_CONTROL_RESERVED
;
2505 if (mp
->phy_addr
== -1) {
2506 pscr
|= DISABLE_AUTO_NEG_SPEED_GMII
;
2507 if (speed
== SPEED_1000
)
2508 pscr
|= SET_GMII_SPEED_TO_1000
;
2509 else if (speed
== SPEED_100
)
2510 pscr
|= SET_MII_SPEED_TO_100
;
2512 pscr
|= DISABLE_AUTO_NEG_FOR_FLOW_CTRL
;
2514 pscr
|= DISABLE_AUTO_NEG_FOR_DUPLEX
;
2515 if (duplex
== DUPLEX_FULL
)
2516 pscr
|= SET_FULL_DUPLEX_MODE
;
2519 wrl(mp
, PORT_SERIAL_CONTROL(mp
->port_num
), pscr
);
2522 static int mv643xx_eth_probe(struct platform_device
*pdev
)
2524 struct mv643xx_eth_platform_data
*pd
;
2525 struct mv643xx_eth_private
*mp
;
2526 struct net_device
*dev
;
2527 struct resource
*res
;
2528 DECLARE_MAC_BUF(mac
);
2531 pd
= pdev
->dev
.platform_data
;
2533 dev_printk(KERN_ERR
, &pdev
->dev
,
2534 "no mv643xx_eth_platform_data\n");
2538 if (pd
->shared
== NULL
) {
2539 dev_printk(KERN_ERR
, &pdev
->dev
,
2540 "no mv643xx_eth_platform_data->shared\n");
2544 dev
= alloc_etherdev_mq(sizeof(struct mv643xx_eth_private
), 8);
2548 mp
= netdev_priv(dev
);
2549 platform_set_drvdata(pdev
, mp
);
2551 mp
->shared
= platform_get_drvdata(pd
->shared
);
2552 mp
->port_num
= pd
->port_number
;
2557 dev
->real_num_tx_queues
= mp
->txq_count
;
2559 spin_lock_init(&mp
->lock
);
2561 mib_counters_clear(mp
);
2562 INIT_WORK(&mp
->tx_timeout_task
, tx_timeout_task
);
2564 if (mp
->phy_addr
!= -1) {
2565 err
= phy_init(mp
, pd
);
2569 SET_ETHTOOL_OPS(dev
, &mv643xx_eth_ethtool_ops
);
2571 SET_ETHTOOL_OPS(dev
, &mv643xx_eth_ethtool_ops_phyless
);
2573 init_pscr(mp
, pd
->speed
, pd
->duplex
);
2575 netif_napi_add(dev
, &mp
->napi
, mv643xx_eth_poll
, 128);
2577 init_timer(&mp
->rx_oom
);
2578 mp
->rx_oom
.data
= (unsigned long)mp
;
2579 mp
->rx_oom
.function
= oom_timer_wrapper
;
2582 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2584 dev
->irq
= res
->start
;
2586 dev
->hard_start_xmit
= mv643xx_eth_xmit
;
2587 dev
->open
= mv643xx_eth_open
;
2588 dev
->stop
= mv643xx_eth_stop
;
2589 dev
->set_multicast_list
= mv643xx_eth_set_rx_mode
;
2590 dev
->set_mac_address
= mv643xx_eth_set_mac_address
;
2591 dev
->do_ioctl
= mv643xx_eth_ioctl
;
2592 dev
->change_mtu
= mv643xx_eth_change_mtu
;
2593 dev
->tx_timeout
= mv643xx_eth_tx_timeout
;
2594 #ifdef CONFIG_NET_POLL_CONTROLLER
2595 dev
->poll_controller
= mv643xx_eth_netpoll
;
2597 dev
->watchdog_timeo
= 2 * HZ
;
2600 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2601 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
2603 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2605 if (mp
->shared
->win_protect
)
2606 wrl(mp
, WINDOW_PROTECT(mp
->port_num
), mp
->shared
->win_protect
);
2608 err
= register_netdev(dev
);
2612 dev_printk(KERN_NOTICE
, &dev
->dev
, "port %d with MAC address %s\n",
2613 mp
->port_num
, print_mac(mac
, dev
->dev_addr
));
2615 if (mp
->tx_desc_sram_size
> 0)
2616 dev_printk(KERN_NOTICE
, &dev
->dev
, "configured with sram\n");
2626 static int mv643xx_eth_remove(struct platform_device
*pdev
)
2628 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
2630 unregister_netdev(mp
->dev
);
2631 flush_scheduled_work();
2632 free_netdev(mp
->dev
);
2634 platform_set_drvdata(pdev
, NULL
);
2639 static void mv643xx_eth_shutdown(struct platform_device
*pdev
)
2641 struct mv643xx_eth_private
*mp
= platform_get_drvdata(pdev
);
2643 /* Mask all interrupts on ethernet port */
2644 wrl(mp
, INT_MASK(mp
->port_num
), 0);
2645 rdl(mp
, INT_MASK(mp
->port_num
));
2647 if (netif_running(mp
->dev
))
2651 static struct platform_driver mv643xx_eth_driver
= {
2652 .probe
= mv643xx_eth_probe
,
2653 .remove
= mv643xx_eth_remove
,
2654 .shutdown
= mv643xx_eth_shutdown
,
2656 .name
= MV643XX_ETH_NAME
,
2657 .owner
= THIS_MODULE
,
2661 static int __init
mv643xx_eth_init_module(void)
2665 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
2667 rc
= platform_driver_register(&mv643xx_eth_driver
);
2669 platform_driver_unregister(&mv643xx_eth_shared_driver
);
2674 module_init(mv643xx_eth_init_module
);
2676 static void __exit
mv643xx_eth_cleanup_module(void)
2678 platform_driver_unregister(&mv643xx_eth_driver
);
2679 platform_driver_unregister(&mv643xx_eth_shared_driver
);
2681 module_exit(mv643xx_eth_cleanup_module
);
2683 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2684 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2685 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2686 MODULE_LICENSE("GPL");
2687 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME
);
2688 MODULE_ALIAS("platform:" MV643XX_ETH_NAME
);