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mips: rename offsets.c to asm-offsets.c
[linux-2.6/verdex.git] / arch / i386 / kernel / mpparse.c
blob15949fd081095c76a44b217fdb5fad7384174146
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/irq.h>
18 #include <linux/init.h>
19 #include <linux/acpi.h>
20 #include <linux/delay.h>
21 #include <linux/config.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/bitops.h>
27
28 #include <asm/smp.h>
29 #include <asm/acpi.h>
30 #include <asm/mtrr.h>
31 #include <asm/mpspec.h>
32 #include <asm/io_apic.h>
33
34 #include <mach_apic.h>
35 #include <mach_mpparse.h>
36 #include <bios_ebda.h>
37
38 /* Have we found an MP table */
39 int smp_found_config;
40 unsigned int __initdata maxcpus = NR_CPUS;
41
42 /*
43 * Various Linux-internal data structures created from the
44 * MP-table.
45 */
46 int apic_version [MAX_APICS];
47 int mp_bus_id_to_type [MAX_MP_BUSSES];
48 int mp_bus_id_to_node [MAX_MP_BUSSES];
49 int mp_bus_id_to_local [MAX_MP_BUSSES];
50 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
51 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
52 static int mp_current_pci_id;
53
54 /* I/O APIC entries */
55 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
56
57 /* # of MP IRQ source entries */
58 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
59
60 /* MP IRQ source entries */
61 int mp_irq_entries;
62
63 int nr_ioapics;
64
65 int pic_mode;
66 unsigned long mp_lapic_addr;
67
68 unsigned int def_to_bigsmp = 0;
69
70 /* Processor that is doing the boot up */
71 unsigned int boot_cpu_physical_apicid = -1U;
72 /* Internal processor count */
73 static unsigned int __initdata num_processors;
74
75 /* Bitmask of physically existing CPUs */
76 physid_mask_t phys_cpu_present_map;
77
78 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
79
80 /*
81 * Intel MP BIOS table parsing routines:
82 */
83
84
85 /*
86 * Checksum an MP configuration block.
87 */
88
89 static int __init mpf_checksum(unsigned char *mp, int len)
90 {
91 int sum = 0;
92
93 while (len--)
94 sum += *mp++;
95
96 return sum & 0xFF;
97 }
98
99 /*
100 * Have to match translation table entries to main table entries by counter
101 * hence the mpc_record variable .... can't see a less disgusting way of
102 * doing this ....
103 */
104
105 static int mpc_record;
106 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
107
108 #ifdef CONFIG_X86_NUMAQ
109 static int MP_valid_apicid(int apicid, int version)
110 {
111 return hweight_long(apicid & 0xf) == 1 && (apicid >> 4) != 0xf;
112 }
113 #else
114 static int MP_valid_apicid(int apicid, int version)
115 {
116 if (version >= 0x14)
117 return apicid < 0xff;
118 else
119 return apicid < 0xf;
120 }
121 #endif
122
123 static void __init MP_processor_info (struct mpc_config_processor *m)
124 {
125 int ver, apicid;
126 physid_mask_t phys_cpu;
127
128 if (!(m->mpc_cpuflag & CPU_ENABLED))
129 return;
130
131 apicid = mpc_apic_id(m, translation_table[mpc_record]);
132
133 if (m->mpc_featureflag&(1<<0))
134 Dprintk(" Floating point unit present.\n");
135 if (m->mpc_featureflag&(1<<7))
136 Dprintk(" Machine Exception supported.\n");
137 if (m->mpc_featureflag&(1<<8))
138 Dprintk(" 64 bit compare & exchange supported.\n");
139 if (m->mpc_featureflag&(1<<9))
140 Dprintk(" Internal APIC present.\n");
141 if (m->mpc_featureflag&(1<<11))
142 Dprintk(" SEP present.\n");
143 if (m->mpc_featureflag&(1<<12))
144 Dprintk(" MTRR present.\n");
145 if (m->mpc_featureflag&(1<<13))
146 Dprintk(" PGE present.\n");
147 if (m->mpc_featureflag&(1<<14))
148 Dprintk(" MCA present.\n");
149 if (m->mpc_featureflag&(1<<15))
150 Dprintk(" CMOV present.\n");
151 if (m->mpc_featureflag&(1<<16))
152 Dprintk(" PAT present.\n");
153 if (m->mpc_featureflag&(1<<17))
154 Dprintk(" PSE present.\n");
155 if (m->mpc_featureflag&(1<<18))
156 Dprintk(" PSN present.\n");
157 if (m->mpc_featureflag&(1<<19))
158 Dprintk(" Cache Line Flush Instruction present.\n");
159 /* 20 Reserved */
160 if (m->mpc_featureflag&(1<<21))
161 Dprintk(" Debug Trace and EMON Store present.\n");
162 if (m->mpc_featureflag&(1<<22))
163 Dprintk(" ACPI Thermal Throttle Registers present.\n");
164 if (m->mpc_featureflag&(1<<23))
165 Dprintk(" MMX present.\n");
166 if (m->mpc_featureflag&(1<<24))
167 Dprintk(" FXSR present.\n");
168 if (m->mpc_featureflag&(1<<25))
169 Dprintk(" XMM present.\n");
170 if (m->mpc_featureflag&(1<<26))
171 Dprintk(" Willamette New Instructions present.\n");
172 if (m->mpc_featureflag&(1<<27))
173 Dprintk(" Self Snoop present.\n");
174 if (m->mpc_featureflag&(1<<28))
175 Dprintk(" HT present.\n");
176 if (m->mpc_featureflag&(1<<29))
177 Dprintk(" Thermal Monitor present.\n");
178 /* 30, 31 Reserved */
179
180
181 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
182 Dprintk(" Bootup CPU\n");
183 boot_cpu_physical_apicid = m->mpc_apicid;
184 }
185
186 if (num_processors >= NR_CPUS) {
187 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
188 " Processor ignored.\n", NR_CPUS);
189 return;
190 }
191
192 if (num_processors >= maxcpus) {
193 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
194 " Processor ignored.\n", maxcpus);
195 return;
196 }
197 ver = m->mpc_apicver;
198
199 if (!MP_valid_apicid(apicid, ver)) {
200 printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n",
201 m->mpc_apicid, MAX_APICS);
202 return;
203 }
204
205 cpu_set(num_processors, cpu_possible_map);
206 num_processors++;
207 phys_cpu = apicid_to_cpu_present(apicid);
208 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
209
210 /*
211 * Validate version
212 */
213 if (ver == 0x0) {
214 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
215 "fixing up to 0x10. (tell your hw vendor)\n",
216 m->mpc_apicid);
217 ver = 0x10;
218 }
219 apic_version[m->mpc_apicid] = ver;
220 if ((num_processors > 8) &&
221 APIC_XAPIC(ver) &&
222 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL))
223 def_to_bigsmp = 1;
224 else
225 def_to_bigsmp = 0;
226
227 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
228 }
229
230 static void __init MP_bus_info (struct mpc_config_bus *m)
231 {
232 char str[7];
233
234 memcpy(str, m->mpc_bustype, 6);
235 str[6] = 0;
236
237 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
238
239 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
240 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
241 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
242 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
243 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
244 mpc_oem_pci_bus(m, translation_table[mpc_record]);
245 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
246 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
247 mp_current_pci_id++;
248 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
249 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
250 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
251 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
252 } else {
253 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
254 }
255 }
256
257 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
258 {
259 if (!(m->mpc_flags & MPC_APIC_USABLE))
260 return;
261
262 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%lX.\n",
263 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
264 if (nr_ioapics >= MAX_IO_APICS) {
265 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
266 MAX_IO_APICS, nr_ioapics);
267 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
268 }
269 if (!m->mpc_apicaddr) {
270 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
271 " found in MP table, skipping!\n");
272 return;
273 }
274 mp_ioapics[nr_ioapics] = *m;
275 nr_ioapics++;
276 }
277
278 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
279 {
280 mp_irqs [mp_irq_entries] = *m;
281 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
282 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
283 m->mpc_irqtype, m->mpc_irqflag & 3,
284 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
285 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
286 if (++mp_irq_entries == MAX_IRQ_SOURCES)
287 panic("Max # of irq sources exceeded!!\n");
288 }
289
290 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
291 {
292 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
293 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
294 m->mpc_irqtype, m->mpc_irqflag & 3,
295 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
296 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
297 /*
298 * Well it seems all SMP boards in existence
299 * use ExtINT/LVT1 == LINT0 and
300 * NMI/LVT2 == LINT1 - the following check
301 * will show us if this assumptions is false.
302 * Until then we do not have to add baggage.
303 */
304 if ((m->mpc_irqtype == mp_ExtINT) &&
305 (m->mpc_destapiclint != 0))
306 BUG();
307 if ((m->mpc_irqtype == mp_NMI) &&
308 (m->mpc_destapiclint != 1))
309 BUG();
310 }
311
312 #ifdef CONFIG_X86_NUMAQ
313 static void __init MP_translation_info (struct mpc_config_translation *m)
314 {
315 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
316
317 if (mpc_record >= MAX_MPC_ENTRY)
318 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
319 else
320 translation_table[mpc_record] = m; /* stash this for later */
321 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
322 node_set_online(m->trans_quad);
323 }
324
325 /*
326 * Read/parse the MPC oem tables
327 */
328
329 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
330 unsigned short oemsize)
331 {
332 int count = sizeof (*oemtable); /* the header size */
333 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
334
335 mpc_record = 0;
336 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
337 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
338 {
339 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
340 oemtable->oem_signature[0],
341 oemtable->oem_signature[1],
342 oemtable->oem_signature[2],
343 oemtable->oem_signature[3]);
344 return;
345 }
346 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
347 {
348 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
349 return;
350 }
351 while (count < oemtable->oem_length) {
352 switch (*oemptr) {
353 case MP_TRANSLATION:
354 {
355 struct mpc_config_translation *m=
356 (struct mpc_config_translation *)oemptr;
357 MP_translation_info(m);
358 oemptr += sizeof(*m);
359 count += sizeof(*m);
360 ++mpc_record;
361 break;
362 }
363 default:
364 {
365 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
366 return;
367 }
368 }
369 }
370 }
371
372 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
373 char *productid)
374 {
375 if (strncmp(oem, "IBM NUMA", 8))
376 printk("Warning! May not be a NUMA-Q system!\n");
377 if (mpc->mpc_oemptr)
378 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
379 mpc->mpc_oemsize);
380 }
381 #endif /* CONFIG_X86_NUMAQ */
382
383 /*
384 * Read/parse the MPC
385 */
386
387 static int __init smp_read_mpc(struct mp_config_table *mpc)
388 {
389 char str[16];
390 char oem[10];
391 int count=sizeof(*mpc);
392 unsigned char *mpt=((unsigned char *)mpc)+count;
393
394 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
395 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
396 *(u32 *)mpc->mpc_signature);
397 return 0;
398 }
399 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
400 printk(KERN_ERR "SMP mptable: checksum error!\n");
401 return 0;
402 }
403 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
404 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
405 mpc->mpc_spec);
406 return 0;
407 }
408 if (!mpc->mpc_lapic) {
409 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
410 return 0;
411 }
412 memcpy(oem,mpc->mpc_oem,8);
413 oem[8]=0;
414 printk(KERN_INFO "OEM ID: %s ",oem);
415
416 memcpy(str,mpc->mpc_productid,12);
417 str[12]=0;
418 printk("Product ID: %s ",str);
419
420 mps_oem_check(mpc, oem, str);
421
422 printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
423
424 /*
425 * Save the local APIC address (it might be non-default) -- but only
426 * if we're not using ACPI.
427 */
428 if (!acpi_lapic)
429 mp_lapic_addr = mpc->mpc_lapic;
430
431 /*
432 * Now process the configuration blocks.
433 */
434 mpc_record = 0;
435 while (count < mpc->mpc_length) {
436 switch(*mpt) {
437 case MP_PROCESSOR:
438 {
439 struct mpc_config_processor *m=
440 (struct mpc_config_processor *)mpt;
441 /* ACPI may have already provided this data */
442 if (!acpi_lapic)
443 MP_processor_info(m);
444 mpt += sizeof(*m);
445 count += sizeof(*m);
446 break;
447 }
448 case MP_BUS:
449 {
450 struct mpc_config_bus *m=
451 (struct mpc_config_bus *)mpt;
452 MP_bus_info(m);
453 mpt += sizeof(*m);
454 count += sizeof(*m);
455 break;
456 }
457 case MP_IOAPIC:
458 {
459 struct mpc_config_ioapic *m=
460 (struct mpc_config_ioapic *)mpt;
461 MP_ioapic_info(m);
462 mpt+=sizeof(*m);
463 count+=sizeof(*m);
464 break;
465 }
466 case MP_INTSRC:
467 {
468 struct mpc_config_intsrc *m=
469 (struct mpc_config_intsrc *)mpt;
470
471 MP_intsrc_info(m);
472 mpt+=sizeof(*m);
473 count+=sizeof(*m);
474 break;
475 }
476 case MP_LINTSRC:
477 {
478 struct mpc_config_lintsrc *m=
479 (struct mpc_config_lintsrc *)mpt;
480 MP_lintsrc_info(m);
481 mpt+=sizeof(*m);
482 count+=sizeof(*m);
483 break;
484 }
485 default:
486 {
487 count = mpc->mpc_length;
488 break;
489 }
490 }
491 ++mpc_record;
492 }
493 clustered_apic_check();
494 if (!num_processors)
495 printk(KERN_ERR "SMP mptable: no processors registered!\n");
496 return num_processors;
497 }
498
499 static int __init ELCR_trigger(unsigned int irq)
500 {
501 unsigned int port;
502
503 port = 0x4d0 + (irq >> 3);
504 return (inb(port) >> (irq & 7)) & 1;
505 }
506
507 static void __init construct_default_ioirq_mptable(int mpc_default_type)
508 {
509 struct mpc_config_intsrc intsrc;
510 int i;
511 int ELCR_fallback = 0;
512
513 intsrc.mpc_type = MP_INTSRC;
514 intsrc.mpc_irqflag = 0; /* conforming */
515 intsrc.mpc_srcbus = 0;
516 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
517
518 intsrc.mpc_irqtype = mp_INT;
519
520 /*
521 * If true, we have an ISA/PCI system with no IRQ entries
522 * in the MP table. To prevent the PCI interrupts from being set up
523 * incorrectly, we try to use the ELCR. The sanity check to see if
524 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
525 * never be level sensitive, so we simply see if the ELCR agrees.
526 * If it does, we assume it's valid.
527 */
528 if (mpc_default_type == 5) {
529 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
530
531 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
532 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
533 else {
534 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
535 ELCR_fallback = 1;
536 }
537 }
538
539 for (i = 0; i < 16; i++) {
540 switch (mpc_default_type) {
541 case 2:
542 if (i == 0 || i == 13)
543 continue; /* IRQ0 & IRQ13 not connected */
544 /* fall through */
545 default:
546 if (i == 2)
547 continue; /* IRQ2 is never connected */
548 }
549
550 if (ELCR_fallback) {
551 /*
552 * If the ELCR indicates a level-sensitive interrupt, we
553 * copy that information over to the MP table in the
554 * irqflag field (level sensitive, active high polarity).
555 */
556 if (ELCR_trigger(i))
557 intsrc.mpc_irqflag = 13;
558 else
559 intsrc.mpc_irqflag = 0;
560 }
561
562 intsrc.mpc_srcbusirq = i;
563 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
564 MP_intsrc_info(&intsrc);
565 }
566
567 intsrc.mpc_irqtype = mp_ExtINT;
568 intsrc.mpc_srcbusirq = 0;
569 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
570 MP_intsrc_info(&intsrc);
571 }
572
573 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
574 {
575 struct mpc_config_processor processor;
576 struct mpc_config_bus bus;
577 struct mpc_config_ioapic ioapic;
578 struct mpc_config_lintsrc lintsrc;
579 int linttypes[2] = { mp_ExtINT, mp_NMI };
580 int i;
581
582 /*
583 * local APIC has default address
584 */
585 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
586
587 /*
588 * 2 CPUs, numbered 0 & 1.
589 */
590 processor.mpc_type = MP_PROCESSOR;
591 /* Either an integrated APIC or a discrete 82489DX. */
592 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
593 processor.mpc_cpuflag = CPU_ENABLED;
594 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
595 (boot_cpu_data.x86_model << 4) |
596 boot_cpu_data.x86_mask;
597 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
598 processor.mpc_reserved[0] = 0;
599 processor.mpc_reserved[1] = 0;
600 for (i = 0; i < 2; i++) {
601 processor.mpc_apicid = i;
602 MP_processor_info(&processor);
603 }
604
605 bus.mpc_type = MP_BUS;
606 bus.mpc_busid = 0;
607 switch (mpc_default_type) {
608 default:
609 printk("???\n");
610 printk(KERN_ERR "Unknown standard configuration %d\n",
611 mpc_default_type);
612 /* fall through */
613 case 1:
614 case 5:
615 memcpy(bus.mpc_bustype, "ISA ", 6);
616 break;
617 case 2:
618 case 6:
619 case 3:
620 memcpy(bus.mpc_bustype, "EISA ", 6);
621 break;
622 case 4:
623 case 7:
624 memcpy(bus.mpc_bustype, "MCA ", 6);
625 }
626 MP_bus_info(&bus);
627 if (mpc_default_type > 4) {
628 bus.mpc_busid = 1;
629 memcpy(bus.mpc_bustype, "PCI ", 6);
630 MP_bus_info(&bus);
631 }
632
633 ioapic.mpc_type = MP_IOAPIC;
634 ioapic.mpc_apicid = 2;
635 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
636 ioapic.mpc_flags = MPC_APIC_USABLE;
637 ioapic.mpc_apicaddr = 0xFEC00000;
638 MP_ioapic_info(&ioapic);
639
640 /*
641 * We set up most of the low 16 IO-APIC pins according to MPS rules.
642 */
643 construct_default_ioirq_mptable(mpc_default_type);
644
645 lintsrc.mpc_type = MP_LINTSRC;
646 lintsrc.mpc_irqflag = 0; /* conforming */
647 lintsrc.mpc_srcbusid = 0;
648 lintsrc.mpc_srcbusirq = 0;
649 lintsrc.mpc_destapic = MP_APIC_ALL;
650 for (i = 0; i < 2; i++) {
651 lintsrc.mpc_irqtype = linttypes[i];
652 lintsrc.mpc_destapiclint = i;
653 MP_lintsrc_info(&lintsrc);
654 }
655 }
656
657 static struct intel_mp_floating *mpf_found;
658
659 /*
660 * Scan the memory blocks for an SMP configuration block.
661 */
662 void __init get_smp_config (void)
663 {
664 struct intel_mp_floating *mpf = mpf_found;
665
666 /*
667 * ACPI supports both logical (e.g. Hyper-Threading) and physical
668 * processors, where MPS only supports physical.
669 */
670 if (acpi_lapic && acpi_ioapic) {
671 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
672 return;
673 }
674 else if (acpi_lapic)
675 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
676
677 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
678 if (mpf->mpf_feature2 & (1<<7)) {
679 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
680 pic_mode = 1;
681 } else {
682 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
683 pic_mode = 0;
684 }
685
686 /*
687 * Now see if we need to read further.
688 */
689 if (mpf->mpf_feature1 != 0) {
690
691 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
692 construct_default_ISA_mptable(mpf->mpf_feature1);
693
694 } else if (mpf->mpf_physptr) {
695
696 /*
697 * Read the physical hardware table. Anything here will
698 * override the defaults.
699 */
700 if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
701 smp_found_config = 0;
702 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
703 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
704 return;
705 }
706 /*
707 * If there are no explicit MP IRQ entries, then we are
708 * broken. We set up most of the low 16 IO-APIC pins to
709 * ISA defaults and hope it will work.
710 */
711 if (!mp_irq_entries) {
712 struct mpc_config_bus bus;
713
714 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
715
716 bus.mpc_type = MP_BUS;
717 bus.mpc_busid = 0;
718 memcpy(bus.mpc_bustype, "ISA ", 6);
719 MP_bus_info(&bus);
720
721 construct_default_ioirq_mptable(0);
722 }
723
724 } else
725 BUG();
726
727 printk(KERN_INFO "Processors: %d\n", num_processors);
728 /*
729 * Only use the first configuration found.
730 */
731 }
732
733 static int __init smp_scan_config (unsigned long base, unsigned long length)
734 {
735 unsigned long *bp = phys_to_virt(base);
736 struct intel_mp_floating *mpf;
737
738 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
739 if (sizeof(*mpf) != 16)
740 printk("Error: MPF size\n");
741
742 while (length > 0) {
743 mpf = (struct intel_mp_floating *)bp;
744 if ((*bp == SMP_MAGIC_IDENT) &&
745 (mpf->mpf_length == 1) &&
746 !mpf_checksum((unsigned char *)bp, 16) &&
747 ((mpf->mpf_specification == 1)
748 || (mpf->mpf_specification == 4)) ) {
749
750 smp_found_config = 1;
751 printk(KERN_INFO "found SMP MP-table at %08lx\n",
752 virt_to_phys(mpf));
753 reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
754 if (mpf->mpf_physptr) {
755 /*
756 * We cannot access to MPC table to compute
757 * table size yet, as only few megabytes from
758 * the bottom is mapped now.
759 * PC-9800's MPC table places on the very last
760 * of physical memory; so that simply reserving
761 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
762 * in reserve_bootmem.
763 */
764 unsigned long size = PAGE_SIZE;
765 unsigned long end = max_low_pfn * PAGE_SIZE;
766 if (mpf->mpf_physptr + size > end)
767 size = end - mpf->mpf_physptr;
768 reserve_bootmem(mpf->mpf_physptr, size);
769 }
770
771 mpf_found = mpf;
772 return 1;
773 }
774 bp += 4;
775 length -= 16;
776 }
777 return 0;
778 }
779
780 void __init find_smp_config (void)
781 {
782 unsigned int address;
783
784 /*
785 * FIXME: Linux assumes you have 640K of base ram..
786 * this continues the error...
787 *
788 * 1) Scan the bottom 1K for a signature
789 * 2) Scan the top 1K of base RAM
790 * 3) Scan the 64K of bios
791 */
792 if (smp_scan_config(0x0,0x400) ||
793 smp_scan_config(639*0x400,0x400) ||
794 smp_scan_config(0xF0000,0x10000))
795 return;
796 /*
797 * If it is an SMP machine we should know now, unless the
798 * configuration is in an EISA/MCA bus machine with an
799 * extended bios data area.
800 *
801 * there is a real-mode segmented pointer pointing to the
802 * 4K EBDA area at 0x40E, calculate and scan it here.
803 *
804 * NOTE! There are Linux loaders that will corrupt the EBDA
805 * area, and as such this kind of SMP config may be less
806 * trustworthy, simply because the SMP table may have been
807 * stomped on during early boot. These loaders are buggy and
808 * should be fixed.
809 *
810 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
811 */
812
813 address = get_bios_ebda();
814 if (address)
815 smp_scan_config(address, 0x400);
816 }
817
818 /* --------------------------------------------------------------------------
819 ACPI-based MP Configuration
820 -------------------------------------------------------------------------- */
821
822 #ifdef CONFIG_ACPI
823
824 void __init mp_register_lapic_address (
825 u64 address)
826 {
827 mp_lapic_addr = (unsigned long) address;
828
829 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
830
831 if (boot_cpu_physical_apicid == -1U)
832 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
833
834 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
835 }
836
837
838 void __init mp_register_lapic (
839 u8 id,
840 u8 enabled)
841 {
842 struct mpc_config_processor processor;
843 int boot_cpu = 0;
844
845 if (MAX_APICS - id <= 0) {
846 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
847 id, MAX_APICS);
848 return;
849 }
850
851 if (id == boot_cpu_physical_apicid)
852 boot_cpu = 1;
853
854 processor.mpc_type = MP_PROCESSOR;
855 processor.mpc_apicid = id;
856 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
857 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
858 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
859 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
860 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
861 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
862 processor.mpc_reserved[0] = 0;
863 processor.mpc_reserved[1] = 0;
864
865 MP_processor_info(&processor);
866 }
867
868 #ifdef CONFIG_X86_IO_APIC
869
870 #define MP_ISA_BUS 0
871 #define MP_MAX_IOAPIC_PIN 127
872
873 static struct mp_ioapic_routing {
874 int apic_id;
875 int gsi_base;
876 int gsi_end;
877 u32 pin_programmed[4];
878 } mp_ioapic_routing[MAX_IO_APICS];
879
880
881 static int mp_find_ioapic (
882 int gsi)
883 {
884 int i = 0;
885
886 /* Find the IOAPIC that manages this GSI. */
887 for (i = 0; i < nr_ioapics; i++) {
888 if ((gsi >= mp_ioapic_routing[i].gsi_base)
889 && (gsi <= mp_ioapic_routing[i].gsi_end))
890 return i;
891 }
892
893 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
894
895 return -1;
896 }
897
898
899 void __init mp_register_ioapic (
900 u8 id,
901 u32 address,
902 u32 gsi_base)
903 {
904 int idx = 0;
905
906 if (nr_ioapics >= MAX_IO_APICS) {
907 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
908 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
909 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
910 }
911 if (!address) {
912 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
913 " found in MADT table, skipping!\n");
914 return;
915 }
916
917 idx = nr_ioapics++;
918
919 mp_ioapics[idx].mpc_type = MP_IOAPIC;
920 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
921 mp_ioapics[idx].mpc_apicaddr = address;
922
923 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
924 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15))
925 mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
926 else
927 mp_ioapics[idx].mpc_apicid = id;
928 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
929
930 /*
931 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
932 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
933 */
934 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
935 mp_ioapic_routing[idx].gsi_base = gsi_base;
936 mp_ioapic_routing[idx].gsi_end = gsi_base +
937 io_apic_get_redir_entries(idx);
938
939 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%lx, "
940 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
941 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
942 mp_ioapic_routing[idx].gsi_base,
943 mp_ioapic_routing[idx].gsi_end);
944
945 return;
946 }
947
948
949 void __init mp_override_legacy_irq (
950 u8 bus_irq,
951 u8 polarity,
952 u8 trigger,
953 u32 gsi)
954 {
955 struct mpc_config_intsrc intsrc;
956 int ioapic = -1;
957 int pin = -1;
958
959 /*
960 * Convert 'gsi' to 'ioapic.pin'.
961 */
962 ioapic = mp_find_ioapic(gsi);
963 if (ioapic < 0)
964 return;
965 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
966
967 /*
968 * TBD: This check is for faulty timer entries, where the override
969 * erroneously sets the trigger to level, resulting in a HUGE
970 * increase of timer interrupts!
971 */
972 if ((bus_irq == 0) && (trigger == 3))
973 trigger = 1;
974
975 intsrc.mpc_type = MP_INTSRC;
976 intsrc.mpc_irqtype = mp_INT;
977 intsrc.mpc_irqflag = (trigger << 2) | polarity;
978 intsrc.mpc_srcbus = MP_ISA_BUS;
979 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
980 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
981 intsrc.mpc_dstirq = pin; /* INTIN# */
982
983 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
984 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
985 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
986 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
987
988 mp_irqs[mp_irq_entries] = intsrc;
989 if (++mp_irq_entries == MAX_IRQ_SOURCES)
990 panic("Max # of irq sources exceeded!\n");
991
992 return;
993 }
994
995 int es7000_plat;
996
997 void __init mp_config_acpi_legacy_irqs (void)
998 {
999 struct mpc_config_intsrc intsrc;
1000 int i = 0;
1001 int ioapic = -1;
1002
1003 /*
1004 * Fabricate the legacy ISA bus (bus #31).
1005 */
1006 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1007 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1008
1009 /*
1010 * Older generations of ES7000 have no legacy identity mappings
1011 */
1012 if (es7000_plat == 1)
1013 return;
1014
1015 /*
1016 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1017 */
1018 ioapic = mp_find_ioapic(0);
1019 if (ioapic < 0)
1020 return;
1021
1022 intsrc.mpc_type = MP_INTSRC;
1023 intsrc.mpc_irqflag = 0; /* Conforming */
1024 intsrc.mpc_srcbus = MP_ISA_BUS;
1025 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1026
1027 /*
1028 * Use the default configuration for the IRQs 0-15. Unless
1029 * overriden by (MADT) interrupt source override entries.
1030 */
1031 for (i = 0; i < 16; i++) {
1032 int idx;
1033
1034 for (idx = 0; idx < mp_irq_entries; idx++) {
1035 struct mpc_config_intsrc *irq = mp_irqs + idx;
1036
1037 /* Do we already have a mapping for this ISA IRQ? */
1038 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1039 break;
1040
1041 /* Do we already have a mapping for this IOAPIC pin */
1042 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1043 (irq->mpc_dstirq == i))
1044 break;
1045 }
1046
1047 if (idx != mp_irq_entries) {
1048 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1049 continue; /* IRQ already used */
1050 }
1051
1052 intsrc.mpc_irqtype = mp_INT;
1053 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1054 intsrc.mpc_dstirq = i;
1055
1056 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1057 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1058 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1059 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1060 intsrc.mpc_dstirq);
1061
1062 mp_irqs[mp_irq_entries] = intsrc;
1063 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1064 panic("Max # of irq sources exceeded!\n");
1065 }
1066 }
1067
1068 #define MAX_GSI_NUM 4096
1069
1070 int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
1071 {
1072 int ioapic = -1;
1073 int ioapic_pin = 0;
1074 int idx, bit = 0;
1075 static int pci_irq = 16;
1076 /*
1077 * Mapping between Global System Interrups, which
1078 * represent all possible interrupts, and IRQs
1079 * assigned to actual devices.
1080 */
1081 static int gsi_to_irq[MAX_GSI_NUM];
1082
1083 /* Don't set up the ACPI SCI because it's already set up */
1084 if (acpi_fadt.sci_int == gsi)
1085 return gsi;
1086
1087 ioapic = mp_find_ioapic(gsi);
1088 if (ioapic < 0) {
1089 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1090 return gsi;
1091 }
1092
1093 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1094
1095 if (ioapic_renumber_irq)
1096 gsi = ioapic_renumber_irq(ioapic, gsi);
1097
1098 /*
1099 * Avoid pin reprogramming. PRTs typically include entries
1100 * with redundant pin->gsi mappings (but unique PCI devices);
1101 * we only program the IOAPIC on the first.
1102 */
1103 bit = ioapic_pin % 32;
1104 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1105 if (idx > 3) {
1106 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1107 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1108 ioapic_pin);
1109 return gsi;
1110 }
1111 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1112 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1113 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1114 return gsi_to_irq[gsi];
1115 }
1116
1117 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1118
1119 if (edge_level) {
1120 /*
1121 * For PCI devices assign IRQs in order, avoiding gaps
1122 * due to unused I/O APIC pins.
1123 */
1124 int irq = gsi;
1125 if (gsi < MAX_GSI_NUM) {
1126 if (gsi > 15)
1127 gsi = pci_irq++;
1128 /*
1129 * Don't assign IRQ used by ACPI SCI
1130 */
1131 if (gsi == acpi_fadt.sci_int)
1132 gsi = pci_irq++;
1133 gsi_to_irq[irq] = gsi;
1134 } else {
1135 printk(KERN_ERR "GSI %u is too high\n", gsi);
1136 return gsi;
1137 }
1138 }
1139
1140 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1141 edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
1142 active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
1143 return gsi;
1144 }
1145
1146 #endif /* CONFIG_X86_IO_APIC */
1147 #endif /* CONFIG_ACPI */
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