arch/i386/kernel/nmi.c

   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/mm.h>
  18 #include <linux/irq.h>
  19 #include <linux/delay.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/mc146818rtc.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/module.h>
  26 #include <linux/nmi.h>
  27 #include <linux/sysdev.h>
  28 #include <linux/sysctl.h>
  29
  30 #include <asm/smp.h>
  31 #include <asm/div64.h>
  32 #include <asm/nmi.h>
  33
  34 #include "mach_traps.h"
  35
  36 unsigned int nmi_watchdog = NMI_NONE;
  37 extern int unknown_nmi_panic;
  38 static unsigned int nmi_hz = HZ;
  39 static unsigned int nmi_perfctr_msr;    /* the MSR to reset in NMI handler */
  40 static unsigned int nmi_p4_cccr_val;
  41 extern void show_registers(struct pt_regs *regs);
  42
  43 /*
  44  * lapic_nmi_owner tracks the ownership of the lapic NMI hardware:
  45  * - it may be reserved by some other driver, or not
  46  * - when not reserved by some other driver, it may be used for
  47  *   the NMI watchdog, or not
  48  *
  49  * This is maintained separately from nmi_active because the NMI
  50  * watchdog may also be driven from the I/O APIC timer.
  51  */
  52 static DEFINE_SPINLOCK(lapic_nmi_owner_lock);
  53 static unsigned int lapic_nmi_owner;
  54 #define LAPIC_NMI_WATCHDOG      (1<<0)
  55 #define LAPIC_NMI_RESERVED      (1<<1)
  56
  57 /* nmi_active:
  58  * +1: the lapic NMI watchdog is active, but can be disabled
  59  *  0: the lapic NMI watchdog has not been set up, and cannot
  60  *     be enabled
  61  * -1: the lapic NMI watchdog is disabled, but can be enabled
  62  */
  63 int nmi_active;
  64
  65 #define K7_EVNTSEL_ENABLE       (1 << 22)
  66 #define K7_EVNTSEL_INT          (1 << 20)
  67 #define K7_EVNTSEL_OS           (1 << 17)
  68 #define K7_EVNTSEL_USR          (1 << 16)
  69 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
  70 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
  71
  72 #define P6_EVNTSEL0_ENABLE      (1 << 22)
  73 #define P6_EVNTSEL_INT          (1 << 20)
  74 #define P6_EVNTSEL_OS           (1 << 17)
  75 #define P6_EVNTSEL_USR          (1 << 16)
  76 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
  77 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
  78
  79 #define MSR_P4_MISC_ENABLE      0x1A0
  80 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
  81 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
  82 #define MSR_P4_PERFCTR0         0x300
  83 #define MSR_P4_CCCR0            0x360
  84 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
  85 #define P4_ESCR_OS              (1<<3)
  86 #define P4_ESCR_USR             (1<<2)
  87 #define P4_CCCR_OVF_PMI0        (1<<26)
  88 #define P4_CCCR_OVF_PMI1        (1<<27)
  89 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
  90 #define P4_CCCR_COMPLEMENT      (1<<19)
  91 #define P4_CCCR_COMPARE         (1<<18)
  92 #define P4_CCCR_REQUIRED        (3<<16)
  93 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
  94 #define P4_CCCR_ENABLE          (1<<12)
  95 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
  96    CRU_ESCR0 (with any non-null event selector) through a complemented
  97    max threshold. [IA32-Vol3, Section 14.9.9] */
  98 #define MSR_P4_IQ_COUNTER0      0x30C
  99 #define P4_NMI_CRU_ESCR0        (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
 100 #define P4_NMI_IQ_CCCR0 \
 101         (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|     \
 102          P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
 103
 104 static int __init check_nmi_watchdog(void)
 105 {
 106         unsigned int prev_nmi_count[NR_CPUS];
 107         int cpu;
 108
 109         if (nmi_watchdog == NMI_NONE)
 110                 return 0;
 111
 112         printk(KERN_INFO "Testing NMI watchdog ... ");
 113
 114         for (cpu = 0; cpu < NR_CPUS; cpu++)
 115                 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
 116         local_irq_enable();
 117         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 118
 119         for (cpu = 0; cpu < NR_CPUS; cpu++) {
 120 #ifdef CONFIG_SMP
 121                 /* Check cpu_callin_map here because that is set
 122                    after the timer is started. */
 123                 if (!cpu_isset(cpu, cpu_callin_map))
 124                         continue;
 125 #endif
 126                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 127                         printk("CPU#%d: NMI appears to be stuck!\n", cpu);
 128                         nmi_active = 0;
 129                         lapic_nmi_owner &= ~LAPIC_NMI_WATCHDOG;
 130                         return -1;
 131                 }
 132         }
 133         printk("OK.\n");
 134
 135         /* now that we know it works we can reduce NMI frequency to
 136            something more reasonable; makes a difference in some configs */
 137         if (nmi_watchdog == NMI_LOCAL_APIC)
 138                 nmi_hz = 1;
 139
 140         return 0;
 141 }
 142 /* This needs to happen later in boot so counters are working */
 143 late_initcall(check_nmi_watchdog);
 144
 145 static int __init setup_nmi_watchdog(char *str)
 146 {
 147         int nmi;
 148
 149         get_option(&str, &nmi);
 150
 151         if (nmi >= NMI_INVALID)
 152                 return 0;
 153         if (nmi == NMI_NONE)
 154                 nmi_watchdog = nmi;
 155         /*
 156          * If any other x86 CPU has a local APIC, then
 157          * please test the NMI stuff there and send me the
 158          * missing bits. Right now Intel P6/P4 and AMD K7 only.
 159          */
 160         if ((nmi == NMI_LOCAL_APIC) &&
 161                         (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
 162                         (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 163                 nmi_watchdog = nmi;
 164         if ((nmi == NMI_LOCAL_APIC) &&
 165                         (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
 166                         (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15))
 167                 nmi_watchdog = nmi;
 168         /*
 169          * We can enable the IO-APIC watchdog
 170          * unconditionally.
 171          */
 172         if (nmi == NMI_IO_APIC) {
 173                 nmi_active = 1;
 174                 nmi_watchdog = nmi;
 175         }
 176         return 1;
 177 }
 178
 179 __setup("nmi_watchdog=", setup_nmi_watchdog);
 180
 181 static void disable_lapic_nmi_watchdog(void)
 182 {
 183         if (nmi_active <= 0)
 184                 return;
 185         switch (boot_cpu_data.x86_vendor) {
 186         case X86_VENDOR_AMD:
 187                 wrmsr(MSR_K7_EVNTSEL0, 0, 0);
 188                 break;
 189         case X86_VENDOR_INTEL:
 190                 switch (boot_cpu_data.x86) {
 191                 case 6:
 192                         if (boot_cpu_data.x86_model > 0xd)
 193                                 break;
 194
 195                         wrmsr(MSR_P6_EVNTSEL0, 0, 0);
 196                         break;
 197                 case 15:
 198                         if (boot_cpu_data.x86_model > 0x4)
 199                                 break;
 200
 201                         wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
 202                         wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
 203                         break;
 204                 }
 205                 break;
 206         }
 207         nmi_active = -1;
 208         /* tell do_nmi() and others that we're not active any more */
 209         nmi_watchdog = 0;
 210 }
 211
 212 static void enable_lapic_nmi_watchdog(void)
 213 {
 214         if (nmi_active < 0) {
 215                 nmi_watchdog = NMI_LOCAL_APIC;
 216                 setup_apic_nmi_watchdog();
 217         }
 218 }
 219
 220 int reserve_lapic_nmi(void)
 221 {
 222         unsigned int old_owner;
 223
 224         spin_lock(&lapic_nmi_owner_lock);
 225         old_owner = lapic_nmi_owner;
 226         lapic_nmi_owner |= LAPIC_NMI_RESERVED;
 227         spin_unlock(&lapic_nmi_owner_lock);
 228         if (old_owner & LAPIC_NMI_RESERVED)
 229                 return -EBUSY;
 230         if (old_owner & LAPIC_NMI_WATCHDOG)
 231                 disable_lapic_nmi_watchdog();
 232         return 0;
 233 }
 234
 235 void release_lapic_nmi(void)
 236 {
 237         unsigned int new_owner;
 238
 239         spin_lock(&lapic_nmi_owner_lock);
 240         new_owner = lapic_nmi_owner & ~LAPIC_NMI_RESERVED;
 241         lapic_nmi_owner = new_owner;
 242         spin_unlock(&lapic_nmi_owner_lock);
 243         if (new_owner & LAPIC_NMI_WATCHDOG)
 244                 enable_lapic_nmi_watchdog();
 245 }
 246
 247 void disable_timer_nmi_watchdog(void)
 248 {
 249         if ((nmi_watchdog != NMI_IO_APIC) || (nmi_active <= 0))
 250                 return;
 251
 252         unset_nmi_callback();
 253         nmi_active = -1;
 254         nmi_watchdog = NMI_NONE;
 255 }
 256
 257 void enable_timer_nmi_watchdog(void)
 258 {
 259         if (nmi_active < 0) {
 260                 nmi_watchdog = NMI_IO_APIC;
 261                 touch_nmi_watchdog();
 262                 nmi_active = 1;
 263         }
 264 }
 265
 266 #ifdef CONFIG_PM
 267
 268 static int nmi_pm_active; /* nmi_active before suspend */
 269
 270 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 271 {
 272         nmi_pm_active = nmi_active;
 273         disable_lapic_nmi_watchdog();
 274         return 0;
 275 }
 276
 277 static int lapic_nmi_resume(struct sys_device *dev)
 278 {
 279         if (nmi_pm_active > 0)
 280                 enable_lapic_nmi_watchdog();
 281         return 0;
 282 }
 283
 284
 285 static struct sysdev_class nmi_sysclass = {
 286         set_kset_name("lapic_nmi"),
 287         .resume         = lapic_nmi_resume,
 288         .suspend        = lapic_nmi_suspend,
 289 };
 290
 291 static struct sys_device device_lapic_nmi = {
 292         .id     = 0,
 293         .cls    = &nmi_sysclass,
 294 };
 295
 296 static int __init init_lapic_nmi_sysfs(void)
 297 {
 298         int error;
 299
 300         if (nmi_active == 0 || nmi_watchdog != NMI_LOCAL_APIC)
 301                 return 0;
 302
 303         error = sysdev_class_register(&nmi_sysclass);
 304         if (!error)
 305                 error = sysdev_register(&device_lapic_nmi);
 306         return error;
 307 }
 308 /* must come after the local APIC's device_initcall() */
 309 late_initcall(init_lapic_nmi_sysfs);
 310
 311 #endif  /* CONFIG_PM */
 312
 313 /*
 314  * Activate the NMI watchdog via the local APIC.
 315  * Original code written by Keith Owens.
 316  */
 317
 318 static void clear_msr_range(unsigned int base, unsigned int n)
 319 {
 320         unsigned int i;
 321
 322         for(i = 0; i < n; ++i)
 323                 wrmsr(base+i, 0, 0);
 324 }
 325
 326 static inline void write_watchdog_counter(const char *descr)
 327 {
 328         u64 count = (u64)cpu_khz * 1000;
 329
 330         do_div(count, nmi_hz);
 331         if(descr)
 332                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 333         wrmsrl(nmi_perfctr_msr, 0 - count);
 334 }
 335
 336 static void setup_k7_watchdog(void)
 337 {
 338         unsigned int evntsel;
 339
 340         nmi_perfctr_msr = MSR_K7_PERFCTR0;
 341
 342         clear_msr_range(MSR_K7_EVNTSEL0, 4);
 343         clear_msr_range(MSR_K7_PERFCTR0, 4);
 344
 345         evntsel = K7_EVNTSEL_INT
 346                 | K7_EVNTSEL_OS
 347                 | K7_EVNTSEL_USR
 348                 | K7_NMI_EVENT;
 349
 350         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 351         write_watchdog_counter("K7_PERFCTR0");
 352         apic_write(APIC_LVTPC, APIC_DM_NMI);
 353         evntsel |= K7_EVNTSEL_ENABLE;
 354         wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
 355 }
 356
 357 static void setup_p6_watchdog(void)
 358 {
 359         unsigned int evntsel;
 360
 361         nmi_perfctr_msr = MSR_P6_PERFCTR0;
 362
 363         clear_msr_range(MSR_P6_EVNTSEL0, 2);
 364         clear_msr_range(MSR_P6_PERFCTR0, 2);
 365
 366         evntsel = P6_EVNTSEL_INT
 367                 | P6_EVNTSEL_OS
 368                 | P6_EVNTSEL_USR
 369                 | P6_NMI_EVENT;
 370
 371         wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
 372         write_watchdog_counter("P6_PERFCTR0");
 373         apic_write(APIC_LVTPC, APIC_DM_NMI);
 374         evntsel |= P6_EVNTSEL0_ENABLE;
 375         wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
 376 }
 377
 378 static int setup_p4_watchdog(void)
 379 {
 380         unsigned int misc_enable, dummy;
 381
 382         rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
 383         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 384                 return 0;
 385
 386         nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
 387         nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
 388 #ifdef CONFIG_SMP
 389         if (smp_num_siblings == 2)
 390                 nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
 391 #endif
 392
 393         if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
 394                 clear_msr_range(0x3F1, 2);
 395         /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
 396            docs doesn't fully define it, so leave it alone for now. */
 397         if (boot_cpu_data.x86_model >= 0x3) {
 398                 /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
 399                 clear_msr_range(0x3A0, 26);
 400                 clear_msr_range(0x3BC, 3);
 401         } else {
 402                 clear_msr_range(0x3A0, 31);
 403         }
 404         clear_msr_range(0x3C0, 6);
 405         clear_msr_range(0x3C8, 6);
 406         clear_msr_range(0x3E0, 2);
 407         clear_msr_range(MSR_P4_CCCR0, 18);
 408         clear_msr_range(MSR_P4_PERFCTR0, 18);
 409
 410         wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
 411         wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
 412         write_watchdog_counter("P4_IQ_COUNTER0");
 413         apic_write(APIC_LVTPC, APIC_DM_NMI);
 414         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 415         return 1;
 416 }
 417
 418 void setup_apic_nmi_watchdog (void)
 419 {
 420         switch (boot_cpu_data.x86_vendor) {
 421         case X86_VENDOR_AMD:
 422                 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
 423                         return;
 424                 setup_k7_watchdog();
 425                 break;
 426         case X86_VENDOR_INTEL:
 427                 switch (boot_cpu_data.x86) {
 428                 case 6:
 429                         if (boot_cpu_data.x86_model > 0xd)
 430                                 return;
 431
 432                         setup_p6_watchdog();
 433                         break;
 434                 case 15:
 435                         if (boot_cpu_data.x86_model > 0x4)
 436                                 return;
 437
 438                         if (!setup_p4_watchdog())
 439                                 return;
 440                         break;
 441                 default:
 442                         return;
 443                 }
 444                 break;
 445         default:
 446                 return;
 447         }
 448         lapic_nmi_owner = LAPIC_NMI_WATCHDOG;
 449         nmi_active = 1;
 450 }
 451
 452 /*
 453  * the best way to detect whether a CPU has a 'hard lockup' problem
 454  * is to check it's local APIC timer IRQ counts. If they are not
 455  * changing then that CPU has some problem.
 456  *
 457  * as these watchdog NMI IRQs are generated on every CPU, we only
 458  * have to check the current processor.
 459  *
 460  * since NMIs don't listen to _any_ locks, we have to be extremely
 461  * careful not to rely on unsafe variables. The printk might lock
 462  * up though, so we have to break up any console locks first ...
 463  * [when there will be more tty-related locks, break them up
 464  *  here too!]
 465  */
 466
 467 static unsigned int
 468         last_irq_sums [NR_CPUS],
 469         alert_counter [NR_CPUS];
 470
 471 void touch_nmi_watchdog (void)
 472 {
 473         int i;
 474
 475         /*
 476          * Just reset the alert counters, (other CPUs might be
 477          * spinning on locks we hold):
 478          */
 479         for (i = 0; i < NR_CPUS; i++)
 480                 alert_counter[i] = 0;
 481
 482         /*
 483          * Tickle the softlockup detector too:
 484          */
 485         touch_softlockup_watchdog();
 486 }
 487
 488 extern void die_nmi(struct pt_regs *, const char *msg);
 489
 490 void nmi_watchdog_tick (struct pt_regs * regs)
 491 {
 492
 493         /*
 494          * Since current_thread_info()-> is always on the stack, and we
 495          * always switch the stack NMI-atomically, it's safe to use
 496          * smp_processor_id().
 497          */
 498         int sum, cpu = smp_processor_id();
 499
 500         sum = per_cpu(irq_stat, cpu).apic_timer_irqs;
 501
 502         if (last_irq_sums[cpu] == sum) {
 503                 /*
 504                  * Ayiee, looks like this CPU is stuck ...
 505                  * wait a few IRQs (5 seconds) before doing the oops ...
 506                  */
 507                 alert_counter[cpu]++;
 508                 if (alert_counter[cpu] == 5*nmi_hz)
 509                         /*
 510                          * die_nmi will return ONLY if NOTIFY_STOP happens..
 511                          */
 512                         die_nmi(regs, "NMI Watchdog detected LOCKUP");
 513
 514                 last_irq_sums[cpu] = sum;
 515                 alert_counter[cpu] = 0;
 516         }
 517         if (nmi_perfctr_msr) {
 518                 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
 519                         /*
 520                          * P4 quirks:
 521                          * - An overflown perfctr will assert its interrupt
 522                          *   until the OVF flag in its CCCR is cleared.
 523                          * - LVTPC is masked on interrupt and must be
 524                          *   unmasked by the LVTPC handler.
 525                          */
 526                         wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
 527                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 528                 }
 529                 else if (nmi_perfctr_msr == MSR_P6_PERFCTR0) {
 530                         /* Only P6 based Pentium M need to re-unmask
 531                          * the apic vector but it doesn't hurt
 532                          * other P6 variant */
 533                         apic_write(APIC_LVTPC, APIC_DM_NMI);
 534                 }
 535                 write_watchdog_counter(NULL);
 536         }
 537 }
 538
 539 #ifdef CONFIG_SYSCTL
 540
 541 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 542 {
 543         unsigned char reason = get_nmi_reason();
 544         char buf[64];
 545
 546         if (!(reason & 0xc0)) {
 547                 sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 548                 die_nmi(regs, buf);
 549         }
 550         return 0;
 551 }
 552
 553 /*
 554  * proc handler for /proc/sys/kernel/unknown_nmi_panic
 555  */
 556 int proc_unknown_nmi_panic(ctl_table *table, int write, struct file *file,
 557                         void __user *buffer, size_t *length, loff_t *ppos)
 558 {
 559         int old_state;
 560
 561         old_state = unknown_nmi_panic;
 562         proc_dointvec(table, write, file, buffer, length, ppos);
 563         if (!!old_state == !!unknown_nmi_panic)
 564                 return 0;
 565
 566         if (unknown_nmi_panic) {
 567                 if (reserve_lapic_nmi() < 0) {
 568                         unknown_nmi_panic = 0;
 569                         return -EBUSY;
 570                 } else {
 571                         set_nmi_callback(unknown_nmi_panic_callback);
 572                 }
 573         } else {
 574                 release_lapic_nmi();
 575                 unset_nmi_callback();
 576         }
 577         return 0;
 578 }
 579
 580 #endif
 581
 582 EXPORT_SYMBOL(nmi_active);
 583 EXPORT_SYMBOL(nmi_watchdog);
 584 EXPORT_SYMBOL(reserve_lapic_nmi);
 585 EXPORT_SYMBOL(release_lapic_nmi);
 586 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 587 EXPORT_SYMBOL(enable_timer_nmi_watchdog);