arch/ia64/kernel/irq_ia64.c

   1 /*
   2  * linux/arch/ia64/kernel/irq.c
   3  *
   4  * Copyright (C) 1998-2001 Hewlett-Packard Co
   5  *      Stephane Eranian <eranian@hpl.hp.com>
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *
   8  *  6/10/99: Updated to bring in sync with x86 version to facilitate
   9  *           support for SMP and different interrupt controllers.
  10  *
  11  * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
  12  *                      PCI to vector allocation routine.
  13  * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
  14  *                                              Added CPU Hotplug handling for IPF.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/module.h>
  19
  20 #include <linux/jiffies.h>
  21 #include <linux/errno.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/kernel_stat.h>
  26 #include <linux/slab.h>
  27 #include <linux/ptrace.h>
  28 #include <linux/random.h>       /* for rand_initialize_irq() */
  29 #include <linux/signal.h>
  30 #include <linux/smp.h>
  31 #include <linux/smp_lock.h>
  32 #include <linux/threads.h>
  33 #include <linux/bitops.h>
  34
  35 #include <asm/delay.h>
  36 #include <asm/intrinsics.h>
  37 #include <asm/io.h>
  38 #include <asm/hw_irq.h>
  39 #include <asm/machvec.h>
  40 #include <asm/pgtable.h>
  41 #include <asm/system.h>
  42
  43 #ifdef CONFIG_PERFMON
  44 # include <asm/perfmon.h>
  45 #endif
  46
  47 #define IRQ_DEBUG       0
  48
  49 /* default base addr of IPI table */
  50 void __iomem *ipi_base_addr = ((void __iomem *)
  51                                (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
  52
  53 /*
  54  * Legacy IRQ to IA-64 vector translation table.
  55  */
  56 __u8 isa_irq_to_vector_map[16] = {
  57         /* 8259 IRQ translation, first 16 entries */
  58         0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
  59         0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
  60 };
  61 EXPORT_SYMBOL(isa_irq_to_vector_map);
  62
  63 static unsigned long ia64_vector_mask[BITS_TO_LONGS(IA64_NUM_DEVICE_VECTORS)];
  64
  65 int
  66 assign_irq_vector (int irq)
  67 {
  68         int pos, vector;
  69  again:
  70         pos = find_first_zero_bit(ia64_vector_mask, IA64_NUM_DEVICE_VECTORS);
  71         vector = IA64_FIRST_DEVICE_VECTOR + pos;
  72         if (vector > IA64_LAST_DEVICE_VECTOR)
  73                 return -ENOSPC;
  74         if (test_and_set_bit(pos, ia64_vector_mask))
  75                 goto again;
  76         return vector;
  77 }
  78
  79 void
  80 free_irq_vector (int vector)
  81 {
  82         int pos;
  83
  84         if (vector < IA64_FIRST_DEVICE_VECTOR || vector > IA64_LAST_DEVICE_VECTOR)
  85                 return;
  86
  87         pos = vector - IA64_FIRST_DEVICE_VECTOR;
  88         if (!test_and_clear_bit(pos, ia64_vector_mask))
  89                 printk(KERN_WARNING "%s: double free!\n", __FUNCTION__);
  90 }
  91
  92 #ifdef CONFIG_SMP
  93 #       define IS_RESCHEDULE(vec)       (vec == IA64_IPI_RESCHEDULE)
  94 #else
  95 #       define IS_RESCHEDULE(vec)       (0)
  96 #endif
  97 /*
  98  * That's where the IVT branches when we get an external
  99  * interrupt. This branches to the correct hardware IRQ handler via
 100  * function ptr.
 101  */
 102 void
 103 ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
 104 {
 105         unsigned long saved_tpr;
 106
 107 #if IRQ_DEBUG
 108         {
 109                 unsigned long bsp, sp;
 110
 111                 /*
 112                  * Note: if the interrupt happened while executing in
 113                  * the context switch routine (ia64_switch_to), we may
 114                  * get a spurious stack overflow here.  This is
 115                  * because the register and the memory stack are not
 116                  * switched atomically.
 117                  */
 118                 bsp = ia64_getreg(_IA64_REG_AR_BSP);
 119                 sp = ia64_getreg(_IA64_REG_SP);
 120
 121                 if ((sp - bsp) < 1024) {
 122                         static unsigned char count;
 123                         static long last_time;
 124
 125                         if (jiffies - last_time > 5*HZ)
 126                                 count = 0;
 127                         if (++count < 5) {
 128                                 last_time = jiffies;
 129                                 printk("ia64_handle_irq: DANGER: less than "
 130                                        "1KB of free stack space!!\n"
 131                                        "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
 132                         }
 133                 }
 134         }
 135 #endif /* IRQ_DEBUG */
 136
 137         /*
 138          * Always set TPR to limit maximum interrupt nesting depth to
 139          * 16 (without this, it would be ~240, which could easily lead
 140          * to kernel stack overflows).
 141          */
 142         irq_enter();
 143         saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
 144         ia64_srlz_d();
 145         while (vector != IA64_SPURIOUS_INT_VECTOR) {
 146                 if (!IS_RESCHEDULE(vector)) {
 147                         ia64_setreg(_IA64_REG_CR_TPR, vector);
 148                         ia64_srlz_d();
 149
 150                         __do_IRQ(local_vector_to_irq(vector), regs);
 151
 152                         /*
 153                          * Disable interrupts and send EOI:
 154                          */
 155                         local_irq_disable();
 156                         ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
 157                 }
 158                 ia64_eoi();
 159                 vector = ia64_get_ivr();
 160         }
 161         /*
 162          * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
 163          * handler needs to be able to wait for further keyboard interrupts, which can't
 164          * come through until ia64_eoi() has been done.
 165          */
 166         irq_exit();
 167 }
 168
 169 #ifdef CONFIG_HOTPLUG_CPU
 170 /*
 171  * This function emulates a interrupt processing when a cpu is about to be
 172  * brought down.
 173  */
 174 void ia64_process_pending_intr(void)
 175 {
 176         ia64_vector vector;
 177         unsigned long saved_tpr;
 178         extern unsigned int vectors_in_migration[NR_IRQS];
 179
 180         vector = ia64_get_ivr();
 181
 182          irq_enter();
 183          saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
 184          ia64_srlz_d();
 185
 186          /*
 187           * Perform normal interrupt style processing
 188           */
 189         while (vector != IA64_SPURIOUS_INT_VECTOR) {
 190                 if (!IS_RESCHEDULE(vector)) {
 191                         ia64_setreg(_IA64_REG_CR_TPR, vector);
 192                         ia64_srlz_d();
 193
 194                         /*
 195                          * Now try calling normal ia64_handle_irq as it would have got called
 196                          * from a real intr handler. Try passing null for pt_regs, hopefully
 197                          * it will work. I hope it works!.
 198                          * Probably could shared code.
 199                          */
 200                         vectors_in_migration[local_vector_to_irq(vector)]=0;
 201                         __do_IRQ(local_vector_to_irq(vector), NULL);
 202
 203                         /*
 204                          * Disable interrupts and send EOI
 205                          */
 206                         local_irq_disable();
 207                         ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
 208                 }
 209                 ia64_eoi();
 210                 vector = ia64_get_ivr();
 211         }
 212         irq_exit();
 213 }
 214 #endif
 215
 216
 217 #ifdef CONFIG_SMP
 218 extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
 219
 220 static struct irqaction ipi_irqaction = {
 221         .handler =      handle_IPI,
 222         .flags =        SA_INTERRUPT,
 223         .name =         "IPI"
 224 };
 225 #endif
 226
 227 void
 228 register_percpu_irq (ia64_vector vec, struct irqaction *action)
 229 {
 230         irq_desc_t *desc;
 231         unsigned int irq;
 232
 233         for (irq = 0; irq < NR_IRQS; ++irq)
 234                 if (irq_to_vector(irq) == vec) {
 235                         desc = irq_descp(irq);
 236                         desc->status |= IRQ_PER_CPU;
 237                         desc->handler = &irq_type_ia64_lsapic;
 238                         if (action)
 239                                 setup_irq(irq, action);
 240                 }
 241 }
 242
 243 void __init
 244 init_IRQ (void)
 245 {
 246         register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
 247 #ifdef CONFIG_SMP
 248         register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
 249 #endif
 250 #ifdef CONFIG_PERFMON
 251         pfm_init_percpu();
 252 #endif
 253         platform_irq_init();
 254 }
 255
 256 void
 257 ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
 258 {
 259         void __iomem *ipi_addr;
 260         unsigned long ipi_data;
 261         unsigned long phys_cpu_id;
 262
 263 #ifdef CONFIG_SMP
 264         phys_cpu_id = cpu_physical_id(cpu);
 265 #else
 266         phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
 267 #endif
 268
 269         /*
 270          * cpu number is in 8bit ID and 8bit EID
 271          */
 272
 273         ipi_data = (delivery_mode << 8) | (vector & 0xff);
 274         ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
 275
 276         writeq(ipi_data, ipi_addr);
 277 }