arch/ppc/platforms/4xx/ebony.c

   1 /*
   2  * arch/ppc/platforms/4xx/ebony.c
   3  *
   4  * Ebony board specific routines
   5  *
   6  * Matt Porter <mporter@kernel.crashing.org>
   7  * Copyright 2002-2005 MontaVista Software Inc.
   8  *
   9  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  10  * Copyright (c) 2003-2005 Zultys Technologies
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/config.h>
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/types.h>
  27 #include <linux/major.h>
  28 #include <linux/blkdev.h>
  29 #include <linux/console.h>
  30 #include <linux/delay.h>
  31 #include <linux/ide.h>
  32 #include <linux/initrd.h>
  33 #include <linux/irq.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/root_dev.h>
  36 #include <linux/tty.h>
  37 #include <linux/serial.h>
  38 #include <linux/serial_core.h>
  39
  40 #include <asm/system.h>
  41 #include <asm/pgtable.h>
  42 #include <asm/page.h>
  43 #include <asm/dma.h>
  44 #include <asm/io.h>
  45 #include <asm/machdep.h>
  46 #include <asm/ocp.h>
  47 #include <asm/pci-bridge.h>
  48 #include <asm/time.h>
  49 #include <asm/todc.h>
  50 #include <asm/bootinfo.h>
  51 #include <asm/ppc4xx_pic.h>
  52 #include <asm/ppcboot.h>
  53 #include <asm/tlbflush.h>
  54
  55 #include <syslib/gen550.h>
  56 #include <syslib/ibm440gp_common.h>
  57
  58 bd_t __res;
  59
  60 static struct ibm44x_clocks clocks __initdata;
  61
  62 /*
  63  * Ebony external IRQ triggering/polarity settings
  64  */
  65 unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ0: PCI slot 0 */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ1: PCI slot 1 */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ2: PCI slot 2 */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ3: PCI slot 3 */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ4: IRDA */
  71         (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE),      /* IRQ5: SMI pushbutton */
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ6: PHYs */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ7: AUX */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ8: EXT */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ9: EXT */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ10: EXT */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* IRQ11: EXT */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* IRQ12: EXT */
  79 };
  80
  81 static void __init
  82 ebony_calibrate_decr(void)
  83 {
  84         unsigned int freq;
  85
  86         /*
  87          * Determine system clock speed
  88          *
  89          * If we are on Rev. B silicon, then use
  90          * default external system clock.  If we are
  91          * on Rev. C silicon then errata forces us to
  92          * use the internal clock.
  93          */
  94         if (strcmp(cur_cpu_spec[0]->cpu_name, "440GP Rev. B") == 0)
  95                 freq = EBONY_440GP_RB_SYSCLK;
  96         else
  97                 freq = EBONY_440GP_RC_SYSCLK;
  98
  99         ibm44x_calibrate_decr(freq);
 100 }
 101
 102 static int
 103 ebony_show_cpuinfo(struct seq_file *m)
 104 {
 105         seq_printf(m, "vendor\t\t: IBM\n");
 106         seq_printf(m, "machine\t\t: Ebony\n");
 107
 108         return 0;
 109 }
 110
 111 static inline int
 112 ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 113 {
 114         static char pci_irq_table[][4] =
 115         /*
 116          *      PCI IDSEL/INTPIN->INTLINE
 117          *         A   B   C   D
 118          */
 119         {
 120                 { 23, 23, 23, 23 },     /* IDSEL 1 - PCI Slot 0 */
 121                 { 24, 24, 24, 24 },     /* IDSEL 2 - PCI Slot 1 */
 122                 { 25, 25, 25, 25 },     /* IDSEL 3 - PCI Slot 2 */
 123                 { 26, 26, 26, 26 },     /* IDSEL 4 - PCI Slot 3 */
 124         };
 125
 126         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 127         return PCI_IRQ_TABLE_LOOKUP;
 128 }
 129
 130 #define PCIX_WRITEL(value, offset) \
 131         (writel(value, pcix_reg_base + offset))
 132
 133 /*
 134  * FIXME: This is only here to "make it work".  This will move
 135  * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
 136  * configuration library. -Matt
 137  */
 138 static void __init
 139 ebony_setup_pcix(void)
 140 {
 141         void __iomem *pcix_reg_base;
 142
 143         pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
 144
 145         /* Disable all windows */
 146         PCIX_WRITEL(0, PCIX0_POM0SA);
 147         PCIX_WRITEL(0, PCIX0_POM1SA);
 148         PCIX_WRITEL(0, PCIX0_POM2SA);
 149         PCIX_WRITEL(0, PCIX0_PIM0SA);
 150         PCIX_WRITEL(0, PCIX0_PIM1SA);
 151         PCIX_WRITEL(0, PCIX0_PIM2SA);
 152
 153         /* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
 154         PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
 155         PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
 156         PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 157         PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
 158         PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
 159
 160         /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 161         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 162         PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 163         PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
 164
 165         eieio();
 166 }
 167
 168 static void __init
 169 ebony_setup_hose(void)
 170 {
 171         struct pci_controller *hose;
 172
 173         /* Configure windows on the PCI-X host bridge */
 174         ebony_setup_pcix();
 175
 176         hose = pcibios_alloc_controller();
 177
 178         if (!hose)
 179                 return;
 180
 181         hose->first_busno = 0;
 182         hose->last_busno = 0xff;
 183
 184         hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
 185
 186         pci_init_resource(&hose->io_resource,
 187                         EBONY_PCI_LOWER_IO,
 188                         EBONY_PCI_UPPER_IO,
 189                         IORESOURCE_IO,
 190                         "PCI host bridge");
 191
 192         pci_init_resource(&hose->mem_resources[0],
 193                         EBONY_PCI_LOWER_MEM,
 194                         EBONY_PCI_UPPER_MEM,
 195                         IORESOURCE_MEM,
 196                         "PCI host bridge");
 197
 198         hose->io_space.start = EBONY_PCI_LOWER_IO;
 199         hose->io_space.end = EBONY_PCI_UPPER_IO;
 200         hose->mem_space.start = EBONY_PCI_LOWER_MEM;
 201         hose->mem_space.end = EBONY_PCI_UPPER_MEM;
 202         hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
 203         isa_io_base = (unsigned long)hose->io_base_virt;
 204
 205         setup_indirect_pci(hose,
 206                         EBONY_PCI_CFGA_PLB32,
 207                         EBONY_PCI_CFGD_PLB32);
 208         hose->set_cfg_type = 1;
 209
 210         hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 211
 212         ppc_md.pci_swizzle = common_swizzle;
 213         ppc_md.pci_map_irq = ebony_map_irq;
 214 }
 215
 216 TODC_ALLOC();
 217
 218 static void __init
 219 ebony_early_serial_map(void)
 220 {
 221         struct uart_port port;
 222
 223         /* Setup ioremapped serial port access */
 224         memset(&port, 0, sizeof(port));
 225         port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
 226         port.irq = 0;
 227         port.uartclk = clocks.uart0;
 228         port.regshift = 0;
 229         port.iotype = SERIAL_IO_MEM;
 230         port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
 231         port.line = 0;
 232
 233         if (early_serial_setup(&port) != 0) {
 234                 printk("Early serial init of port 0 failed\n");
 235         }
 236
 237 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 238         /* Configure debug serial access */
 239         gen550_init(0, &port);
 240
 241         /* Purge TLB entry added in head_44x.S for early serial access */
 242         _tlbie(UART0_IO_BASE);
 243 #endif
 244
 245         port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
 246         port.irq = 1;
 247         port.uartclk = clocks.uart1;
 248         port.line = 1;
 249
 250         if (early_serial_setup(&port) != 0) {
 251                 printk("Early serial init of port 1 failed\n");
 252         }
 253
 254 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 255         /* Configure debug serial access */
 256         gen550_init(1, &port);
 257 #endif
 258 }
 259
 260 static void __init
 261 ebony_setup_arch(void)
 262 {
 263         struct ocp_def *def;
 264         struct ocp_func_emac_data *emacdata;
 265
 266         /* Set mac_addr for each EMAC */
 267         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 268         emacdata = def->additions;
 269         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 270         emacdata->phy_mode = PHY_MODE_RMII;
 271         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 272
 273         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
 274         emacdata = def->additions;
 275         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 276         emacdata->phy_mode = PHY_MODE_RMII;
 277         memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
 278
 279         /*
 280          * Determine various clocks.
 281          * To be completely correct we should get SysClk
 282          * from FPGA, because it can be changed by on-board switches
 283          * --ebs
 284          */
 285         ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
 286         ocp_sys_info.opb_bus_freq = clocks.opb;
 287
 288         /* Setup TODC access */
 289         TODC_INIT(TODC_TYPE_DS1743,
 290                         0,
 291                         0,
 292                         ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
 293                         8);
 294
 295         /* init to some ~sane value until calibrate_delay() runs */
 296         loops_per_jiffy = 50000000/HZ;
 297
 298         /* Setup PCI host bridge */
 299         ebony_setup_hose();
 300
 301 #ifdef CONFIG_BLK_DEV_INITRD
 302         if (initrd_start)
 303                 ROOT_DEV = Root_RAM0;
 304         else
 305 #endif
 306 #ifdef CONFIG_ROOT_NFS
 307                 ROOT_DEV = Root_NFS;
 308 #else
 309                 ROOT_DEV = Root_HDA1;
 310 #endif
 311
 312         ebony_early_serial_map();
 313
 314         /* Identify the system */
 315         printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
 316 }
 317
 318 void __init platform_init(unsigned long r3, unsigned long r4,
 319                 unsigned long r5, unsigned long r6, unsigned long r7)
 320 {
 321         parse_bootinfo(find_bootinfo());
 322
 323         /*
 324          * If we were passed in a board information, copy it into the
 325          * residual data area.
 326          */
 327         if (r3)
 328                 __res = *(bd_t *)(r3 + KERNELBASE);
 329
 330         ibm44x_platform_init();
 331
 332         ppc_md.setup_arch = ebony_setup_arch;
 333         ppc_md.show_cpuinfo = ebony_show_cpuinfo;
 334         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 335
 336         ppc_md.calibrate_decr = ebony_calibrate_decr;
 337         ppc_md.time_init = todc_time_init;
 338         ppc_md.set_rtc_time = todc_set_rtc_time;
 339         ppc_md.get_rtc_time = todc_get_rtc_time;
 340
 341         ppc_md.nvram_read_val = todc_direct_read_val;
 342         ppc_md.nvram_write_val = todc_direct_write_val;
 343 #ifdef CONFIG_KGDB
 344         ppc_md.early_serial_map = ebony_early_serial_map;
 345 #endif
 346 }
 347