arch/ppc/platforms/4xx/luan.c

   1 /*
   2  * arch/ppc/platforms/4xx/luan.c
   3  *
   4  * Luan board specific routines
   5  *
   6  * Matt Porter <mporter@kernel.crashing.org>
   7  *
   8  * Copyright 2004-2005 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/types.h>
  25 #include <linux/major.h>
  26 #include <linux/blkdev.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/ide.h>
  30 #include <linux/initrd.h>
  31 #include <linux/irq.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/root_dev.h>
  34 #include <linux/tty.h>
  35 #include <linux/serial.h>
  36 #include <linux/serial_core.h>
  37
  38 #include <asm/system.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/page.h>
  41 #include <asm/dma.h>
  42 #include <asm/io.h>
  43 #include <asm/machdep.h>
  44 #include <asm/ocp.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/time.h>
  47 #include <asm/todc.h>
  48 #include <asm/bootinfo.h>
  49 #include <asm/ppc4xx_pic.h>
  50 #include <asm/ppcboot.h>
  51
  52 #include <syslib/ibm44x_common.h>
  53 #include <syslib/ibm440gx_common.h>
  54 #include <syslib/ibm440sp_common.h>
  55
  56 bd_t __res;
  57
  58 static struct ibm44x_clocks clocks __initdata;
  59
  60 static void __init
  61 luan_calibrate_decr(void)
  62 {
  63         unsigned int freq;
  64
  65         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  66                 freq = LUAN_TMR_CLK;
  67         else
  68                 freq = clocks.cpu;
  69
  70         ibm44x_calibrate_decr(freq);
  71 }
  72
  73 static int
  74 luan_show_cpuinfo(struct seq_file *m)
  75 {
  76         seq_printf(m, "vendor\t\t: IBM\n");
  77         seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
  78
  79         return 0;
  80 }
  81
  82 static inline int
  83 luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  84 {
  85         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  86
  87         /* PCIX0 in adapter mode, no host interrupt routing */
  88
  89         /* PCIX1 */
  90         if (hose->index == 0) {
  91                 static char pci_irq_table[][4] =
  92                 /*
  93                  *      PCI IDSEL/INTPIN->INTLINE
  94                  *        A   B   C   D
  95                  */
  96                 {
  97                         { 49, 49, 49, 49 },     /* IDSEL 1 - PCIX1 Slot 0 */
  98                         { 49, 49, 49, 49 },     /* IDSEL 2 - PCIX1 Slot 1 */
  99                         { 49, 49, 49, 49 },     /* IDSEL 3 - PCIX1 Slot 2 */
 100                         { 49, 49, 49, 49 },     /* IDSEL 4 - PCIX1 Slot 3 */
 101                 };
 102                 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 103                 return PCI_IRQ_TABLE_LOOKUP;
 104         /* PCIX2 */
 105         } else if (hose->index == 1) {
 106                 static char pci_irq_table[][4] =
 107                 /*
 108                  *      PCI IDSEL/INTPIN->INTLINE
 109                  *        A   B   C   D
 110                  */
 111                 {
 112                         { 50, 50, 50, 50 },     /* IDSEL 1 - PCIX2 Slot 0 */
 113                         { 50, 50, 50, 50 },     /* IDSEL 2 - PCIX2 Slot 1 */
 114                         { 50, 50, 50, 50 },     /* IDSEL 3 - PCIX2 Slot 2 */
 115                         { 50, 50, 50, 50 },     /* IDSEL 4 - PCIX2 Slot 3 */
 116                 };
 117                 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 118                 return PCI_IRQ_TABLE_LOOKUP;
 119         }
 120         return -1;
 121 }
 122
 123 static void __init luan_set_emacdata(void)
 124 {
 125         struct ocp_def *def;
 126         struct ocp_func_emac_data *emacdata;
 127
 128         /* Set phy_map, phy_mode, and mac_addr for the EMAC */
 129         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 130         emacdata = def->additions;
 131         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 132         emacdata->phy_mode = PHY_MODE_GMII;
 133         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 134 }
 135
 136 #define PCIX_READW(offset) \
 137         (readw((void *)((u32)pcix_reg_base+offset)))
 138
 139 #define PCIX_WRITEW(value, offset) \
 140         (writew(value, (void *)((u32)pcix_reg_base+offset)))
 141
 142 #define PCIX_WRITEL(value, offset) \
 143         (writel(value, (void *)((u32)pcix_reg_base+offset)))
 144
 145 static void __init
 146 luan_setup_pcix(void)
 147 {
 148         int i;
 149         void *pcix_reg_base;
 150
 151         for (i=0;i<3;i++) {
 152                 pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
 153
 154                 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 155                 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 156
 157                 /* Disable all windows */
 158                 PCIX_WRITEL(0, PCIX0_POM0SA);
 159                 PCIX_WRITEL(0, PCIX0_POM1SA);
 160                 PCIX_WRITEL(0, PCIX0_POM2SA);
 161                 PCIX_WRITEL(0, PCIX0_PIM0SA);
 162                 PCIX_WRITEL(0, PCIX0_PIM0SAH);
 163                 PCIX_WRITEL(0, PCIX0_PIM1SA);
 164                 PCIX_WRITEL(0, PCIX0_PIM2SA);
 165                 PCIX_WRITEL(0, PCIX0_PIM2SAH);
 166
 167                 /*
 168                  * Setup 512MB PLB->PCI outbound mem window
 169                  * (a_n000_0000->0_n000_0000)
 170                  * */
 171                 PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
 172                 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
 173                 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 174                 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
 175                 PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
 176
 177                 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 178                 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 179                 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 180                 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
 181                 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
 182
 183                 iounmap(pcix_reg_base);
 184         }
 185
 186         eieio();
 187 }
 188
 189 static void __init
 190 luan_setup_hose(struct pci_controller *hose,
 191                 int lower_mem,
 192                 int upper_mem,
 193                 int cfga,
 194                 int cfgd,
 195                 u64 pcix_io_base)
 196 {
 197         char name[20];
 198
 199         sprintf(name, "PCIX%d host bridge", hose->index);
 200
 201         hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
 202
 203         pci_init_resource(&hose->io_resource,
 204                         LUAN_PCIX_LOWER_IO,
 205                         LUAN_PCIX_UPPER_IO,
 206                         IORESOURCE_IO,
 207                         name);
 208
 209         pci_init_resource(&hose->mem_resources[0],
 210                         lower_mem,
 211                         upper_mem,
 212                         IORESOURCE_MEM,
 213                         name);
 214
 215         hose->io_space.start = LUAN_PCIX_LOWER_IO;
 216         hose->io_space.end = LUAN_PCIX_UPPER_IO;
 217         hose->mem_space.start = lower_mem;
 218         hose->mem_space.end = upper_mem;
 219         hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
 220         isa_io_base = (unsigned long) hose->io_base_virt;
 221
 222         setup_indirect_pci(hose, cfga, cfgd);
 223         hose->set_cfg_type = 1;
 224 }
 225
 226 static void __init
 227 luan_setup_hoses(void)
 228 {
 229         struct pci_controller *hose1, *hose2;
 230
 231         /* Configure windows on the PCI-X host bridge */
 232         luan_setup_pcix();
 233
 234         /* Allocate hoses for PCIX1 and PCIX2 */
 235         hose1 = pcibios_alloc_controller();
 236         hose2 = pcibios_alloc_controller();
 237         if (!hose1 || !hose2)
 238                 return;
 239
 240         /* Setup PCIX1 */
 241         hose1->first_busno = 0;
 242         hose1->last_busno = 0xff;
 243
 244         luan_setup_hose(hose1,
 245                         LUAN_PCIX1_LOWER_MEM,
 246                         LUAN_PCIX1_UPPER_MEM,
 247                         PCIX1_CFGA,
 248                         PCIX1_CFGD,
 249                         PCIX1_IO_BASE);
 250
 251         hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
 252
 253         /* Setup PCIX2 */
 254         hose2->first_busno = hose1->last_busno + 1;
 255         hose2->last_busno = 0xff;
 256
 257         luan_setup_hose(hose2,
 258                         LUAN_PCIX2_LOWER_MEM,
 259                         LUAN_PCIX2_UPPER_MEM,
 260                         PCIX2_CFGA,
 261                         PCIX2_CFGD,
 262                         PCIX2_IO_BASE);
 263
 264         hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
 265
 266         ppc_md.pci_swizzle = common_swizzle;
 267         ppc_md.pci_map_irq = luan_map_irq;
 268 }
 269
 270 TODC_ALLOC();
 271
 272 static void __init
 273 luan_early_serial_map(void)
 274 {
 275         struct uart_port port;
 276
 277         /* Setup ioremapped serial port access */
 278         memset(&port, 0, sizeof(port));
 279         port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
 280         port.irq = UART0_INT;
 281         port.uartclk = clocks.uart0;
 282         port.regshift = 0;
 283         port.iotype = SERIAL_IO_MEM;
 284         port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
 285         port.line = 0;
 286
 287         if (early_serial_setup(&port) != 0) {
 288                 printk("Early serial init of port 0 failed\n");
 289         }
 290
 291         port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
 292         port.irq = UART1_INT;
 293         port.uartclk = clocks.uart1;
 294         port.line = 1;
 295
 296         if (early_serial_setup(&port) != 0) {
 297                 printk("Early serial init of port 1 failed\n");
 298         }
 299
 300         port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
 301         port.irq = UART2_INT;
 302         port.uartclk = BASE_BAUD;
 303         port.line = 2;
 304
 305         if (early_serial_setup(&port) != 0) {
 306                 printk("Early serial init of port 2 failed\n");
 307         }
 308 }
 309
 310 static void __init
 311 luan_setup_arch(void)
 312 {
 313         luan_set_emacdata();
 314
 315 #if !defined(CONFIG_BDI_SWITCH)
 316         /*
 317          * The Abatron BDI JTAG debugger does not tolerate others
 318          * mucking with the debug registers.
 319          */
 320         mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
 321 #endif
 322
 323         /*
 324          * Determine various clocks.
 325          * To be completely correct we should get SysClk
 326          * from FPGA, because it can be changed by on-board switches
 327          * --ebs
 328          */
 329         /* 440GX and 440SP clocking is the same -mdp */
 330         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 331         ocp_sys_info.opb_bus_freq = clocks.opb;
 332
 333         /* init to some ~sane value until calibrate_delay() runs */
 334         loops_per_jiffy = 50000000/HZ;
 335
 336         /* Setup PCIXn host bridges */
 337         luan_setup_hoses();
 338
 339 #ifdef CONFIG_BLK_DEV_INITRD
 340         if (initrd_start)
 341                 ROOT_DEV = Root_RAM0;
 342         else
 343 #endif
 344 #ifdef CONFIG_ROOT_NFS
 345                 ROOT_DEV = Root_NFS;
 346 #else
 347                 ROOT_DEV = Root_HDA1;
 348 #endif
 349
 350         luan_early_serial_map();
 351
 352         /* Identify the system */
 353         printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
 354 }
 355
 356 void __init platform_init(unsigned long r3, unsigned long r4,
 357                 unsigned long r5, unsigned long r6, unsigned long r7)
 358 {
 359         parse_bootinfo(find_bootinfo());
 360
 361         /*
 362          * If we were passed in a board information, copy it into the
 363          * residual data area.
 364          */
 365         if (r3)
 366                 __res = *(bd_t *)(r3 + KERNELBASE);
 367
 368         ibm44x_platform_init();
 369
 370         ppc_md.setup_arch = luan_setup_arch;
 371         ppc_md.show_cpuinfo = luan_show_cpuinfo;
 372         ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
 373         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 374
 375         ppc_md.calibrate_decr = luan_calibrate_decr;
 376 #ifdef CONFIG_KGDB
 377         ppc_md.early_serial_map = luan_early_serial_map;
 378 #endif
 379 }