mips: rename offsets.c to asm-offsets.c
[linux-2.6/verdex.git] / arch / ppc / platforms / 4xx / ocotea.h
blob33251153ac5fff23187de3ecc48d6ec7e5c1f844
1 /*
2 * arch/ppc/platforms/ocotea.h
4 * Ocotea board definitions
6 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2003-2005 MontaVista Software Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 #ifdef __KERNEL__
18 #ifndef __ASM_OCOTEA_H__
19 #define __ASM_OCOTEA_H__
21 #include <linux/config.h>
22 #include <platforms/4xx/ibm440gx.h>
24 /* F/W TLB mapping used in bootloader glue to reset EMAC */
25 #define PPC44x_EMAC0_MR0 0xe0000800
27 /* Location of MAC addresses in PIBS image */
28 #define PIBS_FLASH_BASE 0xfff00000
29 #define PIBS_MAC_BASE (PIBS_FLASH_BASE+0xb0500)
30 #define PIBS_MAC_SIZE 0x200
31 #define PIBS_MAC_OFFSET 0x100
33 /* External timer clock frequency */
34 #define OCOTEA_TMR_CLK 25000000
36 /* RTC/NVRAM location */
37 #define OCOTEA_RTC_ADDR 0x0000000148000000ULL
38 #define OCOTEA_RTC_SIZE 0x2000
40 /* Flash */
41 #define OCOTEA_FPGA_REG_0 0x0000000148300000ULL
42 #define OCOTEA_BOOT_LARGE_FLASH(x) (x & 0x40)
43 #define OCOTEA_SMALL_FLASH_LOW 0x00000001ff900000ULL
44 #define OCOTEA_SMALL_FLASH_HIGH 0x00000001fff00000ULL
45 #define OCOTEA_SMALL_FLASH_SIZE 0x100000
46 #define OCOTEA_LARGE_FLASH_LOW 0x00000001ff800000ULL
47 #define OCOTEA_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
48 #define OCOTEA_LARGE_FLASH_SIZE 0x400000
50 /* FPGA_REG_3 (Ethernet Groups) */
51 #define OCOTEA_FPGA_REG_3 0x0000000148300003ULL
54 * Serial port defines
56 #define RS_TABLE_SIZE 2
58 #if defined(__BOOTER__)
59 /* OpenBIOS defined UART mappings, used by bootloader shim */
60 #define UART0_IO_BASE 0xE0000200
61 #define UART1_IO_BASE 0xE0000300
62 #else
63 /* head_44x.S created UART mapping, used before early_serial_setup.
64 * We cannot use default OpenBIOS UART mappings because they
65 * don't work for configurations with more than 512M RAM. --ebs
67 #define UART0_IO_BASE 0xF0000200
68 #define UART1_IO_BASE 0xF0000300
69 #endif
71 #define BASE_BAUD 11059200/16
72 #define STD_UART_OP(num) \
73 { 0, BASE_BAUD, 0, UART##num##_INT, \
74 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
75 iomem_base: (void*)UART##num##_IO_BASE, \
76 io_type: SERIAL_IO_MEM},
78 #define SERIAL_PORT_DFNS \
79 STD_UART_OP(0) \
80 STD_UART_OP(1)
82 /* PCI support */
83 #define OCOTEA_PCI_LOWER_IO 0x00000000
84 #define OCOTEA_PCI_UPPER_IO 0x0000ffff
85 #define OCOTEA_PCI_LOWER_MEM 0x80000000
86 #define OCOTEA_PCI_UPPER_MEM 0xffffefff
88 #define OCOTEA_PCI_CFGREGS_BASE 0x000000020ec00000ULL
89 #define OCOTEA_PCI_CFGA_PLB32 0x0ec00000
90 #define OCOTEA_PCI_CFGD_PLB32 0x0ec00004
92 #define OCOTEA_PCI_IO_BASE 0x0000000208000000ULL
93 #define OCOTEA_PCI_IO_SIZE 0x00010000
94 #define OCOTEA_PCI_MEM_OFFSET 0x00000000
96 #endif /* __ASM_OCOTEA_H__ */
97 #endif /* __KERNEL__ */