arch/ppc/platforms/85xx/stx_gp3.c

   1 /*
   2  * arch/ppc/platforms/85xx/stx_gp3.c
   3  *
   4  * STx GP3 board specific routines
   5  *
   6  * Dan Malek <dan@embeddededge.com>
   7  * Copyright 2004 Embedded Edge, LLC
   8  *
   9  * Copied from mpc8560_ads.c
  10  * Copyright 2002, 2003 Motorola Inc.
  11  *
  12  * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
  13  * Copyright 2004-2005 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  */
  20
  21 #include <linux/config.h>
  22 #include <linux/stddef.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/errno.h>
  26 #include <linux/reboot.h>
  27 #include <linux/pci.h>
  28 #include <linux/kdev_t.h>
  29 #include <linux/major.h>
  30 #include <linux/blkdev.h>
  31 #include <linux/console.h>
  32 #include <linux/delay.h>
  33 #include <linux/irq.h>
  34 #include <linux/root_dev.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/serial.h>
  37 #include <linux/initrd.h>
  38 #include <linux/module.h>
  39 #include <linux/fsl_devices.h>
  40 #include <linux/interrupt.h>
  41
  42 #include <asm/system.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/page.h>
  45 #include <asm/atomic.h>
  46 #include <asm/time.h>
  47 #include <asm/io.h>
  48 #include <asm/machdep.h>
  49 #include <asm/open_pic.h>
  50 #include <asm/bootinfo.h>
  51 #include <asm/pci-bridge.h>
  52 #include <asm/mpc85xx.h>
  53 #include <asm/irq.h>
  54 #include <asm/immap_85xx.h>
  55 #include <asm/cpm2.h>
  56 #include <asm/mpc85xx.h>
  57 #include <asm/ppc_sys.h>
  58
  59 #include <syslib/cpm2_pic.h>
  60 #include <syslib/ppc85xx_common.h>
  61
  62
  63 unsigned char __res[sizeof(bd_t)];
  64
  65 #ifndef CONFIG_PCI
  66 unsigned long isa_io_base = 0;
  67 unsigned long isa_mem_base = 0;
  68 unsigned long pci_dram_offset = 0;
  69 #endif
  70
  71 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  72 static u8 gp3_openpic_initsenses[] __initdata = {
  73         MPC85XX_INTERNAL_IRQ_SENSES,
  74         0x0,                                            /* External  0: */
  75 #if defined(CONFIG_PCI)
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI slot 1 */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI slot 2 */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 4: PCI slot 3 */
  80 #else
  81         0x0,                            /* External  1: */
  82         0x0,                            /* External  2: */
  83         0x0,                            /* External  3: */
  84         0x0,                            /* External  4: */
  85 #endif
  86         0x0,                            /* External  5: */
  87         0x0,                            /* External  6: */
  88         0x0,                            /* External  7: */
  89         0x0,                            /* External  8: */
  90         0x0,                            /* External  9: */
  91         0x0,                            /* External 10: */
  92         0x0,                            /* External 11: */
  93 };
  94
  95 /*
  96  * Setup the architecture
  97  */
  98 static void __init
  99 gp3_setup_arch(void)
 100 {
 101         bd_t *binfo = (bd_t *) __res;
 102         unsigned int freq;
 103         struct gianfar_platform_data *pdata;
 104
 105         cpm2_reset();
 106
 107         /* get the core frequency */
 108         freq = binfo->bi_intfreq;
 109
 110         if (ppc_md.progress)
 111                 ppc_md.progress("gp3_setup_arch()", 0);
 112
 113         /* Set loops_per_jiffy to a half-way reasonable value,
 114            for use until calibrate_delay gets called. */
 115         loops_per_jiffy = freq / HZ;
 116
 117 #ifdef CONFIG_PCI
 118         /* setup PCI host bridges */
 119         mpc85xx_setup_hose();
 120 #endif
 121
 122         /* setup the board related information for the enet controllers */
 123         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
 124         if (pdata) {
 125         /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
 126                 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
 127                 pdata->phyid = 2;
 128                 pdata->phy_reg_addr += binfo->bi_immr_base;
 129                 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 130         }
 131
 132         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
 133         if (pdata) {
 134         /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
 135                 pdata->interruptPHY = MPC85xx_IRQ_EXT5;
 136                 pdata->phyid = 4;
 137                 /* fixup phy address */
 138                 pdata->phy_reg_addr += binfo->bi_immr_base;
 139                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 140         }
 141
 142 #ifdef CONFIG_BLK_DEV_INITRD
 143         if (initrd_start)
 144                 ROOT_DEV = Root_RAM0;
 145         else
 146 #endif
 147 #ifdef  CONFIG_ROOT_NFS
 148                 ROOT_DEV = Root_NFS;
 149 #else
 150                 ROOT_DEV = Root_HDA1;
 151 #endif
 152
 153         printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
 154 }
 155
 156 static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
 157 {
 158         while ((irq = cpm2_get_irq(regs)) >= 0)
 159                 __do_IRQ(irq, regs);
 160
 161         return IRQ_HANDLED;
 162 }
 163
 164 static struct irqaction cpm2_irqaction = {
 165         .handler        = cpm2_cascade,
 166         .flags          = SA_INTERRUPT,
 167         .mask           = CPU_MASK_NONE,
 168         .name           = "cpm2_cascade",
 169 };
 170
 171 static void __init
 172 gp3_init_IRQ(void)
 173 {
 174         bd_t *binfo = (bd_t *) __res;
 175
 176         /*
 177          * Setup OpenPIC
 178          */
 179
 180         /* Determine the Physical Address of the OpenPIC regs */
 181         phys_addr_t OpenPIC_PAddr =
 182             binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 183         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 184         OpenPIC_InitSenses = gp3_openpic_initsenses;
 185         OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
 186
 187         /* Skip reserved space and internal sources */
 188         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 189
 190         /* Map PIC IRQs 0-11 */
 191         openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
 192
 193         /*
 194          * Let openpic interrupts starting from an offset, to
 195          * leave space for cascading interrupts underneath.
 196          */
 197         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 198
 199         /* Setup CPM2 PIC */
 200         cpm2_init_IRQ();
 201
 202         setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
 203
 204         return;
 205 }
 206
 207 static int
 208 gp3_show_cpuinfo(struct seq_file *m)
 209 {
 210         uint pvid, svid, phid1;
 211         bd_t *binfo = (bd_t *) __res;
 212         uint    memsize;
 213         unsigned int freq;
 214         extern unsigned long total_memory;      /* in mm/init */
 215
 216         /* get the core frequency */
 217         freq = binfo->bi_intfreq;
 218
 219         pvid = mfspr(SPRN_PVR);
 220         svid = mfspr(SPRN_SVR);
 221
 222         memsize = total_memory;
 223
 224         seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
 225         seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
 226         seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
 227                    freq % 1000000);
 228         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 229         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 230
 231         /* Display cpu Pll setting */
 232         phid1 = mfspr(SPRN_HID1);
 233         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 234
 235         /* Display the amount of memory */
 236         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 237
 238         return 0;
 239 }
 240
 241 #ifdef CONFIG_PCI
 242 int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
 243                     unsigned char pin)
 244 {
 245         static char pci_irq_table[][4] =
 246             /*
 247              *      PCI IDSEL/INTPIN->INTLINE
 248              *        A      B      C      D
 249              */
 250         {
 251                 {PIRQA, PIRQB, PIRQC, PIRQD},
 252                 {PIRQD, PIRQA, PIRQB, PIRQC},
 253                 {PIRQC, PIRQD, PIRQA, PIRQB},
 254                 {PIRQB, PIRQC, PIRQD, PIRQA},
 255         };
 256
 257         const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
 258         return PCI_IRQ_TABLE_LOOKUP;
 259 }
 260
 261 int mpc85xx_exclude_device(u_char bus, u_char devfn)
 262 {
 263         if (bus == 0 && PCI_SLOT(devfn) == 0)
 264                 return PCIBIOS_DEVICE_NOT_FOUND;
 265         else
 266                 return PCIBIOS_SUCCESSFUL;
 267 }
 268 #endif /* CONFIG_PCI */
 269
 270 void __init
 271 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 272               unsigned long r6, unsigned long r7)
 273 {
 274         /* parse_bootinfo must always be called first */
 275         parse_bootinfo(find_bootinfo());
 276
 277         /*
 278          * If we were passed in a board information, copy it into the
 279          * residual data area.
 280          */
 281         if (r3) {
 282                 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 283                        sizeof (bd_t));
 284
 285         }
 286 #if defined(CONFIG_BLK_DEV_INITRD)
 287         /*
 288          * If the init RAM disk has been configured in, and there's a valid
 289          * starting address for it, set it up.
 290          */
 291         if (r4) {
 292                 initrd_start = r4 + KERNELBASE;
 293                 initrd_end = r5 + KERNELBASE;
 294         }
 295 #endif                          /* CONFIG_BLK_DEV_INITRD */
 296
 297         /* Copy the kernel command line arguments to a safe place. */
 298
 299         if (r6) {
 300                 *(char *) (r7 + KERNELBASE) = 0;
 301                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 302         }
 303
 304         identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 305
 306         /* setup the PowerPC module struct */
 307         ppc_md.setup_arch = gp3_setup_arch;
 308         ppc_md.show_cpuinfo = gp3_show_cpuinfo;
 309
 310         ppc_md.init_IRQ = gp3_init_IRQ;
 311         ppc_md.get_irq = openpic_get_irq;
 312
 313         ppc_md.restart = mpc85xx_restart;
 314         ppc_md.power_off = mpc85xx_power_off;
 315         ppc_md.halt = mpc85xx_halt;
 316
 317         ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
 318
 319         ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
 320
 321         if (ppc_md.progress)
 322                 ppc_md.progress("platform_init(): exit", 0);
 323
 324         return;
 325 }