arch/ppc/platforms/ev64360.c

   1 /*
   2  * arch/ppc/platforms/ev64360.c
   3  *
   4  * Board setup routines for the Marvell EV-64360-BP Evaluation Board.
   5  *
   6  * Author: Lee Nicks <allinux@gmail.com>
   7  *
   8  * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
   9  * Based on code done by - Mark A. Greer <mgreer@mvista.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License as published by the
  13  * Free Software Foundation; either version 2 of the License, or (at your
  14  * option) any later version.
  15  */
  16 #include <linux/config.h>
  17 #include <linux/kernel.h>
  18 #include <linux/pci.h>
  19 #include <linux/kdev_t.h>
  20 #include <linux/console.h>
  21 #include <linux/initrd.h>
  22 #include <linux/root_dev.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/bootmem.h>
  26 #include <linux/mtd/physmap.h>
  27 #include <linux/mv643xx.h>
  28 #ifdef CONFIG_BOOTIMG
  29 #include <linux/bootimg.h>
  30 #endif
  31 #include <asm/page.h>
  32 #include <asm/time.h>
  33 #include <asm/smp.h>
  34 #include <asm/todc.h>
  35 #include <asm/bootinfo.h>
  36 #include <asm/ppcboot.h>
  37 #include <asm/mv64x60.h>
  38 #include <platforms/ev64360.h>
  39
  40 #define BOARD_VENDOR    "Marvell"
  41 #define BOARD_MACHINE   "EV-64360-BP"
  42
  43 static struct           mv64x60_handle bh;
  44 static void __iomem     *sram_base;
  45
  46 static u32              ev64360_flash_size_0;
  47 static u32              ev64360_flash_size_1;
  48
  49 static u32              ev64360_bus_frequency;
  50
  51 unsigned char   __res[sizeof(bd_t)];
  52
  53 static int __init
  54 ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  55 {
  56         return 0;
  57 }
  58
  59 static void __init
  60 ev64360_setup_bridge(void)
  61 {
  62         struct mv64x60_setup_info si;
  63         int i;
  64
  65         memset(&si, 0, sizeof(si));
  66
  67         si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
  68
  69         #ifdef CONFIG_PCI
  70         si.pci_1.enable_bus = 1;
  71         si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
  72         si.pci_1.pci_io.pci_base_hi = 0;
  73         si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
  74         si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
  75         si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
  76         si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
  77         si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
  78         si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
  79         si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
  80         si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
  81         si.pci_1.pci_cmd_bits = 0;
  82         si.pci_1.latency_timer = 0x80;
  83         #else
  84         si.pci_0.enable_bus = 0;
  85         si.pci_1.enable_bus = 0;
  86         #endif
  87
  88         for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
  89 #if defined(CONFIG_NOT_COHERENT_CACHE)
  90                 si.cpu_prot_options[i] = 0;
  91                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
  92                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
  93                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
  94
  95                 si.pci_1.acc_cntl_options[i] =
  96                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
  97                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
  98                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
  99                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 100 #else
 101                 si.cpu_prot_options[i] = 0;
 102                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
 103                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
 104                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
 105
 106                 si.pci_1.acc_cntl_options[i] =
 107                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 108                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 109                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 110                     MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 111 #endif
 112         }
 113
 114         if (mv64x60_init(&bh, &si))
 115                 printk(KERN_WARNING "Bridge initialization failed.\n");
 116
 117         #ifdef CONFIG_PCI
 118         pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
 119         ppc_md.pci_swizzle = common_swizzle;
 120         ppc_md.pci_map_irq = ev64360_map_irq;
 121         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 122
 123         mv64x60_set_bus(&bh, 1, 0);
 124         bh.hose_b->first_busno = 0;
 125         bh.hose_b->last_busno = 0xff;
 126         #endif
 127 }
 128
 129 /* Bridge & platform setup routines */
 130 void __init
 131 ev64360_intr_setup(void)
 132 {
 133         /* MPP 8, 9, and 10 */
 134         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
 135
 136         /*
 137          * Define GPP 8,9,and 10 interrupt polarity as active low
 138          * input signal and level triggered
 139          */
 140         mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
 141         mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
 142
 143         /* Config GPP intr ctlr to respond to level trigger */
 144         mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
 145
 146         /* Erranum FEr PCI-#8 */
 147         mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
 148         mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
 149
 150         /*
 151          * Dismiss and then enable interrupt on GPP interrupt cause
 152          * for CPU #0
 153          */
 154         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
 155         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
 156
 157         /*
 158          * Dismiss and then enable interrupt on CPU #0 high cause reg
 159          * BIT25 summarizes GPP interrupts 8-15
 160          */
 161         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
 162 }
 163
 164 void __init
 165 ev64360_setup_peripherals(void)
 166 {
 167         u32 base;
 168
 169         /* Set up window for boot CS */
 170         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 171                  EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
 172         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 173
 174         /* We only use the 32-bit flash */
 175         mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
 176                 &ev64360_flash_size_0);
 177         ev64360_flash_size_1 = 0;
 178
 179         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 180                  EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
 181         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 182
 183         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 184                  EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 185         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 186         sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
 187
 188         /* Set up Enet->SRAM window */
 189         mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
 190                 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
 191         bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
 192
 193         /* Give enet r/w access to memory region */
 194         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
 195         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
 196         mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
 197
 198         mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
 199         mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
 200                          ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
 201
 202 #if defined(CONFIG_NOT_COHERENT_CACHE)
 203         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
 204 #else
 205         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 206 #endif
 207
 208         /*
 209          * Setting the SRAM to 0. Note that this generates parity errors on
 210          * internal data path in SRAM since it's first time accessing it
 211          * while after reset it's not configured.
 212          */
 213         memset(sram_base, 0, MV64360_SRAM_SIZE);
 214
 215         /* set up PCI interrupt controller */
 216         ev64360_intr_setup();
 217 }
 218
 219 static void __init
 220 ev64360_setup_arch(void)
 221 {
 222         if (ppc_md.progress)
 223                 ppc_md.progress("ev64360_setup_arch: enter", 0);
 224
 225         set_tb(0, 0);
 226
 227 #ifdef CONFIG_BLK_DEV_INITRD
 228         if (initrd_start)
 229                 ROOT_DEV = Root_RAM0;
 230         else
 231 #endif
 232 #ifdef   CONFIG_ROOT_NFS
 233                 ROOT_DEV = Root_NFS;
 234 #else
 235                 ROOT_DEV = Root_SDA2;
 236 #endif
 237
 238         /*
 239          * Set up the L2CR register.
 240          */
 241         _set_L2CR(L2CR_L2E | L2CR_L2PE);
 242
 243         if (ppc_md.progress)
 244                 ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);
 245
 246         ev64360_setup_bridge();
 247         ev64360_setup_peripherals();
 248         ev64360_bus_frequency = ev64360_bus_freq();
 249
 250         printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
 251                 "(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
 252         if (ppc_md.progress)
 253                 ppc_md.progress("ev64360_setup_arch: exit", 0);
 254 }
 255
 256 /* Platform device data fixup routines. */
 257 #if defined(CONFIG_SERIAL_MPSC)
 258 static void __init
 259 ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
 260 {
 261         struct mpsc_pdata *pdata;
 262
 263         pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
 264
 265         pdata->max_idle = 40;
 266         pdata->default_baud = EV64360_DEFAULT_BAUD;
 267         pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
 268         /*
 269          * TCLK (not SysCLk) is routed to BRG, then to the MPSC.  On most parts,
 270          * TCLK == SysCLK but on 64460, they are separate pins.
 271          * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
 272          */
 273         pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
 274 }
 275 #endif
 276
 277 #if defined(CONFIG_MV643XX_ETH)
 278 static void __init
 279 ev64360_fixup_eth_pdata(struct platform_device *pdev)
 280 {
 281         struct mv643xx_eth_platform_data *eth_pd;
 282         static u16 phy_addr[] = {
 283                 EV64360_ETH0_PHY_ADDR,
 284                 EV64360_ETH1_PHY_ADDR,
 285                 EV64360_ETH2_PHY_ADDR,
 286         };
 287
 288         eth_pd = pdev->dev.platform_data;
 289         eth_pd->force_phy_addr = 1;
 290         eth_pd->phy_addr = phy_addr[pdev->id];
 291         eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
 292         eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
 293 }
 294 #endif
 295
 296 static int __init
 297 ev64360_platform_notify(struct device *dev)
 298 {
 299         static struct {
 300                 char    *bus_id;
 301                 void    ((*rtn)(struct platform_device *pdev));
 302         } dev_map[] = {
 303 #if defined(CONFIG_SERIAL_MPSC)
 304                 { MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
 305                 { MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
 306 #endif
 307 #if defined(CONFIG_MV643XX_ETH)
 308                 { MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
 309                 { MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
 310                 { MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
 311 #endif
 312         };
 313         struct platform_device  *pdev;
 314         int     i;
 315
 316         if (dev && dev->bus_id)
 317                 for (i=0; i<ARRAY_SIZE(dev_map); i++)
 318                         if (!strncmp(dev->bus_id, dev_map[i].bus_id,
 319                                 BUS_ID_SIZE)) {
 320
 321                                 pdev = container_of(dev,
 322                                         struct platform_device, dev);
 323                                 dev_map[i].rtn(pdev);
 324                         }
 325
 326         return 0;
 327 }
 328
 329 #ifdef CONFIG_MTD_PHYSMAP
 330
 331 #ifndef MB
 332 #define MB      (1 << 20)
 333 #endif
 334
 335 /*
 336  * MTD Layout.
 337  *
 338  * FLASH Amount:        0xff000000 - 0xffffffff
 339  * -------------        -----------------------
 340  * Reserved:            0xff000000 - 0xff03ffff
 341  * JFFS2 file system:   0xff040000 - 0xffefffff
 342  * U-boot:              0xfff00000 - 0xffffffff
 343  */
 344 static int __init
 345 ev64360_setup_mtd(void)
 346 {
 347         u32     size;
 348         int     ptbl_entries;
 349         static struct mtd_partition     *ptbl;
 350
 351         size = ev64360_flash_size_0 + ev64360_flash_size_1;
 352         if (!size)
 353                 return -ENOMEM;
 354
 355         ptbl_entries = 3;
 356
 357         if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
 358                 GFP_KERNEL)) == NULL) {
 359
 360                 printk(KERN_WARNING "Can't alloc MTD partition table\n");
 361                 return -ENOMEM;
 362         }
 363         memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
 364
 365         ptbl[0].name = "reserved";
 366         ptbl[0].offset = 0;
 367         ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
 368         ptbl[1].name = "jffs2";
 369         ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
 370         ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
 371         ptbl[2].name = "U-BOOT";
 372         ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
 373         ptbl[2].size = EV64360_MTD_UBOOT_SIZE;
 374
 375         physmap_map.size = size;
 376         physmap_set_partitions(ptbl, ptbl_entries);
 377         return 0;
 378 }
 379
 380 arch_initcall(ev64360_setup_mtd);
 381 #endif
 382
 383 static void
 384 ev64360_restart(char *cmd)
 385 {
 386         ulong   i = 0xffffffff;
 387         volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);
 388
 389         /* issue hard reset */
 390         rtc_base[0xf] = 0x80;
 391         rtc_base[0xc] = 0x00;
 392         rtc_base[0xd] = 0x01;
 393         rtc_base[0xf] = 0x83;
 394
 395         while (i-- > 0) ;
 396         panic("restart failed\n");
 397 }
 398
 399 static void
 400 ev64360_halt(void)
 401 {
 402         while (1) ;
 403         /* NOTREACHED */
 404 }
 405
 406 static void
 407 ev64360_power_off(void)
 408 {
 409         ev64360_halt();
 410         /* NOTREACHED */
 411 }
 412
 413 static int
 414 ev64360_show_cpuinfo(struct seq_file *m)
 415 {
 416         seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
 417         seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
 418         seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);
 419
 420         return 0;
 421 }
 422
 423 static void __init
 424 ev64360_calibrate_decr(void)
 425 {
 426         u32 freq;
 427
 428         freq = ev64360_bus_frequency / 4;
 429
 430         printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
 431                (long)freq / 1000000, (long)freq % 1000000);
 432
 433         tb_ticks_per_jiffy = freq / HZ;
 434         tb_to_us = mulhwu_scale_factor(freq, 1000000);
 435 }
 436
 437 unsigned long __init
 438 ev64360_find_end_of_memory(void)
 439 {
 440         return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 441                 MV64x60_TYPE_MV64360);
 442 }
 443
 444 static inline void
 445 ev64360_set_bat(void)
 446 {
 447         mb();
 448         mtspr(SPRN_DBAT2U, 0xf0001ffe);
 449         mtspr(SPRN_DBAT2L, 0xf000002a);
 450         mb();
 451 }
 452
 453 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 454 static void __init
 455 ev64360_map_io(void)
 456 {
 457         io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
 458                          CONFIG_MV64X60_NEW_BASE, \
 459                          0x00020000, _PAGE_IO);
 460 }
 461 #endif
 462
 463 void __init
 464 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 465               unsigned long r6, unsigned long r7)
 466 {
 467         parse_bootinfo(find_bootinfo());
 468
 469         /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 470          * are non-zero, then we should use the board info from the bd_t
 471          * structure and the cmdline pointed to by r6 instead of the
 472          * information from birecs, if any.  Otherwise, use the information
 473          * from birecs as discovered by the preceeding call to
 474          * parse_bootinfo().  This rule should work with both PPCBoot, which
 475          * uses a bd_t board info structure, and the kernel boot wrapper,
 476          * which uses birecs.
 477          */
 478         if (r3 && r6) {
 479                 /* copy board info structure */
 480                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 481                 /* copy command line */
 482                 *(char *)(r7+KERNELBASE) = 0;
 483                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 484         }
 485         #ifdef CONFIG_ISA
 486         isa_mem_base = 0;
 487         #endif
 488
 489         ppc_md.setup_arch = ev64360_setup_arch;
 490         ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
 491         ppc_md.init_IRQ = mv64360_init_irq;
 492         ppc_md.get_irq = mv64360_get_irq;
 493         ppc_md.restart = ev64360_restart;
 494         ppc_md.power_off = ev64360_power_off;
 495         ppc_md.halt = ev64360_halt;
 496         ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
 497         ppc_md.calibrate_decr = ev64360_calibrate_decr;
 498
 499 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
 500         ppc_md.setup_io_mappings = ev64360_map_io;
 501         ppc_md.progress = mv64x60_mpsc_progress;
 502         mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
 503 #endif
 504
 505 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
 506         platform_notify = ev64360_platform_notify;
 507 #endif
 508
 509         ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
 510 }