arch/ppc/platforms/sandpoint.c

   1 /*
   2  * arch/ppc/platforms/sandpoint_setup.c
   3  *
   4  * Board setup routines for the Motorola SPS Sandpoint Test Platform.
   5  *
   6  * Author: Mark A. Greer
   7  *       mgreer@mvista.com
   8  *
   9  * 2000-2003 (c) MontaVista Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 /*
  16  * This file adds support for the Motorola SPS Sandpoint Test Platform.
  17  * These boards have a PPMC slot for the processor so any combination
  18  * of cpu and host bridge can be attached.  This port is for an 8240 PPMC
  19  * module from Motorola SPS and other closely related cpu/host bridge
  20  * combinations (e.g., 750/755/7400 with MPC107 host bridge).
  21  * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
  22  * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
  23  * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
  24  * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
  25  * but are really 5V).
  26  *
  27  * The firmware on the sandpoint is called DINK (not my acronym :).  This port
  28  * depends on DINK to do some basic initialization (e.g., initialize the memory
  29  * ctlr) and to ensure that the processor is using MAP B (CHRP map).
  30  *
  31  * The switch settings for the Sandpoint board MUST be as follows:
  32  *      S3: down
  33  *      S4: up
  34  *      S5: up
  35  *      S6: down
  36  *
  37  * 'down' is in the direction from the PCI slots towards the PPMC slot;
  38  * 'up' is in the direction from the PPMC slot towards the PCI slots.
  39  * Be careful, the way the sandpoint board is installed in XT chasses will
  40  * make the directions reversed.
  41  *
  42  * Since Motorola listened to our suggestions for improvement, we now have
  43  * the Sandpoint X3 board.  All of the PCI slots are available, it uses
  44  * the serial interrupt interface (just a hardware thing we need to
  45  * configure properly).
  46  *
  47  * Use the default X3 switch settings.  The interrupts are then:
  48  *              EPIC    Source
  49  *                0     SIOINT          (8259, active low)
  50  *                1     PCI #1
  51  *                2     PCI #2
  52  *                3     PCI #3
  53  *                4     PCI #4
  54  *                7     Winbond INTC    (IDE interrupt)
  55  *                8     Winbond INTD    (IDE interrupt)
  56  *
  57  *
  58  * Motorola has finally released a version of DINK32 that correctly
  59  * (seemingly) initalizes the memory controller correctly, regardless
  60  * of the amount of memory in the system.  Once a method of determining
  61  * what version of DINK initializes the system for us, if applicable, is
  62  * found, we can hopefully stop hardcoding 32MB of RAM.
  63  */
  64
  65 #include <linux/config.h>
  66 #include <linux/stddef.h>
  67 #include <linux/kernel.h>
  68 #include <linux/init.h>
  69 #include <linux/errno.h>
  70 #include <linux/reboot.h>
  71 #include <linux/pci.h>
  72 #include <linux/kdev_t.h>
  73 #include <linux/major.h>
  74 #include <linux/initrd.h>
  75 #include <linux/console.h>
  76 #include <linux/delay.h>
  77 #include <linux/irq.h>
  78 #include <linux/ide.h>
  79 #include <linux/seq_file.h>
  80 #include <linux/root_dev.h>
  81 #include <linux/serial.h>
  82 #include <linux/tty.h>  /* for linux/serial_core.h */
  83 #include <linux/serial_core.h>
  84 #include <linux/serial_8250.h>
  85
  86 #include <asm/system.h>
  87 #include <asm/pgtable.h>
  88 #include <asm/page.h>
  89 #include <asm/time.h>
  90 #include <asm/dma.h>
  91 #include <asm/io.h>
  92 #include <asm/machdep.h>
  93 #include <asm/prom.h>
  94 #include <asm/smp.h>
  95 #include <asm/vga.h>
  96 #include <asm/open_pic.h>
  97 #include <asm/i8259.h>
  98 #include <asm/todc.h>
  99 #include <asm/bootinfo.h>
 100 #include <asm/mpc10x.h>
 101 #include <asm/pci-bridge.h>
 102 #include <asm/kgdb.h>
 103 #include <asm/ppc_sys.h>
 104
 105 #include "sandpoint.h"
 106
 107 /* Set non-zero if an X2 Sandpoint detected. */
 108 static int sandpoint_is_x2;
 109
 110 unsigned char __res[sizeof(bd_t)];
 111
 112 static void sandpoint_halt(void);
 113 static void sandpoint_probe_type(void);
 114
 115 /*
 116  * Define all of the IRQ senses and polarities.  Taken from the
 117  * Sandpoint X3 User's manual.
 118  */
 119 static u_char sandpoint_openpic_initsenses[] __initdata = {
 120         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 0: SIOINT */
 121         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 2: PCI Slot 1 */
 122         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 3: PCI Slot 2 */
 123         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 4: PCI Slot 3 */
 124         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 5: PCI Slot 4 */
 125         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 8: IDE (INT C) */
 126         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)       /* 9: IDE (INT D) */
 127 };
 128
 129 /*
 130  * Motorola SPS Sandpoint interrupt routing.
 131  */
 132 static inline int
 133 x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 134 {
 135         static char pci_irq_table[][4] =
 136         /*
 137          *      PCI IDSEL/INTPIN->INTLINE
 138          *         A   B   C   D
 139          */
 140         {
 141                 { 16,  0,  0,  0 },     /* IDSEL 11 - i8259 on Winbond */
 142                 {  0,  0,  0,  0 },     /* IDSEL 12 - unused */
 143                 { 18, 21, 20, 19 },     /* IDSEL 13 - PCI slot 1 */
 144                 { 19, 18, 21, 20 },     /* IDSEL 14 - PCI slot 2 */
 145                 { 20, 19, 18, 21 },     /* IDSEL 15 - PCI slot 3 */
 146                 { 21, 20, 19, 18 },     /* IDSEL 16 - PCI slot 4 */
 147         };
 148
 149         const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
 150         return PCI_IRQ_TABLE_LOOKUP;
 151 }
 152
 153 static inline int
 154 x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 155 {
 156         static char pci_irq_table[][4] =
 157         /*
 158          *      PCI IDSEL/INTPIN->INTLINE
 159          *         A   B   C   D
 160          */
 161         {
 162                 { 18,  0,  0,  0 },     /* IDSEL 11 - i8259 on Windbond */
 163                 {  0,  0,  0,  0 },     /* IDSEL 12 - unused */
 164                 { 16, 17, 18, 19 },     /* IDSEL 13 - PCI slot 1 */
 165                 { 17, 18, 19, 16 },     /* IDSEL 14 - PCI slot 2 */
 166                 { 18, 19, 16, 17 },     /* IDSEL 15 - PCI slot 3 */
 167                 { 19, 16, 17, 18 },     /* IDSEL 16 - PCI slot 4 */
 168         };
 169
 170         const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
 171         return PCI_IRQ_TABLE_LOOKUP;
 172 }
 173
 174 static void __init
 175 sandpoint_setup_winbond_83553(struct pci_controller *hose)
 176 {
 177         int             devfn;
 178
 179         /*
 180          * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
 181          * We can't route the IDE interrupt to PCI INTC# or INTD# because those
 182          * woule interfere with the PMC's INTC# and INTD# lines.
 183          */
 184         /*
 185          * Winbond Fcn 0
 186          */
 187         devfn = PCI_DEVFN(11,0);
 188
 189         early_write_config_byte(hose,
 190                                 0,
 191                                 devfn,
 192                                 0x43, /* IDE Interrupt Routing Control */
 193                                 0xef);
 194         early_write_config_word(hose,
 195                                 0,
 196                                 devfn,
 197                                 0x44, /* PCI Interrupt Routing Control */
 198                                 0x0000);
 199
 200         /* Want ISA memory cycles to be forwarded to PCI bus */
 201         early_write_config_byte(hose,
 202                                 0,
 203                                 devfn,
 204                                 0x48, /* ISA-to-PCI Addr Decoder Control */
 205                                 0xf0);
 206
 207         /* Enable Port 92.  */
 208         early_write_config_byte(hose,
 209                                 0,
 210                                 devfn,
 211                                 0x4e,   /* AT System Control Register */
 212                                 0x06);
 213         /*
 214          * Winbond Fcn 1
 215          */
 216         devfn = PCI_DEVFN(11,1);
 217
 218         /* Put IDE controller into native mode. */
 219         early_write_config_byte(hose,
 220                                 0,
 221                                 devfn,
 222                                 0x09,   /* Programming interface Register */
 223                                 0x8f);
 224
 225         /* Init IRQ routing, enable both ports, disable fast 16 */
 226         early_write_config_dword(hose,
 227                                 0,
 228                                 devfn,
 229                                 0x40,   /* IDE Control/Status Register */
 230                                 0x00ff0011);
 231         return;
 232 }
 233
 234 /* On the sandpoint X2, we must avoid sending configuration cycles to
 235  * device #12 (IDSEL addr = AD12).
 236  */
 237 static int
 238 x2_exclude_device(u_char bus, u_char devfn)
 239 {
 240         if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
 241                 return PCIBIOS_DEVICE_NOT_FOUND;
 242         else
 243                 return PCIBIOS_SUCCESSFUL;
 244 }
 245
 246 static void __init
 247 sandpoint_find_bridges(void)
 248 {
 249         struct pci_controller   *hose;
 250
 251         hose = pcibios_alloc_controller();
 252
 253         if (!hose)
 254                 return;
 255
 256         hose->first_busno = 0;
 257         hose->last_busno = 0xff;
 258
 259         if (mpc10x_bridge_init(hose,
 260                                MPC10X_MEM_MAP_B,
 261                                MPC10X_MEM_MAP_B,
 262                                MPC10X_MAPB_EUMB_BASE) == 0) {
 263
 264                 /* Do early winbond init, then scan PCI bus */
 265                 sandpoint_setup_winbond_83553(hose);
 266                 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 267
 268                 ppc_md.pcibios_fixup = NULL;
 269                 ppc_md.pcibios_fixup_bus = NULL;
 270                 ppc_md.pci_swizzle = common_swizzle;
 271                 if (sandpoint_is_x2) {
 272                         ppc_md.pci_map_irq = x2_map_irq;
 273                         ppc_md.pci_exclude_device = x2_exclude_device;
 274                 } else
 275                         ppc_md.pci_map_irq = x3_map_irq;
 276         }
 277         else {
 278                 if (ppc_md.progress)
 279                         ppc_md.progress("Bridge init failed", 0x100);
 280                 printk("Host bridge init failed\n");
 281         }
 282
 283         return;
 284 }
 285
 286 static void __init
 287 sandpoint_setup_arch(void)
 288 {
 289         /* Probe for Sandpoint model */
 290         sandpoint_probe_type();
 291         if (sandpoint_is_x2)
 292                 epic_serial_mode = 0;
 293
 294         loops_per_jiffy = 100000000 / HZ;
 295
 296 #ifdef CONFIG_BLK_DEV_INITRD
 297         if (initrd_start)
 298                 ROOT_DEV = Root_RAM0;
 299         else
 300 #endif
 301 #ifdef  CONFIG_ROOT_NFS
 302                 ROOT_DEV = Root_NFS;
 303 #else
 304                 ROOT_DEV = Root_HDA1;
 305 #endif
 306
 307         /* Lookup PCI host bridges */
 308         sandpoint_find_bridges();
 309
 310         if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0)
 311         {
 312                 bd_t *bp = (bd_t *)__res;
 313                 struct plat_serial8250_port *pdata;
 314
 315                 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
 316                 if (pdata)
 317                 {
 318                         pdata[0].uartclk = bp->bi_busfreq;
 319                 }
 320
 321 #ifdef CONFIG_SANDPOINT_ENABLE_UART1
 322                 pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
 323                 if (pdata)
 324                 {
 325                         pdata[0].uartclk = bp->bi_busfreq;
 326                 }
 327 #else
 328                 ppc_sys_device_remove(MPC10X_UART1);
 329 #endif
 330         }
 331
 332         printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
 333         printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 334
 335         /* DINK32 12.3 and below do not correctly enable any caches.
 336          * We will do this now with good known values.  Future versions
 337          * of DINK32 are supposed to get this correct.
 338          */
 339         if (cpu_has_feature(CPU_FTR_SPEC7450))
 340                 /* 745x is different.  We only want to pass along enable. */
 341                 _set_L2CR(L2CR_L2E);
 342         else if (cpu_has_feature(CPU_FTR_L2CR))
 343                 /* All modules have 1MB of L2.  We also assume that an
 344                  * L2 divisor of 3 will work.
 345                  */
 346                 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
 347                                 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
 348 #if 0
 349         /* Untested right now. */
 350         if (cpu_has_feature(CPU_FTR_L3CR)) {
 351                 /* Magic value. */
 352                 _set_L3CR(0x8f032000);
 353         }
 354 #endif
 355 }
 356
 357 #define SANDPOINT_87308_CFG_ADDR                0x15c
 358 #define SANDPOINT_87308_CFG_DATA                0x15d
 359
 360 #define SANDPOINT_87308_CFG_INB(addr, byte) {                           \
 361         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 362         (byte) = inb(SANDPOINT_87308_CFG_DATA);                         \
 363 }
 364
 365 #define SANDPOINT_87308_CFG_OUTB(addr, byte) {                          \
 366         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 367         outb((byte), SANDPOINT_87308_CFG_DATA);                         \
 368 }
 369
 370 #define SANDPOINT_87308_SELECT_DEV(dev_num) {                           \
 371         SANDPOINT_87308_CFG_OUTB(0x07, (dev_num));                      \
 372 }
 373
 374 #define SANDPOINT_87308_DEV_ENABLE(dev_num) {                           \
 375         SANDPOINT_87308_SELECT_DEV(dev_num);                            \
 376         SANDPOINT_87308_CFG_OUTB(0x30, 0x01);                           \
 377 }
 378
 379 /*
 380  * To probe the Sandpoint type, we need to check for a connection between GPIO
 381  * pins 6 and 7 on the NS87308 SuperIO.
 382  */
 383 static void __init sandpoint_probe_type(void)
 384 {
 385         u8 x;
 386         /* First, ensure that the GPIO pins are enabled. */
 387         SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
 388         SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
 389         SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
 390         SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
 391
 392         /* Now, set pin 7 to output and pin 6 to input. */
 393         outb((inb(0x701) | 0x80) & 0xbf, 0x701);
 394         /* Set push-pull output */
 395         outb(inb(0x702) | 0x80, 0x702);
 396         /* Set pull-up on input */
 397         outb(inb(0x703) | 0x40, 0x703);
 398         /* Set output high and check */
 399         x = inb(0x700);
 400         outb(x | 0x80, 0x700);
 401         x = inb(0x700);
 402         sandpoint_is_x2 = ! (x & 0x40);
 403         if (ppc_md.progress && sandpoint_is_x2)
 404                 ppc_md.progress("High output says X2", 0);
 405         /* Set output low and check */
 406         outb(x & 0x7f, 0x700);
 407         sandpoint_is_x2 |= inb(0x700) & 0x40;
 408         if (ppc_md.progress && sandpoint_is_x2)
 409                 ppc_md.progress("Low output says X2", 0);
 410         if (ppc_md.progress && ! sandpoint_is_x2)
 411                 ppc_md.progress("Sandpoint is X3", 0);
 412 }
 413
 414 /*
 415  * Fix IDE interrupts.
 416  */
 417 static int __init
 418 sandpoint_fix_winbond_83553(void)
 419 {
 420         /* Make some 8259 interrupt level sensitive */
 421         outb(0xe0, 0x4d0);
 422         outb(0xde, 0x4d1);
 423
 424         return 0;
 425 }
 426
 427 arch_initcall(sandpoint_fix_winbond_83553);
 428
 429 /*
 430  * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
 431  */
 432 static int __init
 433 sandpoint_setup_natl_87308(void)
 434 {
 435         u_char  reg;
 436
 437         /*
 438          * Enable all the devices on the Super I/O chip.
 439          */
 440         SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
 441         SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
 442         SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
 443         SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
 444         SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
 445         SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
 446         SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
 447         SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
 448         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 449         SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
 450         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 451
 452         /* Set up floppy in PS/2 mode */
 453         outb(0x09, SIO_CONFIG_RA);
 454         reg = inb(SIO_CONFIG_RD);
 455         reg = (reg & 0x3F) | 0x40;
 456         outb(reg, SIO_CONFIG_RD);
 457         outb(reg, SIO_CONFIG_RD);       /* Have to write twice to change! */
 458
 459         return 0;
 460 }
 461
 462 arch_initcall(sandpoint_setup_natl_87308);
 463
 464 static int __init
 465 sandpoint_request_io(void)
 466 {
 467         request_region(0x00,0x20,"dma1");
 468         request_region(0x20,0x20,"pic1");
 469         request_region(0x40,0x20,"timer");
 470         request_region(0x80,0x10,"dma page reg");
 471         request_region(0xa0,0x20,"pic2");
 472         request_region(0xc0,0x20,"dma2");
 473
 474         return 0;
 475 }
 476
 477 arch_initcall(sandpoint_request_io);
 478
 479 /*
 480  * Interrupt setup and service.  Interrrupts on the Sandpoint come
 481  * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
 482  * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
 483  * IDE is on EPIC 7 and 8.
 484  */
 485 static void __init
 486 sandpoint_init_IRQ(void)
 487 {
 488         int i;
 489
 490         OpenPIC_InitSenses = sandpoint_openpic_initsenses;
 491         OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
 492
 493         mpc10x_set_openpic();
 494         openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
 495                         i8259_irq);
 496
 497         /*
 498          * openpic_init() has set up irq_desc[16-31] to be openpic
 499          * interrupts.  We need to set irq_desc[0-15] to be i8259
 500          * interrupts.
 501          */
 502         for(i=0; i < NUM_8259_INTERRUPTS; i++)
 503                 irq_desc[i].handler = &i8259_pic;
 504
 505         /*
 506          * The EPIC allows for a read in the range of 0xFEF00000 ->
 507          * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
 508          */
 509         i8259_init(0xfef00000);
 510 }
 511
 512 static u32
 513 sandpoint_irq_canonicalize(u32 irq)
 514 {
 515         if (irq == 2)
 516                 return 9;
 517         else
 518                 return irq;
 519 }
 520
 521 static unsigned long __init
 522 sandpoint_find_end_of_memory(void)
 523 {
 524         bd_t *bp = (bd_t *)__res;
 525
 526         if (bp->bi_memsize)
 527                 return bp->bi_memsize;
 528
 529         /* DINK32 13.0 correctly initalizes things, so iff you use
 530          * this you _should_ be able to change this instead of a
 531          * hardcoded value. */
 532 #if 0
 533         return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
 534 #else
 535         return 32*1024*1024;
 536 #endif
 537 }
 538
 539 static void __init
 540 sandpoint_map_io(void)
 541 {
 542         io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
 543 }
 544
 545 static void
 546 sandpoint_restart(char *cmd)
 547 {
 548         local_irq_disable();
 549
 550         /* Set exception prefix high - to the firmware */
 551         _nmask_and_or_msr(0, MSR_IP);
 552
 553         /* Reset system via Port 92 */
 554         outb(0x00, 0x92);
 555         outb(0x01, 0x92);
 556         for(;;);        /* Spin until reset happens */
 557 }
 558
 559 static void
 560 sandpoint_power_off(void)
 561 {
 562         local_irq_disable();
 563         for(;;);        /* No way to shut power off with software */
 564         /* NOTREACHED */
 565 }
 566
 567 static void
 568 sandpoint_halt(void)
 569 {
 570         sandpoint_power_off();
 571         /* NOTREACHED */
 572 }
 573
 574 static int
 575 sandpoint_show_cpuinfo(struct seq_file *m)
 576 {
 577         seq_printf(m, "vendor\t\t: Motorola SPS\n");
 578         seq_printf(m, "machine\t\t: Sandpoint\n");
 579
 580         return 0;
 581 }
 582
 583 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 584 /*
 585  * IDE support.
 586  */
 587 static int              sandpoint_ide_ports_known = 0;
 588 static unsigned long    sandpoint_ide_regbase[MAX_HWIFS];
 589 static unsigned long    sandpoint_ide_ctl_regbase[MAX_HWIFS];
 590 static unsigned long    sandpoint_idedma_regbase;
 591
 592 static void
 593 sandpoint_ide_probe(void)
 594 {
 595         struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_WINBOND,
 596                         PCI_DEVICE_ID_WINBOND_82C105, NULL);
 597
 598         if (pdev) {
 599                 sandpoint_ide_regbase[0]=pdev->resource[0].start;
 600                 sandpoint_ide_regbase[1]=pdev->resource[2].start;
 601                 sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
 602                 sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
 603                 sandpoint_idedma_regbase=pdev->resource[4].start;
 604                 pci_dev_put(pdev);
 605         }
 606
 607         sandpoint_ide_ports_known = 1;
 608 }
 609
 610 static int
 611 sandpoint_ide_default_irq(unsigned long base)
 612 {
 613         if (sandpoint_ide_ports_known == 0)
 614                 sandpoint_ide_probe();
 615
 616         if (base == sandpoint_ide_regbase[0])
 617                 return SANDPOINT_IDE_INT0;
 618         else if (base == sandpoint_ide_regbase[1])
 619                 return SANDPOINT_IDE_INT1;
 620         else
 621                 return 0;
 622 }
 623
 624 static unsigned long
 625 sandpoint_ide_default_io_base(int index)
 626 {
 627         if (sandpoint_ide_ports_known == 0)
 628                 sandpoint_ide_probe();
 629
 630         return sandpoint_ide_regbase[index];
 631 }
 632
 633 static void __init
 634 sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
 635                 unsigned long ctrl_port, int *irq)
 636 {
 637         unsigned long reg = data_port;
 638         uint    alt_status_base;
 639         int     i;
 640
 641         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 642                 hw->io_ports[i] = reg++;
 643         }
 644
 645         if (data_port == sandpoint_ide_regbase[0]) {
 646                 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
 647                 hw->irq = 14;
 648         }
 649         else if (data_port == sandpoint_ide_regbase[1]) {
 650                 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
 651                 hw->irq = 15;
 652         }
 653         else {
 654                 alt_status_base = 0;
 655                 hw->irq = 0;
 656         }
 657
 658         if (ctrl_port) {
 659                 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 660         } else {
 661                 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
 662         }
 663
 664         if (irq != NULL) {
 665                 *irq = hw->irq;
 666         }
 667 }
 668 #endif
 669
 670 /*
 671  * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
 672  */
 673 static __inline__ void
 674 sandpoint_set_bat(void)
 675 {
 676         unsigned long bat3u, bat3l;
 677
 678         __asm__ __volatile__(
 679                         " lis %0,0xf800\n       \
 680                         ori %1,%0,0x002a\n      \
 681                         ori %0,%0,0x0ffe\n      \
 682                         mtspr 0x21e,%0\n        \
 683                         mtspr 0x21f,%1\n        \
 684                         isync\n                 \
 685                         sync "
 686                         : "=r" (bat3u), "=r" (bat3l));
 687 }
 688
 689 TODC_ALLOC();
 690
 691 void __init
 692 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 693                 unsigned long r6, unsigned long r7)
 694 {
 695         parse_bootinfo(find_bootinfo());
 696
 697         /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 698          * are non-zero, then we should use the board info from the bd_t
 699          * structure and the cmdline pointed to by r6 instead of the
 700          * information from birecs, if any.  Otherwise, use the information
 701          * from birecs as discovered by the preceeding call to
 702          * parse_bootinfo().  This rule should work with both PPCBoot, which
 703          * uses a bd_t board info structure, and the kernel boot wrapper,
 704          * which uses birecs.
 705          */
 706         if (r3 && r6) {
 707                 /* copy board info structure */
 708                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 709                 /* copy command line */
 710                 *(char *)(r7+KERNELBASE) = 0;
 711                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 712         }
 713
 714 #ifdef CONFIG_BLK_DEV_INITRD
 715         /* take care of initrd if we have one */
 716         if (r4) {
 717                 initrd_start = r4 + KERNELBASE;
 718                 initrd_end = r5 + KERNELBASE;
 719         }
 720 #endif /* CONFIG_BLK_DEV_INITRD */
 721
 722         /* Map in board regs, etc. */
 723         sandpoint_set_bat();
 724
 725         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 726         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 727         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 728         ISA_DMA_THRESHOLD = 0x00ffffff;
 729         DMA_MODE_READ = 0x44;
 730         DMA_MODE_WRITE = 0x48;
 731
 732         ppc_md.setup_arch = sandpoint_setup_arch;
 733         ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
 734         ppc_md.irq_canonicalize = sandpoint_irq_canonicalize;
 735         ppc_md.init_IRQ = sandpoint_init_IRQ;
 736         ppc_md.get_irq = openpic_get_irq;
 737
 738         ppc_md.restart = sandpoint_restart;
 739         ppc_md.power_off = sandpoint_power_off;
 740         ppc_md.halt = sandpoint_halt;
 741
 742         ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
 743         ppc_md.setup_io_mappings = sandpoint_map_io;
 744
 745         TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
 746         ppc_md.time_init = todc_time_init;
 747         ppc_md.set_rtc_time = todc_set_rtc_time;
 748         ppc_md.get_rtc_time = todc_get_rtc_time;
 749         ppc_md.calibrate_decr = todc_calibrate_decr;
 750
 751         ppc_md.nvram_read_val = todc_mc146818_read_val;
 752         ppc_md.nvram_write_val = todc_mc146818_write_val;
 753
 754 #ifdef CONFIG_KGDB
 755         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 756 #endif
 757 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 758         ppc_md.progress = gen550_progress;
 759 #endif
 760
 761 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 762         ppc_ide_md.default_irq = sandpoint_ide_default_irq;
 763         ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
 764         ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
 765 #endif
 766 }