2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
39 #include "ipath_common.h"
42 * min buffers we want to have per port, after driver
44 #define IPATH_MIN_USER_PORT_BUFCNT 8
47 * Number of ports we are configured to use (to allow for more pio
48 * buffers per port, etc.) Zero means use chip value.
50 static ushort ipath_cfgports
;
52 module_param_named(cfgports
, ipath_cfgports
, ushort
, S_IRUGO
);
53 MODULE_PARM_DESC(cfgports
, "Set max number of ports to use");
56 * Number of buffers reserved for driver (verbs and layered drivers.)
57 * Reserved at end of buffer list. Initialized based on
58 * number of PIO buffers if not set via module interface.
59 * The problem with this is that it's global, but we'll use different
60 * numbers for different chip types. So the default value is not
61 * very useful. I've redefined it for the 1.3 release so that it's
62 * zero unless set by the user to something else, in which case we
65 static ushort ipath_kpiobufs
;
67 static int ipath_set_kpiobufs(const char *val
, struct kernel_param
*kp
);
69 module_param_call(kpiobufs
, ipath_set_kpiobufs
, param_get_ushort
,
70 &ipath_kpiobufs
, S_IWUSR
| S_IRUGO
);
71 MODULE_PARM_DESC(kpiobufs
, "Set number of PIO buffers for driver");
74 * create_port0_egr - allocate the eager TID buffers
75 * @dd: the infinipath device
77 * This code is now quite different for user and kernel, because
78 * the kernel uses skb's, for the accelerated network performance.
79 * This is the kernel (port0) version.
81 * Allocate the eager TID buffers and program them into infinipath.
82 * We use the network layer alloc_skb() allocator to allocate the
83 * memory, and either use the buffers as is for things like verbs
84 * packets, or pass the buffers up to the ipath layered driver and
85 * thence the network layer, replacing them as we do so (see
88 static int create_port0_egr(struct ipath_devdata
*dd
)
91 struct ipath_skbinfo
*skbinfo
;
94 egrcnt
= dd
->ipath_rcvegrcnt
;
96 skbinfo
= vmalloc(sizeof(*dd
->ipath_port0_skbinfo
) * egrcnt
);
97 if (skbinfo
== NULL
) {
98 ipath_dev_err(dd
, "allocation error for eager TID "
103 for (e
= 0; e
< egrcnt
; e
++) {
105 * This is a bit tricky in that we allocate extra
106 * space for 2 bytes of the 14 byte ethernet header.
107 * These two bytes are passed in the ipath header so
108 * the rest of the data is word aligned. We allocate
109 * 4 bytes so that the data buffer stays word aligned.
110 * See ipath_kreceive() for more details.
112 skbinfo
[e
].skb
= ipath_alloc_skb(dd
, GFP_KERNEL
);
113 if (!skbinfo
[e
].skb
) {
114 ipath_dev_err(dd
, "SKB allocation error for "
115 "eager TID %u\n", e
);
117 dev_kfree_skb(skbinfo
[--e
].skb
);
124 * After loop above, so we can test non-NULL to see if ready
125 * to use at receive, etc.
127 dd
->ipath_port0_skbinfo
= skbinfo
;
129 for (e
= 0; e
< egrcnt
; e
++) {
130 dd
->ipath_port0_skbinfo
[e
].phys
=
131 ipath_map_single(dd
->pcidev
,
132 dd
->ipath_port0_skbinfo
[e
].skb
->data
,
133 dd
->ipath_ibmaxlen
, PCI_DMA_FROMDEVICE
);
134 dd
->ipath_f_put_tid(dd
, e
+ (u64 __iomem
*)
135 ((char __iomem
*) dd
->ipath_kregbase
+
136 dd
->ipath_rcvegrbase
), 0,
137 dd
->ipath_port0_skbinfo
[e
].phys
);
146 static int bringup_link(struct ipath_devdata
*dd
)
151 /* hold IBC in reset */
152 dd
->ipath_control
&= ~INFINIPATH_C_LINKENABLE
;
153 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_control
,
157 * Note that prior to try 14 or 15 of IB, the credit scaling
158 * wasn't working, because it was swapped for writes with the
159 * 1 bit default linkstate field
162 /* ignore pbc and align word */
163 val
= dd
->ipath_piosize2k
- 2 * sizeof(u32
);
165 * for ICRC, which we only send in diag test pkt mode, and we
166 * don't need to worry about that for mtu
170 * Set the IBC maxpktlength to the size of our pio buffers the
171 * maxpktlength is in words. This is *not* the IB data MTU.
173 ibc
= (val
/ sizeof(u32
)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT
;
175 ibc
|= 0x5ULL
<< INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT
;
177 * How often flowctrl sent. More or less in usecs; balance against
178 * watermark value, so that in theory senders always get a flow
179 * control update in time to not let the IB link go idle.
181 ibc
|= 0x3ULL
<< INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT
;
182 /* max error tolerance */
183 ibc
|= 0xfULL
<< INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT
;
184 /* use "real" buffer space for */
185 ibc
|= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT
;
186 /* IB credit flow control. */
187 ibc
|= 0xfULL
<< INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT
;
188 /* initially come up waiting for TS1, without sending anything. */
189 dd
->ipath_ibcctrl
= ibc
;
191 * Want to start out with both LINKCMD and LINKINITCMD in NOP
192 * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that
195 ibc
|= INFINIPATH_IBCC_LINKINITCMD_DISABLE
<<
196 INFINIPATH_IBCC_LINKINITCMD_SHIFT
;
197 ipath_cdbg(VERBOSE
, "Writing 0x%llx to ibcctrl\n",
198 (unsigned long long) ibc
);
199 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_ibcctrl
, ibc
);
201 // be sure chip saw it
202 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_scratch
);
204 ret
= dd
->ipath_f_bringup_serdes(dd
);
207 dev_info(&dd
->pcidev
->dev
, "Could not initialize SerDes, "
211 dd
->ipath_control
|= INFINIPATH_C_LINKENABLE
;
212 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_control
,
219 static struct ipath_portdata
*create_portdata0(struct ipath_devdata
*dd
)
221 struct ipath_portdata
*pd
= NULL
;
223 pd
= kzalloc(sizeof(*pd
), GFP_KERNEL
);
227 /* The port 0 pkey table is used by the layer interface. */
228 pd
->port_pkeys
[0] = IPATH_DEFAULT_P_KEY
;
233 static int init_chip_first(struct ipath_devdata
*dd
,
234 struct ipath_portdata
**pdp
)
236 struct ipath_portdata
*pd
= NULL
;
241 * skip cfgports stuff because we are not allocating memory,
242 * and we don't want problems if the portcnt changed due to
243 * cfgports. We do still check and report a difference, if
244 * not same (should be impossible).
247 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_portcnt
);
249 dd
->ipath_cfgports
= dd
->ipath_portcnt
;
250 else if (ipath_cfgports
<= dd
->ipath_portcnt
) {
251 dd
->ipath_cfgports
= ipath_cfgports
;
252 ipath_dbg("Configured to use %u ports out of %u in chip\n",
253 dd
->ipath_cfgports
, dd
->ipath_portcnt
);
255 dd
->ipath_cfgports
= dd
->ipath_portcnt
;
256 ipath_dbg("Tried to configured to use %u ports; chip "
257 "only supports %u\n", ipath_cfgports
,
261 * Allocate full portcnt array, rather than just cfgports, because
262 * cleanup iterates across all possible ports.
264 dd
->ipath_pd
= kzalloc(sizeof(*dd
->ipath_pd
) * dd
->ipath_portcnt
,
268 ipath_dev_err(dd
, "Unable to allocate portdata array, "
274 dd
->ipath_lastegrheads
= kzalloc(sizeof(*dd
->ipath_lastegrheads
)
275 * dd
->ipath_cfgports
,
277 dd
->ipath_lastrcvhdrqtails
=
278 kzalloc(sizeof(*dd
->ipath_lastrcvhdrqtails
)
279 * dd
->ipath_cfgports
, GFP_KERNEL
);
281 if (!dd
->ipath_lastegrheads
|| !dd
->ipath_lastrcvhdrqtails
) {
282 ipath_dev_err(dd
, "Unable to allocate head arrays, "
288 pd
= create_portdata0(dd
);
291 ipath_dev_err(dd
, "Unable to allocate portdata for port "
296 dd
->ipath_pd
[0] = pd
;
298 dd
->ipath_rcvtidcnt
=
299 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_rcvtidcnt
);
300 dd
->ipath_rcvtidbase
=
301 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_rcvtidbase
);
302 dd
->ipath_rcvegrcnt
=
303 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_rcvegrcnt
);
304 dd
->ipath_rcvegrbase
=
305 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_rcvegrbase
);
307 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_pagealign
);
308 dd
->ipath_piobufbase
=
309 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_sendpiobufbase
);
310 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_sendpiosize
);
311 dd
->ipath_piosize2k
= val
& ~0U;
312 dd
->ipath_piosize4k
= val
>> 32;
314 * Note: the chips support a maximum MTU of 4096, but the driver
315 * hasn't implemented this feature yet, so set the initial value
318 dd
->ipath_ibmtu
= 2048;
319 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_sendpiobufcnt
);
320 dd
->ipath_piobcnt2k
= val
& ~0U;
321 dd
->ipath_piobcnt4k
= val
>> 32;
322 dd
->ipath_pio2kbase
=
323 (u32 __iomem
*) (((char __iomem
*) dd
->ipath_kregbase
) +
324 (dd
->ipath_piobufbase
& 0xffffffff));
325 if (dd
->ipath_piobcnt4k
) {
326 dd
->ipath_pio4kbase
= (u32 __iomem
*)
327 (((char __iomem
*) dd
->ipath_kregbase
) +
328 (dd
->ipath_piobufbase
>> 32));
330 * 4K buffers take 2 pages; we use roundup just to be
331 * paranoid; we calculate it once here, rather than on
334 dd
->ipath_4kalign
= ALIGN(dd
->ipath_piosize4k
,
336 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
338 dd
->ipath_piobcnt2k
, dd
->ipath_piosize2k
,
339 dd
->ipath_pio2kbase
, dd
->ipath_piobcnt4k
,
340 dd
->ipath_piosize4k
, dd
->ipath_pio4kbase
,
343 else ipath_dbg("%u 2k piobufs @ %p\n",
344 dd
->ipath_piobcnt2k
, dd
->ipath_pio2kbase
);
346 spin_lock_init(&dd
->ipath_tid_lock
);
348 spin_lock_init(&dd
->ipath_gpio_lock
);
349 spin_lock_init(&dd
->ipath_eep_st_lock
);
350 sema_init(&dd
->ipath_eep_sem
, 1);
358 * init_chip_reset - re-initialize after a reset, or enable
359 * @dd: the infinipath device
360 * @pdp: output for port data
362 * sanity check at least some of the values after reset, and
363 * ensure no receive or transmit (explictly, in case reset
366 static int init_chip_reset(struct ipath_devdata
*dd
,
367 struct ipath_portdata
**pdp
)
371 *pdp
= dd
->ipath_pd
[0];
372 /* ensure chip does no sends or receives while we re-initialize */
373 dd
->ipath_control
= dd
->ipath_sendctrl
= dd
->ipath_rcvctrl
= 0U;
374 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvctrl
, 0);
375 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
, 0);
376 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_control
, 0);
378 rtmp
= ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_portcnt
);
379 if (dd
->ipath_portcnt
!= rtmp
)
380 dev_info(&dd
->pcidev
->dev
, "portcnt was %u before "
381 "reset, now %u, using original\n",
382 dd
->ipath_portcnt
, rtmp
);
383 rtmp
= ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_rcvtidcnt
);
384 if (rtmp
!= dd
->ipath_rcvtidcnt
)
385 dev_info(&dd
->pcidev
->dev
, "tidcnt was %u before "
386 "reset, now %u, using original\n",
387 dd
->ipath_rcvtidcnt
, rtmp
);
388 rtmp
= ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_rcvtidbase
);
389 if (rtmp
!= dd
->ipath_rcvtidbase
)
390 dev_info(&dd
->pcidev
->dev
, "tidbase was %u before "
391 "reset, now %u, using original\n",
392 dd
->ipath_rcvtidbase
, rtmp
);
393 rtmp
= ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_rcvegrcnt
);
394 if (rtmp
!= dd
->ipath_rcvegrcnt
)
395 dev_info(&dd
->pcidev
->dev
, "egrcnt was %u before "
396 "reset, now %u, using original\n",
397 dd
->ipath_rcvegrcnt
, rtmp
);
398 rtmp
= ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_rcvegrbase
);
399 if (rtmp
!= dd
->ipath_rcvegrbase
)
400 dev_info(&dd
->pcidev
->dev
, "egrbase was %u before "
401 "reset, now %u, using original\n",
402 dd
->ipath_rcvegrbase
, rtmp
);
407 static int init_pioavailregs(struct ipath_devdata
*dd
)
411 dd
->ipath_pioavailregs_dma
= dma_alloc_coherent(
412 &dd
->pcidev
->dev
, PAGE_SIZE
, &dd
->ipath_pioavailregs_phys
,
414 if (!dd
->ipath_pioavailregs_dma
) {
415 ipath_dev_err(dd
, "failed to allocate PIOavail reg area "
422 * we really want L2 cache aligned, but for current CPUs of
423 * interest, they are the same.
425 dd
->ipath_statusp
= (u64
*)
426 ((char *)dd
->ipath_pioavailregs_dma
+
427 ((2 * L1_CACHE_BYTES
+
428 dd
->ipath_pioavregs
* sizeof(u64
)) & ~L1_CACHE_BYTES
));
429 /* copy the current value now that it's really allocated */
430 *dd
->ipath_statusp
= dd
->_ipath_status
;
432 * setup buffer to hold freeze msg, accessible to apps,
435 dd
->ipath_freezemsg
= (char *)&dd
->ipath_statusp
[1];
437 dd
->ipath_freezelen
= L1_CACHE_BYTES
- sizeof(dd
->ipath_statusp
[0]);
446 * init_shadow_tids - allocate the shadow TID array
447 * @dd: the infinipath device
449 * allocate the shadow TID array, so we can ipath_munlock previous
450 * entries. It may make more sense to move the pageshadow to the
451 * port data structure, so we only allocate memory for ports actually
452 * in use, since we at 8k per port, now.
454 static void init_shadow_tids(struct ipath_devdata
*dd
)
459 pages
= vmalloc(dd
->ipath_cfgports
* dd
->ipath_rcvtidcnt
*
460 sizeof(struct page
*));
462 ipath_dev_err(dd
, "failed to allocate shadow page * "
463 "array, no expected sends!\n");
464 dd
->ipath_pageshadow
= NULL
;
468 addrs
= vmalloc(dd
->ipath_cfgports
* dd
->ipath_rcvtidcnt
*
471 ipath_dev_err(dd
, "failed to allocate shadow dma handle "
472 "array, no expected sends!\n");
473 vfree(dd
->ipath_pageshadow
);
474 dd
->ipath_pageshadow
= NULL
;
478 memset(pages
, 0, dd
->ipath_cfgports
* dd
->ipath_rcvtidcnt
*
479 sizeof(struct page
*));
481 dd
->ipath_pageshadow
= pages
;
482 dd
->ipath_physshadow
= addrs
;
485 static void enable_chip(struct ipath_devdata
*dd
,
486 struct ipath_portdata
*pd
, int reinit
)
492 init_waitqueue_head(&ipath_state_wait
);
494 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvctrl
,
497 /* Enable PIO send, and update of PIOavail regs to memory. */
498 dd
->ipath_sendctrl
= INFINIPATH_S_PIOENABLE
|
499 INFINIPATH_S_PIOBUFAVAILUPD
;
500 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
504 * enable port 0 receive, and receive interrupt. other ports
505 * done as user opens and inits them.
507 dd
->ipath_rcvctrl
= INFINIPATH_R_TAILUPD
|
508 (1ULL << INFINIPATH_R_PORTENABLE_SHIFT
) |
509 (1ULL << INFINIPATH_R_INTRAVAIL_SHIFT
);
510 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvctrl
,
514 * now ready for use. this should be cleared whenever we
515 * detect a reset, or initiate one.
517 dd
->ipath_flags
|= IPATH_INITTED
;
520 * init our shadow copies of head from tail values, and write
521 * head values to match.
523 val
= ipath_read_ureg32(dd
, ur_rcvegrindextail
, 0);
524 (void)ipath_write_ureg(dd
, ur_rcvegrindexhead
, val
, 0);
525 dd
->ipath_port0head
= ipath_read_ureg32(dd
, ur_rcvhdrtail
, 0);
527 /* Initialize so we interrupt on next packet received */
528 (void)ipath_write_ureg(dd
, ur_rcvhdrhead
,
529 dd
->ipath_rhdrhead_intr_off
|
530 dd
->ipath_port0head
, 0);
533 * by now pioavail updates to memory should have occurred, so
534 * copy them into our working/shadow registers; this is in
535 * case something went wrong with abort, but mostly to get the
536 * initial values of the generation bit correct.
538 for (i
= 0; i
< dd
->ipath_pioavregs
; i
++) {
542 * Chip Errata bug 6641; even and odd qwords>3 are swapped.
546 val
= dd
->ipath_pioavailregs_dma
[i
- 1];
548 val
= dd
->ipath_pioavailregs_dma
[i
+ 1];
551 val
= dd
->ipath_pioavailregs_dma
[i
];
552 dd
->ipath_pioavailshadow
[i
] = le64_to_cpu(val
);
554 /* can get counters, stats, etc. */
555 dd
->ipath_flags
|= IPATH_PRESENT
;
558 static int init_housekeeping(struct ipath_devdata
*dd
,
559 struct ipath_portdata
**pdp
, int reinit
)
565 * have to clear shadow copies of registers at init that are
566 * not otherwise set here, or all kinds of bizarre things
567 * happen with driver on chip reset
569 dd
->ipath_rcvhdrsize
= 0;
572 * Don't clear ipath_flags as 8bit mode was set before
573 * entering this func. However, we do set the linkstate to
574 * unknown, so we can watch for a transition.
575 * PRESENT is set because we want register reads to work,
576 * and the kernel infrastructure saw it in config space;
577 * We clear it if we have failures.
579 dd
->ipath_flags
|= IPATH_LINKUNK
| IPATH_PRESENT
;
580 dd
->ipath_flags
&= ~(IPATH_LINKACTIVE
| IPATH_LINKARMED
|
581 IPATH_LINKDOWN
| IPATH_LINKINIT
);
583 ipath_cdbg(VERBOSE
, "Try to read spc chip revision\n");
585 ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_revision
);
588 * set up fundamental info we need to use the chip; we assume
589 * if the revision reg and these regs are OK, we don't need to
590 * special case the rest
593 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_sendregbase
);
595 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_counterregbase
);
597 ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_userregbase
);
598 ipath_cdbg(VERBOSE
, "ipath_kregbase %p, sendbase %x usrbase %x, "
599 "cntrbase %x\n", dd
->ipath_kregbase
, dd
->ipath_sregbase
,
600 dd
->ipath_uregbase
, dd
->ipath_cregbase
);
601 if ((dd
->ipath_revision
& 0xffffffff) == 0xffffffff
602 || (dd
->ipath_sregbase
& 0xffffffff) == 0xffffffff
603 || (dd
->ipath_cregbase
& 0xffffffff) == 0xffffffff
604 || (dd
->ipath_uregbase
& 0xffffffff) == 0xffffffff) {
605 ipath_dev_err(dd
, "Register read failures from chip, "
606 "giving up initialization\n");
607 dd
->ipath_flags
&= ~IPATH_PRESENT
;
613 /* clear diagctrl register, in case diags were running and crashed */
614 ipath_write_kreg (dd
, dd
->ipath_kregs
->kr_hwdiagctrl
, 0);
616 /* clear the initial reset flag, in case first driver load */
617 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_errorclear
,
621 ret
= init_chip_reset(dd
, pdp
);
623 ret
= init_chip_first(dd
, pdp
);
628 ipath_cdbg(VERBOSE
, "Revision %llx (PCI %x), %u ports, %u tids, "
629 "%u egrtids\n", (unsigned long long) dd
->ipath_revision
,
630 dd
->ipath_pcirev
, dd
->ipath_portcnt
, dd
->ipath_rcvtidcnt
,
631 dd
->ipath_rcvegrcnt
);
633 if (((dd
->ipath_revision
>> INFINIPATH_R_SOFTWARE_SHIFT
) &
634 INFINIPATH_R_SOFTWARE_MASK
) != IPATH_CHIP_SWVERSION
) {
635 ipath_dev_err(dd
, "Driver only handles version %d, "
636 "chip swversion is %d (%llx), failng\n",
637 IPATH_CHIP_SWVERSION
,
638 (int)(dd
->ipath_revision
>>
639 INFINIPATH_R_SOFTWARE_SHIFT
) &
640 INFINIPATH_R_SOFTWARE_MASK
,
641 (unsigned long long) dd
->ipath_revision
);
645 dd
->ipath_majrev
= (u8
) ((dd
->ipath_revision
>>
646 INFINIPATH_R_CHIPREVMAJOR_SHIFT
) &
647 INFINIPATH_R_CHIPREVMAJOR_MASK
);
648 dd
->ipath_minrev
= (u8
) ((dd
->ipath_revision
>>
649 INFINIPATH_R_CHIPREVMINOR_SHIFT
) &
650 INFINIPATH_R_CHIPREVMINOR_MASK
);
651 dd
->ipath_boardrev
= (u8
) ((dd
->ipath_revision
>>
652 INFINIPATH_R_BOARDID_SHIFT
) &
653 INFINIPATH_R_BOARDID_MASK
);
655 ret
= dd
->ipath_f_get_boardname(dd
, boardn
, sizeof boardn
);
657 snprintf(dd
->ipath_boardversion
, sizeof(dd
->ipath_boardversion
),
658 "Driver %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
660 IPATH_CHIP_VERS_MAJ
, IPATH_CHIP_VERS_MIN
, boardn
,
661 (unsigned)(dd
->ipath_revision
>> INFINIPATH_R_ARCH_SHIFT
) &
662 INFINIPATH_R_ARCH_MASK
,
663 dd
->ipath_majrev
, dd
->ipath_minrev
, dd
->ipath_pcirev
,
664 (unsigned)(dd
->ipath_revision
>>
665 INFINIPATH_R_SOFTWARE_SHIFT
) &
666 INFINIPATH_R_SOFTWARE_MASK
);
668 ipath_dbg("%s", dd
->ipath_boardversion
);
676 * ipath_init_chip - do the actual initialization sequence on the chip
677 * @dd: the infinipath device
678 * @reinit: reinitializing, so don't allocate new memory
680 * Do the actual initialization sequence on the chip. This is done
681 * both from the init routine called from the PCI infrastructure, and
682 * when we reset the chip, or detect that it was reset internally,
683 * or it's administratively re-enabled.
685 * Memory allocation here and in called routines is only done in
686 * the first case (reinit == 0). We have to be careful, because even
687 * without memory allocation, we need to re-write all the chip registers
688 * TIDs, etc. after the reset or enable has completed.
690 int ipath_init_chip(struct ipath_devdata
*dd
, int reinit
)
696 struct ipath_portdata
*pd
= NULL
; /* keep gcc4 happy */
697 gfp_t gfp_flags
= GFP_USER
| __GFP_COMP
;
699 ret
= init_housekeeping(dd
, &pd
, reinit
);
704 * we ignore most issues after reporting them, but have to specially
705 * handle hardware-disabled chips.
708 /* unique error, known to ipath_init_one */
714 * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
715 * but then it no longer nicely fits power of two, and since
716 * we now use routines that backend onto __get_free_pages, the
717 * rest would be wasted.
719 dd
->ipath_rcvhdrcnt
= dd
->ipath_rcvegrcnt
;
720 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvhdrcnt
,
721 dd
->ipath_rcvhdrcnt
);
724 * Set up the shadow copies of the piobufavail registers,
725 * which we compare against the chip registers for now, and
726 * the in memory DMA'ed copies of the registers. This has to
727 * be done early, before we calculate lastport, etc.
729 piobufs
= dd
->ipath_piobcnt2k
+ dd
->ipath_piobcnt4k
;
731 * calc number of pioavail registers, and save it; we have 2
734 dd
->ipath_pioavregs
= ALIGN(piobufs
, sizeof(u64
) * BITS_PER_BYTE
/ 2)
735 / (sizeof(u64
) * BITS_PER_BYTE
/ 2);
736 uports
= dd
->ipath_cfgports
? dd
->ipath_cfgports
- 1 : 0;
737 if (ipath_kpiobufs
== 0) {
738 /* not set by user (this is default) */
739 if (piobufs
>= (uports
* IPATH_MIN_USER_PORT_BUFCNT
) + 32)
745 kpiobufs
= ipath_kpiobufs
;
747 if (kpiobufs
+ (uports
* IPATH_MIN_USER_PORT_BUFCNT
) > piobufs
) {
749 (int) (uports
* IPATH_MIN_USER_PORT_BUFCNT
);
752 dev_info(&dd
->pcidev
->dev
, "Allocating %d PIO bufs of "
753 "%d for kernel leaves too few for %d user ports "
754 "(%d each); using %u\n", kpiobufs
,
755 piobufs
, uports
, IPATH_MIN_USER_PORT_BUFCNT
, i
);
757 * shouldn't change ipath_kpiobufs, because could be
758 * different for different devices...
762 dd
->ipath_lastport_piobuf
= piobufs
- kpiobufs
;
763 dd
->ipath_pbufsport
=
764 uports
? dd
->ipath_lastport_piobuf
/ uports
: 0;
765 val32
= dd
->ipath_lastport_piobuf
- (dd
->ipath_pbufsport
* uports
);
767 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
768 "add to kernel\n", dd
->ipath_pbufsport
, val32
);
769 dd
->ipath_lastport_piobuf
-= val32
;
770 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
771 dd
->ipath_pbufsport
, val32
);
773 dd
->ipath_lastpioindex
= dd
->ipath_lastport_piobuf
;
774 ipath_cdbg(VERBOSE
, "%d PIO bufs for kernel out of %d total %u "
775 "each for %u user ports\n", kpiobufs
,
776 piobufs
, dd
->ipath_pbufsport
, uports
);
778 dd
->ipath_f_early_init(dd
);
780 /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
781 * done after early_init */
783 dd
->ipath_rcvhdrentsize
* (dd
->ipath_rcvhdrcnt
- 1);
784 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvhdrentsize
,
785 dd
->ipath_rcvhdrentsize
);
786 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvhdrsize
,
787 dd
->ipath_rcvhdrsize
);
790 ret
= init_pioavailregs(dd
);
791 init_shadow_tids(dd
);
796 (void)ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendpioavailaddr
,
797 dd
->ipath_pioavailregs_phys
);
799 * this is to detect s/w errors, which the h/w works around by
800 * ignoring the low 6 bits of address, if it wasn't aligned.
802 val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_sendpioavailaddr
);
803 if (val
!= dd
->ipath_pioavailregs_phys
) {
804 ipath_dev_err(dd
, "Catastrophic software error, "
805 "SendPIOAvailAddr written as %lx, "
806 "read back as %llx\n",
807 (unsigned long) dd
->ipath_pioavailregs_phys
,
808 (unsigned long long) val
);
813 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_rcvbthqp
, IPATH_KD_QP
);
816 * make sure we are not in freeze, and PIO send enabled, so
817 * writes to pbc happen
819 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrmask
, 0ULL);
820 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrclear
,
821 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED
);
822 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_control
, 0ULL);
823 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_sendctrl
,
824 INFINIPATH_S_PIOENABLE
);
827 * before error clears, since we expect serdes pll errors during
828 * this, the first time after reset
830 if (bringup_link(dd
)) {
831 dev_info(&dd
->pcidev
->dev
, "Failed to bringup IB link\n");
837 * clear any "expected" hwerrs from reset and/or initialization
838 * clear any that aren't enabled (at least this once), and then
839 * set the enable mask
841 dd
->ipath_f_init_hwerrors(dd
);
842 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrclear
,
843 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED
);
844 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_hwerrmask
,
845 dd
->ipath_hwerrmask
);
847 dd
->ipath_maskederrs
= dd
->ipath_ignorederrs
;
849 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_errorclear
, -1LL);
850 /* enable errors that are masked, at least this first time. */
851 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_errormask
,
852 ~dd
->ipath_maskederrs
);
853 /* clear any interrups up to this point (ints still not enabled) */
854 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_intclear
, -1LL);
857 * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing
858 * re-init, the simplest way to handle this is to free
859 * existing, and re-allocate.
860 * Need to re-create rest of port 0 portdata as well.
863 /* Alloc and init new ipath_portdata for port0,
864 * Then free old pd. Could lead to fragmentation, but also
865 * makes later support for hot-swap easier.
867 struct ipath_portdata
*npd
;
868 npd
= create_portdata0(dd
);
870 ipath_free_pddata(dd
, pd
);
871 dd
->ipath_pd
[0] = pd
= npd
;
873 ipath_dev_err(dd
, "Unable to allocate portdata for"
874 " port 0, failing\n");
879 dd
->ipath_f_tidtemplate(dd
);
880 ret
= ipath_create_rcvhdrq(dd
, pd
);
882 dd
->ipath_hdrqtailptr
=
883 (volatile __le64
*)pd
->port_rcvhdrtail_kvaddr
;
884 ret
= create_port0_egr(dd
);
887 ipath_dev_err(dd
, "failed to allocate port 0 (kernel) "
888 "rcvhdrq and/or egr bufs\n");
890 enable_chip(dd
, pd
, reinit
);
893 if (!ret
&& !reinit
) {
894 /* used when we close a port, for DMA already in flight at close */
895 dd
->ipath_dummy_hdrq
= dma_alloc_coherent(
896 &dd
->pcidev
->dev
, pd
->port_rcvhdrq_size
,
897 &dd
->ipath_dummy_hdrq_phys
,
899 if (!dd
->ipath_dummy_hdrq
) {
900 dev_info(&dd
->pcidev
->dev
,
901 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
902 pd
->port_rcvhdrq_size
);
903 /* fallback to just 0'ing */
904 dd
->ipath_dummy_hdrq_phys
= 0UL;
909 * cause retrigger of pending interrupts ignored during init,
910 * even if we had errors
912 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_intclear
, 0ULL);
914 if(!dd
->ipath_stats_timer_active
) {
916 * first init, or after an admin disable/enable
917 * set up stats retrieval timer, even if we had errors
918 * in last portion of setup
920 init_timer(&dd
->ipath_stats_timer
);
921 dd
->ipath_stats_timer
.function
= ipath_get_faststats
;
922 dd
->ipath_stats_timer
.data
= (unsigned long) dd
;
923 /* every 5 seconds; */
924 dd
->ipath_stats_timer
.expires
= jiffies
+ 5 * HZ
;
925 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
926 add_timer(&dd
->ipath_stats_timer
);
927 dd
->ipath_stats_timer_active
= 1;
932 *dd
->ipath_statusp
|= IPATH_STATUS_CHIP_PRESENT
;
933 if (!dd
->ipath_f_intrsetup(dd
)) {
934 /* now we can enable all interrupts from the chip */
935 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_intmask
,
937 /* force re-interrupt of any pending interrupts. */
938 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_intclear
,
940 /* chip is usable; mark it as initialized */
941 *dd
->ipath_statusp
|= IPATH_STATUS_INITTED
;
943 ipath_dev_err(dd
, "No interrupts enabled, couldn't "
944 "setup interrupt address\n");
946 if (dd
->ipath_cfgports
> ipath_stats
.sps_nports
)
948 * sps_nports is a global, so, we set it to
949 * the highest number of ports of any of the
950 * chips we find; we never decrement it, at
951 * least for now. Since this might have changed
952 * over disable/enable or prior to reset, always
953 * do the check and potentially adjust.
955 ipath_stats
.sps_nports
= dd
->ipath_cfgports
;
957 ipath_dbg("Failed (%d) to initialize chip\n", ret
);
959 /* if ret is non-zero, we probably should do some cleanup
964 static int ipath_set_kpiobufs(const char *str
, struct kernel_param
*kp
)
966 struct ipath_devdata
*dd
;
971 ret
= ipath_parse_ushort(str
, &val
);
973 spin_lock_irqsave(&ipath_devs_lock
, flags
);
983 list_for_each_entry(dd
, &ipath_dev_list
, ipath_list
) {
984 if (dd
->ipath_kregbase
)
986 if (val
> (dd
->ipath_piobcnt2k
+ dd
->ipath_piobcnt4k
-
987 (dd
->ipath_cfgports
*
988 IPATH_MIN_USER_PORT_BUFCNT
)))
992 "Allocating %d PIO bufs for kernel leaves "
993 "too few for %d user ports (%d each)\n",
994 val
, dd
->ipath_cfgports
- 1,
995 IPATH_MIN_USER_PORT_BUFCNT
);
999 dd
->ipath_lastport_piobuf
=
1000 dd
->ipath_piobcnt2k
+ dd
->ipath_piobcnt4k
- val
;
1003 ipath_kpiobufs
= val
;
1006 spin_unlock_irqrestore(&ipath_devs_lock
, flags
);