2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "1.05"
99 PIIX_IOCFG
= 0x54, /* IDE I/O configuration register */
100 ICH5_PMR
= 0x90, /* port mapping register */
101 ICH5_PCS
= 0x92, /* port control and status */
102 PIIX_SCC
= 0x0A, /* sub-class code register */
104 PIIX_FLAG_AHCI
= (1 << 28), /* AHCI possible */
105 PIIX_FLAG_CHECKINTR
= (1 << 29), /* make sure PCI INTx enabled */
106 PIIX_FLAG_COMBINED
= (1 << 30), /* combined mode possible */
108 /* combined mode. if set, PATA is channel 0.
109 * if clear, PATA is channel 1.
111 PIIX_COMB_PATA_P0
= (1 << 1),
112 PIIX_COMB
= (1 << 2), /* combined mode enabled? */
114 PIIX_PORT_ENABLED
= (1 << 0),
115 PIIX_PORT_PRESENT
= (1 << 4),
117 PIIX_80C_PRI
= (1 << 5) | (1 << 4),
118 PIIX_80C_SEC
= (1 << 7) | (1 << 6),
126 PIIX_AHCI_DEVICE
= 6,
129 static int piix_init_one (struct pci_dev
*pdev
,
130 const struct pci_device_id
*ent
);
132 static void piix_pata_phy_reset(struct ata_port
*ap
);
133 static void piix_sata_phy_reset(struct ata_port
*ap
);
134 static void piix_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
);
135 static void piix_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
);
137 static unsigned int in_module_init
= 1;
139 static const struct pci_device_id piix_pci_tbl
[] = {
140 #ifdef ATA_ENABLE_PATA
141 { 0x8086, 0x7111, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, piix4_pata
},
142 { 0x8086, 0x24db, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_pata
},
143 { 0x8086, 0x25a2, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_pata
},
146 /* NOTE: The following PCI ids must be kept in sync with the
147 * list in drivers/pci/quirks.c.
150 { 0x8086, 0x24d1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
151 { 0x8086, 0x24df, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
152 { 0x8086, 0x25a3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
153 { 0x8086, 0x25b0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich5_sata
},
154 { 0x8086, 0x2651, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata
},
155 { 0x8086, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
156 { 0x8086, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
157 { 0x8086, 0x27c0, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
158 { 0x8086, 0x27c4, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
159 { 0x8086, 0x2680, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, ich6_sata_ahci
},
161 { } /* terminate list */
164 static struct pci_driver piix_pci_driver
= {
166 .id_table
= piix_pci_tbl
,
167 .probe
= piix_init_one
,
168 .remove
= ata_pci_remove_one
,
171 static struct scsi_host_template piix_sht
= {
172 .module
= THIS_MODULE
,
174 .ioctl
= ata_scsi_ioctl
,
175 .queuecommand
= ata_scsi_queuecmd
,
176 .eh_strategy_handler
= ata_scsi_error
,
177 .can_queue
= ATA_DEF_QUEUE
,
178 .this_id
= ATA_SHT_THIS_ID
,
179 .sg_tablesize
= LIBATA_MAX_PRD
,
180 .max_sectors
= ATA_MAX_SECTORS
,
181 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
182 .emulated
= ATA_SHT_EMULATED
,
183 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
184 .proc_name
= DRV_NAME
,
185 .dma_boundary
= ATA_DMA_BOUNDARY
,
186 .slave_configure
= ata_scsi_slave_config
,
187 .bios_param
= ata_std_bios_param
,
191 static const struct ata_port_operations piix_pata_ops
= {
192 .port_disable
= ata_port_disable
,
193 .set_piomode
= piix_set_piomode
,
194 .set_dmamode
= piix_set_dmamode
,
196 .tf_load
= ata_tf_load
,
197 .tf_read
= ata_tf_read
,
198 .check_status
= ata_check_status
,
199 .exec_command
= ata_exec_command
,
200 .dev_select
= ata_std_dev_select
,
202 .phy_reset
= piix_pata_phy_reset
,
204 .bmdma_setup
= ata_bmdma_setup
,
205 .bmdma_start
= ata_bmdma_start
,
206 .bmdma_stop
= ata_bmdma_stop
,
207 .bmdma_status
= ata_bmdma_status
,
208 .qc_prep
= ata_qc_prep
,
209 .qc_issue
= ata_qc_issue_prot
,
211 .eng_timeout
= ata_eng_timeout
,
213 .irq_handler
= ata_interrupt
,
214 .irq_clear
= ata_bmdma_irq_clear
,
216 .port_start
= ata_port_start
,
217 .port_stop
= ata_port_stop
,
218 .host_stop
= ata_host_stop
,
221 static const struct ata_port_operations piix_sata_ops
= {
222 .port_disable
= ata_port_disable
,
224 .tf_load
= ata_tf_load
,
225 .tf_read
= ata_tf_read
,
226 .check_status
= ata_check_status
,
227 .exec_command
= ata_exec_command
,
228 .dev_select
= ata_std_dev_select
,
230 .phy_reset
= piix_sata_phy_reset
,
232 .bmdma_setup
= ata_bmdma_setup
,
233 .bmdma_start
= ata_bmdma_start
,
234 .bmdma_stop
= ata_bmdma_stop
,
235 .bmdma_status
= ata_bmdma_status
,
236 .qc_prep
= ata_qc_prep
,
237 .qc_issue
= ata_qc_issue_prot
,
239 .eng_timeout
= ata_eng_timeout
,
241 .irq_handler
= ata_interrupt
,
242 .irq_clear
= ata_bmdma_irq_clear
,
244 .port_start
= ata_port_start
,
245 .port_stop
= ata_port_stop
,
246 .host_stop
= ata_host_stop
,
249 static struct ata_port_info piix_port_info
[] = {
253 .host_flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
|
255 .pio_mask
= 0x1f, /* pio0-4 */
257 .mwdma_mask
= 0x06, /* mwdma1-2 */
259 .mwdma_mask
= 0x00, /* mwdma broken */
261 .udma_mask
= 0x3f, /* udma0-5 */
262 .port_ops
= &piix_pata_ops
,
268 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_SRST
|
269 PIIX_FLAG_COMBINED
| PIIX_FLAG_CHECKINTR
,
270 .pio_mask
= 0x1f, /* pio0-4 */
271 .mwdma_mask
= 0x07, /* mwdma0-2 */
272 .udma_mask
= 0x7f, /* udma0-6 */
273 .port_ops
= &piix_sata_ops
,
279 .host_flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
,
280 .pio_mask
= 0x1f, /* pio0-4 */
282 .mwdma_mask
= 0x06, /* mwdma1-2 */
284 .mwdma_mask
= 0x00, /* mwdma broken */
286 .udma_mask
= ATA_UDMA_MASK_40C
,
287 .port_ops
= &piix_pata_ops
,
293 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_SRST
|
294 PIIX_FLAG_COMBINED
| PIIX_FLAG_CHECKINTR
|
296 .pio_mask
= 0x1f, /* pio0-4 */
297 .mwdma_mask
= 0x07, /* mwdma0-2 */
298 .udma_mask
= 0x7f, /* udma0-6 */
299 .port_ops
= &piix_sata_ops
,
305 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_SRST
|
306 PIIX_FLAG_COMBINED
| PIIX_FLAG_CHECKINTR
|
307 ATA_FLAG_SLAVE_POSS
| PIIX_FLAG_AHCI
,
308 .pio_mask
= 0x1f, /* pio0-4 */
309 .mwdma_mask
= 0x07, /* mwdma0-2 */
310 .udma_mask
= 0x7f, /* udma0-6 */
311 .port_ops
= &piix_sata_ops
,
315 static struct pci_bits piix_enable_bits
[] = {
316 { 0x41U
, 1U, 0x80UL
, 0x80UL
}, /* port 0 */
317 { 0x43U
, 1U, 0x80UL
, 0x80UL
}, /* port 1 */
320 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
321 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
322 MODULE_LICENSE("GPL");
323 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
324 MODULE_VERSION(DRV_VERSION
);
327 * piix_pata_cbl_detect - Probe host controller cable detect info
328 * @ap: Port for which cable detect info is desired
330 * Read 80c cable indicator from ATA PCI device's PCI config
331 * register. This register is normally set by firmware (BIOS).
334 * None (inherited from caller).
336 static void piix_pata_cbl_detect(struct ata_port
*ap
)
338 struct pci_dev
*pdev
= to_pci_dev(ap
->host_set
->dev
);
341 /* no 80c support in host controller? */
342 if ((ap
->udma_mask
& ~ATA_UDMA_MASK_40C
) == 0)
345 /* check BIOS cable detect results */
346 mask
= ap
->hard_port_no
== 0 ? PIIX_80C_PRI
: PIIX_80C_SEC
;
347 pci_read_config_byte(pdev
, PIIX_IOCFG
, &tmp
);
348 if ((tmp
& mask
) == 0)
351 ap
->cbl
= ATA_CBL_PATA80
;
355 ap
->cbl
= ATA_CBL_PATA40
;
356 ap
->udma_mask
&= ATA_UDMA_MASK_40C
;
360 * piix_pata_phy_reset - Probe specified port on PATA host controller
366 * None (inherited from caller).
369 static void piix_pata_phy_reset(struct ata_port
*ap
)
371 struct pci_dev
*pdev
= to_pci_dev(ap
->host_set
->dev
);
373 if (!pci_test_config_bits(pdev
, &piix_enable_bits
[ap
->hard_port_no
])) {
374 ata_port_disable(ap
);
375 printk(KERN_INFO
"ata%u: port disabled. ignoring.\n", ap
->id
);
379 piix_pata_cbl_detect(ap
);
387 * piix_sata_probe - Probe PCI device for present SATA devices
388 * @ap: Port associated with the PCI device we wish to probe
390 * Reads SATA PCI device's PCI config register Port Configuration
391 * and Status (PCS) to determine port and device availability.
394 * None (inherited from caller).
397 * Non-zero if port is enabled, it may or may not have a device
398 * attached in that case (PRESENT bit would only be set if BIOS probe
399 * was done). Zero is returned if port is disabled.
401 static int piix_sata_probe (struct ata_port
*ap
)
403 struct pci_dev
*pdev
= to_pci_dev(ap
->host_set
->dev
);
404 int combined
= (ap
->flags
& ATA_FLAG_SLAVE_POSS
);
405 int orig_mask
, mask
, i
;
408 mask
= (PIIX_PORT_PRESENT
<< ap
->hard_port_no
) |
409 (PIIX_PORT_ENABLED
<< ap
->hard_port_no
);
411 pci_read_config_byte(pdev
, ICH5_PCS
, &pcs
);
412 orig_mask
= (int) pcs
& 0xff;
414 /* TODO: this is vaguely wrong for ICH6 combined mode,
415 * where only two of the four SATA ports are mapped
416 * onto a single ATA channel. It is also vaguely inaccurate
417 * for ICH5, which has only two ports. However, this is ok,
418 * as further device presence detection code will handle
419 * any false positives produced here.
422 for (i
= 0; i
< 4; i
++) {
423 mask
= (PIIX_PORT_ENABLED
<< i
);
425 if ((orig_mask
& mask
) == mask
)
426 if (combined
|| (i
== ap
->hard_port_no
))
434 * piix_sata_phy_reset - Probe specified port on SATA host controller
440 * None (inherited from caller).
443 static void piix_sata_phy_reset(struct ata_port
*ap
)
445 if (!piix_sata_probe(ap
)) {
446 ata_port_disable(ap
);
447 printk(KERN_INFO
"ata%u: SATA port has no device.\n", ap
->id
);
451 ap
->cbl
= ATA_CBL_SATA
;
459 * piix_set_piomode - Initialize host controller PATA PIO timings
460 * @ap: Port whose timings we are configuring
463 * Set PIO mode for device, in host controller PCI config space.
466 * None (inherited from caller).
469 static void piix_set_piomode (struct ata_port
*ap
, struct ata_device
*adev
)
471 unsigned int pio
= adev
->pio_mode
- XFER_PIO_0
;
472 struct pci_dev
*dev
= to_pci_dev(ap
->host_set
->dev
);
473 unsigned int is_slave
= (adev
->devno
!= 0);
474 unsigned int master_port
= ap
->hard_port_no
? 0x42 : 0x40;
475 unsigned int slave_port
= 0x44;
479 static const /* ISP RTC */
480 u8 timings
[][2] = { { 0, 0 },
486 pci_read_config_word(dev
, master_port
, &master_data
);
488 master_data
|= 0x4000;
489 /* enable PPE, IE and TIME */
490 master_data
|= 0x0070;
491 pci_read_config_byte(dev
, slave_port
, &slave_data
);
492 slave_data
&= (ap
->hard_port_no
? 0x0f : 0xf0);
494 (timings
[pio
][0] << 2) |
495 (timings
[pio
][1] << (ap
->hard_port_no
? 4 : 0));
497 master_data
&= 0xccf8;
498 /* enable PPE, IE and TIME */
499 master_data
|= 0x0007;
501 (timings
[pio
][0] << 12) |
502 (timings
[pio
][1] << 8);
504 pci_write_config_word(dev
, master_port
, master_data
);
506 pci_write_config_byte(dev
, slave_port
, slave_data
);
510 * piix_set_dmamode - Initialize host controller PATA PIO timings
511 * @ap: Port whose timings we are configuring
513 * @udma: udma mode, 0 - 6
515 * Set UDMA mode for device, in host controller PCI config space.
518 * None (inherited from caller).
521 static void piix_set_dmamode (struct ata_port
*ap
, struct ata_device
*adev
)
523 unsigned int udma
= adev
->dma_mode
; /* FIXME: MWDMA too */
524 struct pci_dev
*dev
= to_pci_dev(ap
->host_set
->dev
);
525 u8 maslave
= ap
->hard_port_no
? 0x42 : 0x40;
527 unsigned int drive_dn
= (ap
->hard_port_no
? 2 : 0) + adev
->devno
;
528 int a_speed
= 3 << (drive_dn
* 4);
529 int u_flag
= 1 << drive_dn
;
530 int v_flag
= 0x01 << drive_dn
;
531 int w_flag
= 0x10 << drive_dn
;
535 u8 reg48
, reg54
, reg55
;
537 pci_read_config_word(dev
, maslave
, ®4042
);
538 DPRINTK("reg4042 = 0x%04x\n", reg4042
);
539 sitre
= (reg4042
& 0x4000) ? 1 : 0;
540 pci_read_config_byte(dev
, 0x48, ®48
);
541 pci_read_config_word(dev
, 0x4a, ®4a
);
542 pci_read_config_byte(dev
, 0x54, ®54
);
543 pci_read_config_byte(dev
, 0x55, ®55
);
547 case XFER_UDMA_2
: u_speed
= 2 << (drive_dn
* 4); break;
551 case XFER_UDMA_1
: u_speed
= 1 << (drive_dn
* 4); break;
552 case XFER_UDMA_0
: u_speed
= 0 << (drive_dn
* 4); break;
554 case XFER_MW_DMA_1
: break;
560 if (speed
>= XFER_UDMA_0
) {
561 if (!(reg48
& u_flag
))
562 pci_write_config_byte(dev
, 0x48, reg48
| u_flag
);
563 if (speed
== XFER_UDMA_5
) {
564 pci_write_config_byte(dev
, 0x55, (u8
) reg55
|w_flag
);
566 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
568 if ((reg4a
& a_speed
) != u_speed
)
569 pci_write_config_word(dev
, 0x4a, (reg4a
& ~a_speed
) | u_speed
);
570 if (speed
> XFER_UDMA_2
) {
571 if (!(reg54
& v_flag
))
572 pci_write_config_byte(dev
, 0x54, reg54
| v_flag
);
574 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
577 pci_write_config_byte(dev
, 0x48, reg48
& ~u_flag
);
579 pci_write_config_word(dev
, 0x4a, reg4a
& ~a_speed
);
581 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
583 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
587 #define AHCI_PCI_BAR 5
588 #define AHCI_GLOBAL_CTL 0x04
589 #define AHCI_ENABLE (1 << 31)
590 static int piix_disable_ahci(struct pci_dev
*pdev
)
596 /* BUG: pci_enable_device has not yet been called. This
597 * works because this device is usually set up by BIOS.
600 if (!pci_resource_start(pdev
, AHCI_PCI_BAR
) ||
601 !pci_resource_len(pdev
, AHCI_PCI_BAR
))
604 mmio
= pci_iomap(pdev
, AHCI_PCI_BAR
, 64);
608 tmp
= readl(mmio
+ AHCI_GLOBAL_CTL
);
609 if (tmp
& AHCI_ENABLE
) {
611 writel(tmp
, mmio
+ AHCI_GLOBAL_CTL
);
613 tmp
= readl(mmio
+ AHCI_GLOBAL_CTL
);
614 if (tmp
& AHCI_ENABLE
)
618 pci_iounmap(pdev
, mmio
);
623 * piix_check_450nx_errata - Check for problem 450NX setup
625 * Check for the present of 450NX errata #19 and errata #25. If
626 * they are found return an error code so we can turn off DMA
629 static int __devinit
piix_check_450nx_errata(struct pci_dev
*ata_dev
)
631 struct pci_dev
*pdev
= NULL
;
636 while((pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
)) != NULL
)
638 /* Look for 450NX PXB. Check for problem configurations
639 A PCI quirk checks bit 6 already */
640 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
641 pci_read_config_word(pdev
, 0x41, &cfg
);
642 /* Only on the original revision: IDE DMA can hang */
645 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
646 else if(cfg
& (1<<14) && rev
< 5)
650 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "450NX errata present, disabling IDE DMA.\n");
652 dev_printk(KERN_WARNING
, &ata_dev
->dev
, "A BIOS update may resolve this.\n");
657 * piix_init_one - Register PIIX ATA PCI device with kernel services
658 * @pdev: PCI device to register
659 * @ent: Entry in piix_pci_tbl matching with @pdev
661 * Called from kernel PCI layer. We probe for combined mode (sigh),
662 * and then hand over control to libata, for it to do the rest.
665 * Inherited from PCI layer (may sleep).
668 * Zero on success, or -ERRNO value.
671 static int piix_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
673 static int printed_version
;
674 struct ata_port_info
*port_info
[2];
675 unsigned int combined
= 0;
676 unsigned int pata_chan
= 0, sata_chan
= 0;
678 if (!printed_version
++)
679 dev_printk(KERN_DEBUG
, &pdev
->dev
,
680 "version " DRV_VERSION
"\n");
682 /* no hotplugging support (FIXME) */
686 port_info
[0] = &piix_port_info
[ent
->driver_data
];
687 port_info
[1] = &piix_port_info
[ent
->driver_data
];
689 if (port_info
[0]->host_flags
& PIIX_FLAG_AHCI
) {
691 pci_read_config_byte(pdev
, PIIX_SCC
, &tmp
);
692 if (tmp
== PIIX_AHCI_DEVICE
) {
693 int rc
= piix_disable_ahci(pdev
);
699 if (port_info
[0]->host_flags
& PIIX_FLAG_COMBINED
) {
701 pci_read_config_byte(pdev
, ICH5_PMR
, &tmp
);
703 if (tmp
& PIIX_COMB
) {
705 if (tmp
& PIIX_COMB_PATA_P0
)
712 /* On ICH5, some BIOSen disable the interrupt using the
713 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
714 * On ICH6, this bit has the same effect, but only when
715 * MSI is disabled (and it is disabled, as we don't use
716 * message-signalled interrupts currently).
718 if (port_info
[0]->host_flags
& PIIX_FLAG_CHECKINTR
)
722 port_info
[sata_chan
] = &piix_port_info
[ent
->driver_data
];
723 port_info
[sata_chan
]->host_flags
|= ATA_FLAG_SLAVE_POSS
;
724 port_info
[pata_chan
] = &piix_port_info
[ich5_pata
];
726 dev_printk(KERN_WARNING
, &pdev
->dev
,
727 "combined mode detected (p=%u, s=%u)\n",
728 pata_chan
, sata_chan
);
730 if (piix_check_450nx_errata(pdev
)) {
731 /* This writes into the master table but it does not
732 really matter for this errata as we will apply it to
733 all the PIIX devices on the board */
734 port_info
[0]->mwdma_mask
= 0;
735 port_info
[0]->udma_mask
= 0;
736 port_info
[1]->mwdma_mask
= 0;
737 port_info
[1]->udma_mask
= 0;
739 return ata_pci_init_one(pdev
, port_info
, 2);
742 static int __init
piix_init(void)
746 DPRINTK("pci_module_init\n");
747 rc
= pci_module_init(&piix_pci_driver
);
757 static void __exit
piix_exit(void)
759 pci_unregister_driver(&piix_pci_driver
);
762 module_init(piix_init
);
763 module_exit(piix_exit
);