include/asm-alpha/core_t2.h

   1 #ifndef __ALPHA_T2__H__
   2 #define __ALPHA_T2__H__
   3
   4 #include <linux/config.h>
   5 #include <linux/types.h>
   6 #include <linux/spinlock.h>
   7 #include <asm/compiler.h>
   8 #include <asm/system.h>
   9
  10 /*
  11  * T2 is the internal name for the core logic chipset which provides
  12  * memory controller and PCI access for the SABLE-based systems.
  13  *
  14  * This file is based on:
  15  *
  16  * SABLE I/O Specification
  17  * Revision/Update Information: 1.3
  18  *
  19  * jestabro@amt.tay1.dec.com Initial Version.
  20  *
  21  */
  22
  23 #define T2_MEM_R1_MASK 0x07ffffff  /* Mem sparse region 1 mask is 26 bits */
  24
  25 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */
  26 /* All LYNX machines, EV4 or EV5, use the GAMMA bias also */
  27 #define _GAMMA_BIAS             0x8000000000UL
  28
  29 #if defined(CONFIG_ALPHA_GENERIC)
  30 #define GAMMA_BIAS              alpha_mv.sys.t2.gamma_bias
  31 #elif defined(CONFIG_ALPHA_GAMMA)
  32 #define GAMMA_BIAS              _GAMMA_BIAS
  33 #else
  34 #define GAMMA_BIAS              0
  35 #endif
  36
  37 /*
  38  * Memory spaces:
  39  */
  40 #define T2_CONF                 (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
  41 #define T2_IO                   (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
  42 #define T2_SPARSE_MEM           (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
  43 #define T2_DENSE_MEM            (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
  44
  45 #define T2_IOCSR                (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
  46 #define T2_CERR1                (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
  47 #define T2_CERR2                (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
  48 #define T2_CERR3                (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
  49 #define T2_PERR1                (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
  50 #define T2_PERR2                (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
  51 #define T2_PSCR                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
  52 #define T2_HAE_1                (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
  53 #define T2_HAE_2                (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
  54 #define T2_HBASE                (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
  55 #define T2_WBASE1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
  56 #define T2_WMASK1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
  57 #define T2_TBASE1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
  58 #define T2_WBASE2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
  59 #define T2_WMASK2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
  60 #define T2_TBASE2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
  61 #define T2_TLBBR                (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
  62 #define T2_IVR                  (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
  63 #define T2_HAE_3                (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
  64 #define T2_HAE_4                (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
  65
  66 /* The CSRs below are T3/T4 only */
  67 #define T2_WBASE3               (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
  68 #define T2_WMASK3               (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
  69 #define T2_TBASE3               (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
  70
  71 #define T2_TDR0                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
  72 #define T2_TDR1                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
  73 #define T2_TDR2                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
  74 #define T2_TDR3                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
  75 #define T2_TDR4                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
  76 #define T2_TDR5                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
  77 #define T2_TDR6                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
  78 #define T2_TDR7                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
  79
  80 #define T2_WBASE4               (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
  81 #define T2_WMASK4               (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
  82 #define T2_TBASE4               (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
  83
  84 #define T2_AIR                  (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
  85 #define T2_VAR                  (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
  86 #define T2_DIR                  (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
  87 #define T2_ICE                  (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
  88
  89 #define T2_HAE_ADDRESS          T2_HAE_1
  90
  91 /*  T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
  92  3.8fff.ffff
  93  *
  94  *  +--------------+ 3 8000 0000
  95  *  | CPU 0 CSRs   |
  96  *  +--------------+ 3 8100 0000
  97  *  | CPU 1 CSRs   |
  98  *  +--------------+ 3 8200 0000
  99  *  | CPU 2 CSRs   |
 100  *  +--------------+ 3 8300 0000
 101  *  | CPU 3 CSRs   |
 102  *  +--------------+ 3 8400 0000
 103  *  | CPU Reserved |
 104  *  +--------------+ 3 8700 0000
 105  *  | Mem Reserved |
 106  *  +--------------+ 3 8800 0000
 107  *  | Mem 0 CSRs   |
 108  *  +--------------+ 3 8900 0000
 109  *  | Mem 1 CSRs   |
 110  *  +--------------+ 3 8a00 0000
 111  *  | Mem 2 CSRs   |
 112  *  +--------------+ 3 8b00 0000
 113  *  | Mem 3 CSRs   |
 114  *  +--------------+ 3 8c00 0000
 115  *  | Mem Reserved |
 116  *  +--------------+ 3 8e00 0000
 117  *  | PCI Bridge   |
 118  *  +--------------+ 3 8f00 0000
 119  *  | Expansion IO |
 120  *  +--------------+ 3 9000 0000
 121  *
 122  *
 123  */
 124 #define T2_CPU0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
 125 #define T2_CPU1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
 126 #define T2_CPU2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
 127 #define T2_CPU3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
 128
 129 #define T2_CPUn_BASE(n)         (T2_CPU0_BASE + (((n)&3) * 0x001000000L))
 130
 131 #define T2_MEM0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
 132 #define T2_MEM1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
 133 #define T2_MEM2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
 134 #define T2_MEM3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
 135
 136
 137 /*
 138  * Sable CPU Module CSRS
 139  *
 140  * These are CSRs for hardware other than the CPU chip on the CPU module.
 141  * The CPU module has Backup Cache control logic, Cbus control logic, and
 142  * interrupt control logic on it.  There is a duplicate tag store to speed
 143  * up maintaining cache coherency.
 144  */
 145
 146 struct sable_cpu_csr {
 147   unsigned long bcc;     long fill_00[3]; /* Backup Cache Control */
 148   unsigned long bcce;    long fill_01[3]; /* Backup Cache Correctable Error */
 149   unsigned long bccea;   long fill_02[3]; /* B-Cache Corr Err Address Latch */
 150   unsigned long bcue;    long fill_03[3]; /* B-Cache Uncorrectable Error */
 151   unsigned long bcuea;   long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */
 152   unsigned long dter;    long fill_05[3]; /* Duplicate Tag Error */
 153   unsigned long cbctl;   long fill_06[3]; /* CBus Control */
 154   unsigned long cbe;     long fill_07[3]; /* CBus Error */
 155   unsigned long cbeal;   long fill_08[3]; /* CBus Error Addr Latch low */
 156   unsigned long cbeah;   long fill_09[3]; /* CBus Error Addr Latch high */
 157   unsigned long pmbx;    long fill_10[3]; /* Processor Mailbox */
 158   unsigned long ipir;    long fill_11[3]; /* Inter-Processor Int Request */
 159   unsigned long sic;     long fill_12[3]; /* System Interrupt Clear */
 160   unsigned long adlk;    long fill_13[3]; /* Address Lock (LDxL/STxC) */
 161   unsigned long madrl;   long fill_14[3]; /* CBus Miss Address */
 162   unsigned long rev;     long fill_15[3]; /* CMIC Revision */
 163 };
 164
 165 /*
 166  * Data structure for handling T2 machine checks:
 167  */
 168 struct el_t2_frame_header {
 169         unsigned int    elcf_fid;       /* Frame ID (from above) */
 170         unsigned int    elcf_size;      /* Size of frame in bytes */
 171 };
 172
 173 struct el_t2_procdata_mcheck {
 174         unsigned long   elfmc_paltemp[32];      /* PAL TEMP REGS. */
 175         /* EV4-specific fields */
 176         unsigned long   elfmc_exc_addr; /* Addr of excepting insn. */
 177         unsigned long   elfmc_exc_sum;  /* Summary of arith traps. */
 178         unsigned long   elfmc_exc_mask; /* Exception mask (from exc_sum). */
 179         unsigned long   elfmc_iccsr;    /* IBox hardware enables. */
 180         unsigned long   elfmc_pal_base; /* Base address for PALcode. */
 181         unsigned long   elfmc_hier;     /* Hardware Interrupt Enable. */
 182         unsigned long   elfmc_hirr;     /* Hardware Interrupt Request. */
 183         unsigned long   elfmc_mm_csr;   /* D-stream fault info. */
 184         unsigned long   elfmc_dc_stat;  /* D-cache status (ECC/Parity Err). */
 185         unsigned long   elfmc_dc_addr;  /* EV3 Phys Addr for ECC/DPERR. */
 186         unsigned long   elfmc_abox_ctl; /* ABox Control Register. */
 187         unsigned long   elfmc_biu_stat; /* BIU Status. */
 188         unsigned long   elfmc_biu_addr; /* BUI Address. */
 189         unsigned long   elfmc_biu_ctl;  /* BIU Control. */
 190         unsigned long   elfmc_fill_syndrome; /* For correcting ECC errors. */
 191         unsigned long   elfmc_fill_addr;/* Cache block which was being read. */
 192         unsigned long   elfmc_va;       /* Effective VA of fault or miss. */
 193         unsigned long   elfmc_bc_tag;   /* Backup Cache Tag Probe Results. */
 194 };
 195
 196 /*
 197  * Sable processor specific Machine Check Data segment.
 198  */
 199
 200 struct el_t2_logout_header {
 201         unsigned int    elfl_size;      /* size in bytes of logout area. */
 202         unsigned int    elfl_sbz1:31;   /* Should be zero. */
 203         unsigned int    elfl_retry:1;   /* Retry flag. */
 204         unsigned int    elfl_procoffset; /* Processor-specific offset. */
 205         unsigned int    elfl_sysoffset;  /* Offset of system-specific. */
 206         unsigned int    elfl_error_type;        /* PAL error type code. */
 207         unsigned int    elfl_frame_rev;         /* PAL Frame revision. */
 208 };
 209 struct el_t2_sysdata_mcheck {
 210         unsigned long    elcmc_bcc;           /* CSR 0 */
 211         unsigned long    elcmc_bcce;          /* CSR 1 */
 212         unsigned long    elcmc_bccea;      /* CSR 2 */
 213         unsigned long    elcmc_bcue;          /* CSR 3 */
 214         unsigned long    elcmc_bcuea;      /* CSR 4 */
 215         unsigned long    elcmc_dter;          /* CSR 5 */
 216         unsigned long    elcmc_cbctl;      /* CSR 6 */
 217         unsigned long    elcmc_cbe;           /* CSR 7 */
 218         unsigned long    elcmc_cbeal;      /* CSR 8 */
 219         unsigned long    elcmc_cbeah;      /* CSR 9 */
 220         unsigned long    elcmc_pmbx;          /* CSR 10 */
 221         unsigned long    elcmc_ipir;          /* CSR 11 */
 222         unsigned long    elcmc_sic;           /* CSR 12 */
 223         unsigned long    elcmc_adlk;          /* CSR 13 */
 224         unsigned long    elcmc_madrl;      /* CSR 14 */
 225         unsigned long    elcmc_crrev4;     /* CSR 15 */
 226 };
 227
 228 /*
 229  * Sable memory error frame - sable pfms section 3.42
 230  */
 231 struct el_t2_data_memory {
 232         struct  el_t2_frame_header elcm_hdr;    /* ID$MEM-FERR = 0x08 */
 233         unsigned int  elcm_module;      /* Module id. */
 234         unsigned int  elcm_res04;       /* Reserved. */
 235         unsigned long elcm_merr;        /* CSR0: Error Reg 1. */
 236         unsigned long elcm_mcmd1;       /* CSR1: Command Trap 1. */
 237         unsigned long elcm_mcmd2;       /* CSR2: Command Trap 2. */
 238         unsigned long elcm_mconf;       /* CSR3: Configuration. */
 239         unsigned long elcm_medc1;       /* CSR4: EDC Status 1. */
 240         unsigned long elcm_medc2;       /* CSR5: EDC Status 2. */
 241         unsigned long elcm_medcc;       /* CSR6: EDC Control. */
 242         unsigned long elcm_msctl;       /* CSR7: Stream Buffer Control. */
 243         unsigned long elcm_mref;        /* CSR8: Refresh Control. */
 244         unsigned long elcm_filter;      /* CSR9: CRD Filter Control. */
 245 };
 246
 247
 248 /*
 249  * Sable other CPU error frame - sable pfms section 3.43
 250  */
 251 struct el_t2_data_other_cpu {
 252         short         elco_cpuid;       /* CPU ID */
 253         short         elco_res02[3];
 254         unsigned long elco_bcc; /* CSR 0 */
 255         unsigned long elco_bcce;        /* CSR 1 */
 256         unsigned long elco_bccea;       /* CSR 2 */
 257         unsigned long elco_bcue;        /* CSR 3 */
 258         unsigned long elco_bcuea;       /* CSR 4 */
 259         unsigned long elco_dter;        /* CSR 5 */
 260         unsigned long elco_cbctl;       /* CSR 6 */
 261         unsigned long elco_cbe; /* CSR 7 */
 262         unsigned long elco_cbeal;       /* CSR 8 */
 263         unsigned long elco_cbeah;       /* CSR 9 */
 264         unsigned long elco_pmbx;        /* CSR 10 */
 265         unsigned long elco_ipir;        /* CSR 11 */
 266         unsigned long elco_sic; /* CSR 12 */
 267         unsigned long elco_adlk;        /* CSR 13 */
 268         unsigned long elco_madrl;       /* CSR 14 */
 269         unsigned long elco_crrev4;      /* CSR 15 */
 270 };
 271
 272 /*
 273  * Sable other CPU error frame - sable pfms section 3.44
 274  */
 275 struct el_t2_data_t2{
 276         struct el_t2_frame_header elct_hdr;     /* ID$T2-FRAME */
 277         unsigned long elct_iocsr;       /* IO Control and Status Register */
 278         unsigned long elct_cerr1;       /* Cbus Error Register 1 */
 279         unsigned long elct_cerr2;       /* Cbus Error Register 2 */
 280         unsigned long elct_cerr3;       /* Cbus Error Register 3 */
 281         unsigned long elct_perr1;       /* PCI Error Register 1 */
 282         unsigned long elct_perr2;       /* PCI Error Register 2 */
 283         unsigned long elct_hae0_1;      /* High Address Extension Register 1 */
 284         unsigned long elct_hae0_2;      /* High Address Extension Register 2 */
 285         unsigned long elct_hbase;       /* High Base Register */
 286         unsigned long elct_wbase1;      /* Window Base Register 1 */
 287         unsigned long elct_wmask1;      /* Window Mask Register 1 */
 288         unsigned long elct_tbase1;      /* Translated Base Register 1 */
 289         unsigned long elct_wbase2;      /* Window Base Register 2 */
 290         unsigned long elct_wmask2;      /* Window Mask Register 2 */
 291         unsigned long elct_tbase2;      /* Translated Base Register 2 */
 292         unsigned long elct_tdr0;        /* TLB Data Register 0 */
 293         unsigned long elct_tdr1;        /* TLB Data Register 1 */
 294         unsigned long elct_tdr2;        /* TLB Data Register 2 */
 295         unsigned long elct_tdr3;        /* TLB Data Register 3 */
 296         unsigned long elct_tdr4;        /* TLB Data Register 4 */
 297         unsigned long elct_tdr5;        /* TLB Data Register 5 */
 298         unsigned long elct_tdr6;        /* TLB Data Register 6 */
 299         unsigned long elct_tdr7;        /* TLB Data Register 7 */
 300 };
 301
 302 /*
 303  * Sable error log data structure - sable pfms section 3.40
 304  */
 305 struct el_t2_data_corrected {
 306         unsigned long elcpb_biu_stat;
 307         unsigned long elcpb_biu_addr;
 308         unsigned long elcpb_biu_ctl;
 309         unsigned long elcpb_fill_syndrome;
 310         unsigned long elcpb_fill_addr;
 311         unsigned long elcpb_bc_tag;
 312 };
 313
 314 /*
 315  * Sable error log data structure
 316  * Note there are 4 memory slots on sable (see t2.h)
 317  */
 318 struct el_t2_frame_mcheck {
 319         struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */
 320         struct el_t2_logout_header elfmc_hdr;
 321         struct el_t2_procdata_mcheck elfmc_procdata;
 322         struct el_t2_sysdata_mcheck elfmc_sysdata;
 323         struct el_t2_data_t2 elfmc_t2data;
 324         struct el_t2_data_memory elfmc_memdata[4];
 325         struct el_t2_frame_header elfmc_footer; /* empty */
 326 };
 327
 328
 329 /*
 330  * Sable error log data structures on memory errors
 331  */
 332 struct el_t2_frame_corrected {
 333         struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */
 334         struct el_t2_logout_header elfcc_hdr;
 335         struct el_t2_data_corrected elfcc_procdata;
 336 /*      struct el_t2_data_t2 elfcc_t2data;              */
 337 /*      struct el_t2_data_memory elfcc_memdata[4];      */
 338         struct el_t2_frame_header elfcc_footer; /* empty */
 339 };
 340
 341
 342 #ifdef __KERNEL__
 343
 344 #ifndef __EXTERN_INLINE
 345 #define __EXTERN_INLINE extern inline
 346 #define __IO_EXTERN_INLINE
 347 #endif
 348
 349 /*
 350  * I/O functions:
 351  *
 352  * T2 (the core logic PCI/memory support chipset for the SABLE
 353  * series of processors uses a sparse address mapping scheme to
 354  * get at PCI memory and I/O.
 355  */
 356
 357 #define vip     volatile int *
 358 #define vuip    volatile unsigned int *
 359
 360 static inline u8 t2_inb(unsigned long addr)
 361 {
 362         long result = *(vip) ((addr << 5) + T2_IO + 0x00);
 363         return __kernel_extbl(result, addr & 3);
 364 }
 365
 366 static inline void t2_outb(u8 b, unsigned long addr)
 367 {
 368         unsigned long w;
 369
 370         w = __kernel_insbl(b, addr & 3);
 371         *(vuip) ((addr << 5) + T2_IO + 0x00) = w;
 372         mb();
 373 }
 374
 375 static inline u16 t2_inw(unsigned long addr)
 376 {
 377         long result = *(vip) ((addr << 5) + T2_IO + 0x08);
 378         return __kernel_extwl(result, addr & 3);
 379 }
 380
 381 static inline void t2_outw(u16 b, unsigned long addr)
 382 {
 383         unsigned long w;
 384
 385         w = __kernel_inswl(b, addr & 3);
 386         *(vuip) ((addr << 5) + T2_IO + 0x08) = w;
 387         mb();
 388 }
 389
 390 static inline u32 t2_inl(unsigned long addr)
 391 {
 392         return *(vuip) ((addr << 5) + T2_IO + 0x18);
 393 }
 394
 395 static inline void t2_outl(u32 b, unsigned long addr)
 396 {
 397         *(vuip) ((addr << 5) + T2_IO + 0x18) = b;
 398         mb();
 399 }
 400
 401
 402 /*
 403  * Memory functions.
 404  *
 405  * For reading and writing 8 and 16 bit quantities we need to
 406  * go through one of the three sparse address mapping regions
 407  * and use the HAE_MEM CSR to provide some bits of the address.
 408  * The following few routines use only sparse address region 1
 409  * which gives 1Gbyte of accessible space which relates exactly
 410  * to the amount of PCI memory mapping *into* system address space.
 411  * See p 6-17 of the specification but it looks something like this:
 412  *
 413  * 21164 Address:
 414  *
 415  *          3         2         1
 416  * 9876543210987654321098765432109876543210
 417  * 1ZZZZ0.PCI.QW.Address............BBLL
 418  *
 419  * ZZ = SBZ
 420  * BB = Byte offset
 421  * LL = Transfer length
 422  *
 423  * PCI Address:
 424  *
 425  * 3         2         1
 426  * 10987654321098765432109876543210
 427  * HHH....PCI.QW.Address........ 00
 428  *
 429  * HHH = 31:29 HAE_MEM CSR
 430  *
 431  */
 432
 433 #define t2_set_hae { \
 434         msb = addr  >> 27; \
 435         addr &= T2_MEM_R1_MASK; \
 436         set_hae(msb); \
 437 }
 438
 439 static spinlock_t t2_hae_lock = SPIN_LOCK_UNLOCKED;
 440
 441 __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr)
 442 {
 443         unsigned long addr = (unsigned long) xaddr;
 444         unsigned long result, msb;
 445         unsigned long flags;
 446         spin_lock_irqsave(&t2_hae_lock, flags);
 447
 448         t2_set_hae;
 449
 450         result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
 451         spin_unlock_irqrestore(&t2_hae_lock, flags);
 452         return __kernel_extbl(result, addr & 3);
 453 }
 454
 455 __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr)
 456 {
 457         unsigned long addr = (unsigned long) xaddr;
 458         unsigned long result, msb;
 459         unsigned long flags;
 460         spin_lock_irqsave(&t2_hae_lock, flags);
 461
 462         t2_set_hae;
 463
 464         result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
 465         spin_unlock_irqrestore(&t2_hae_lock, flags);
 466         return __kernel_extwl(result, addr & 3);
 467 }
 468
 469 /*
 470  * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
 471  * because we cannot access all of DENSE without changing its HAE.
 472  */
 473 __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr)
 474 {
 475         unsigned long addr = (unsigned long) xaddr;
 476         unsigned long result, msb;
 477         unsigned long flags;
 478         spin_lock_irqsave(&t2_hae_lock, flags);
 479
 480         t2_set_hae;
 481
 482         result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
 483         spin_unlock_irqrestore(&t2_hae_lock, flags);
 484         return result & 0xffffffffUL;
 485 }
 486
 487 __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr)
 488 {
 489         unsigned long addr = (unsigned long) xaddr;
 490         unsigned long r0, r1, work, msb;
 491         unsigned long flags;
 492         spin_lock_irqsave(&t2_hae_lock, flags);
 493
 494         t2_set_hae;
 495
 496         work = (addr << 5) + T2_SPARSE_MEM + 0x18;
 497         r0 = *(vuip)(work);
 498         r1 = *(vuip)(work + (4 << 5));
 499         spin_unlock_irqrestore(&t2_hae_lock, flags);
 500         return r1 << 32 | r0;
 501 }
 502
 503 __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr)
 504 {
 505         unsigned long addr = (unsigned long) xaddr;
 506         unsigned long msb, w;
 507         unsigned long flags;
 508         spin_lock_irqsave(&t2_hae_lock, flags);
 509
 510         t2_set_hae;
 511
 512         w = __kernel_insbl(b, addr & 3);
 513         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
 514         spin_unlock_irqrestore(&t2_hae_lock, flags);
 515 }
 516
 517 __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr)
 518 {
 519         unsigned long addr = (unsigned long) xaddr;
 520         unsigned long msb, w;
 521         unsigned long flags;
 522         spin_lock_irqsave(&t2_hae_lock, flags);
 523
 524         t2_set_hae;
 525
 526         w = __kernel_inswl(b, addr & 3);
 527         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
 528         spin_unlock_irqrestore(&t2_hae_lock, flags);
 529 }
 530
 531 /*
 532  * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
 533  * because we cannot access all of DENSE without changing its HAE.
 534  */
 535 __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr)
 536 {
 537         unsigned long addr = (unsigned long) xaddr;
 538         unsigned long msb;
 539         unsigned long flags;
 540         spin_lock_irqsave(&t2_hae_lock, flags);
 541
 542         t2_set_hae;
 543
 544         *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
 545         spin_unlock_irqrestore(&t2_hae_lock, flags);
 546 }
 547
 548 __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr)
 549 {
 550         unsigned long addr = (unsigned long) xaddr;
 551         unsigned long msb, work;
 552         unsigned long flags;
 553         spin_lock_irqsave(&t2_hae_lock, flags);
 554
 555         t2_set_hae;
 556
 557         work = (addr << 5) + T2_SPARSE_MEM + 0x18;
 558         *(vuip)work = b;
 559         *(vuip)(work + (4 << 5)) = b >> 32;
 560         spin_unlock_irqrestore(&t2_hae_lock, flags);
 561 }
 562
 563 __EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr)
 564 {
 565         return (void __iomem *)(addr + T2_IO);
 566 }
 567
 568 __EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr,
 569                                          unsigned long size)
 570 {
 571         return (void __iomem *)(addr + T2_DENSE_MEM);
 572 }
 573
 574 __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
 575 {
 576         return (long)addr >= 0;
 577 }
 578
 579 __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr)
 580 {
 581         return (unsigned long)addr >= T2_DENSE_MEM;
 582 }
 583
 584 /* New-style ioread interface.  The mmio routines are so ugly for T2 that
 585    it doesn't make sense to merge the pio and mmio routines.  */
 586
 587 #define IOPORT(OS, NS)                                                  \
 588 __EXTERN_INLINE unsigned int t2_ioread##NS(void __iomem *xaddr)         \
 589 {                                                                       \
 590         if (t2_is_mmio(xaddr))                                          \
 591                 return t2_read##OS(xaddr - T2_DENSE_MEM);               \
 592         else                                                            \
 593                 return t2_in##OS((unsigned long)xaddr - T2_IO);         \
 594 }                                                                       \
 595 __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr)       \
 596 {                                                                       \
 597         if (t2_is_mmio(xaddr))                                          \
 598                 t2_write##OS(b, xaddr - T2_DENSE_MEM);                  \
 599         else                                                            \
 600                 t2_out##OS(b, (unsigned long)xaddr - T2_IO);            \
 601 }
 602
 603 IOPORT(b, 8)
 604 IOPORT(w, 16)
 605 IOPORT(l, 32)
 606
 607 #undef IOPORT
 608
 609 #undef vip
 610 #undef vuip
 611
 612 #undef __IO_PREFIX
 613 #define __IO_PREFIX             t2
 614 #define t2_trivial_rw_bw        0
 615 #define t2_trivial_rw_lq        0
 616 #define t2_trivial_io_bw        0
 617 #define t2_trivial_io_lq        0
 618 #define t2_trivial_iounmap      1
 619 #include <asm/io_trivial.h>
 620
 621 #ifdef __IO_EXTERN_INLINE
 622 #undef __EXTERN_INLINE
 623 #undef __IO_EXTERN_INLINE
 624 #endif
 625
 626 #endif /* __KERNEL__ */
 627
 628 #endif /* __ALPHA_T2__H__ */