include/asm-arm/arch-epxa10db/pld_conf00.h

   1 #ifndef __PLD_CONF00_H
   2 #define __PLD_CONF00_H
   3
   4 /*
   5  * Register definitions for the PLD Configuration Logic
   6  */
   7
   8 /*
   9  *
  10  *  This file contains the register definitions for the Excalibur
  11  *  Interrupt controller INT_CTRL00.
  12  *
  13  *  Copyright (C) 2001 Altera Corporation
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  28  */
  29
  30 #define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR))
  31 #define CONFIG_CONTROL_LK_MSK (0x1)
  32 #define CONFIG_CONTROL_LK_OFST (0)
  33 #define CONFIG_CONTROL_CO_MSK (0x2)
  34 #define CONFIG_CONTROL_CO_OFST (1)
  35 #define CONFIG_CONTROL_B_MSK  (0x4)
  36 #define CONFIG_CONTROL_B_OFST (2)
  37 #define CONFIG_CONTROL_PC_MSK (0x8)
  38 #define CONFIG_CONTROL_PC_OFST (3)
  39 #define CONFIG_CONTROL_E_MSK (0x10)
  40 #define CONFIG_CONTROL_E_OFST (4)
  41 #define CONFIG_CONTROL_ES_MSK (0xE0)
  42 #define CONFIG_CONTROL_ES_OFST (5)
  43 #define CONFIG_CONTROL_ES_0_MSK (0x20)
  44 #define CONFIG_CONTROL_ES_1_MSK (0x40)
  45 #define CONFIG_CONTROL_ES_2_MSK (0x80)
  46
  47 #define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0x4 ))
  48 #define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF)
  49 #define CONFIG_CONTROL_CLOCK_RATIO_OFST (0)
  50
  51 #define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0x8 ))
  52 #define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF)
  53 #define CONFIG_CONTROL_DATA_OFST (0)
  54
  55 #define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0xC ))
  56 #define CONFIG_UNLOCK_MSK (0xFFFFFFFF)
  57 #define CONFIG_UNLOCK_OFST (0)
  58
  59 #define CONFIG_UNLOCK_MAGIC (0x554E4C4B)
  60
  61 #endif /* __PLD_CONF00_H */
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