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[CONNECTOR]: Update documentation to match reality.
[linux-2.6/verdex.git] / include / asm-arm / arch-s3c2410 / io.h
blob418233a7ee6fb2054debf777251643f2073972b3
1 /*
2 * linux/include/asm-arm/arch-s3c2410/io.h
3 * from linux/include/asm-arm/arch-rpc/io.h
4 *
5 * Copyright (C) 1997 Russell King
6 * (C) 2003 Simtec Electronics
7 *
8 * Modifications:
9 * 06-Dec-1997 RMK Created.
10 * 02-Sep-2003 BJD Modified for S3C2410
11 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
12 *
13 */
14
15 #ifndef __ASM_ARM_ARCH_IO_H
16 #define __ASM_ARM_ARCH_IO_H
17
18 #define IO_SPACE_LIMIT 0xffffffff
19
20 /*
21 * We use two different types of addressing - PC style addresses, and ARM
22 * addresses. PC style accesses the PC hardware with the normal PC IO
23 * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28
24 * and are translated to the start of IO. Note that all addresses are
25 * not shifted left!
26 */
27
28 #define __PORT_PCIO(x) ((x) < (1<<28))
29
30 #define PCIO_BASE (S3C24XX_VA_ISA_WORD)
31 #define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE)
32 #define PCIO_BASE_w (S3C24XX_VA_ISA_WORD)
33 #define PCIO_BASE_l (S3C24XX_VA_ISA_WORD)
34 /*
35 * Dynamic IO functions - let the compiler
36 * optimize the expressions
37 */
38
39 #define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
40 static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
41 { \
42 unsigned long temp; \
43 __asm__ __volatile__( \
44 "cmp %2, #(1<<28)\n\t" \
45 "mov %0, %2\n\t" \
46 "addcc %0, %0, %3\n\t" \
47 "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \
48 : "=&r" (temp) \
49 : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
50 : "cc"); \
51 }
52
53
54 #define DECLARE_DYN_IN(sz,fnsuffix,instr) \
55 static inline unsigned sz __in##fnsuffix (unsigned int port) \
56 { \
57 unsigned long temp, value; \
58 __asm__ __volatile__( \
59 "cmp %2, #(1<<28)\n\t" \
60 "mov %0, %2\n\t" \
61 "addcc %0, %0, %3\n\t" \
62 "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
63 : "=&r" (temp), "=r" (value) \
64 : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \
65 : "cc"); \
66 return (unsigned sz)value; \
67 }
68
69 static inline void __iomem *__ioaddr (unsigned long port)
70 {
71 return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
72 }
73
74 #define DECLARE_IO(sz,fnsuffix,instr) \
75 DECLARE_DYN_IN(sz,fnsuffix,instr) \
76 DECLARE_DYN_OUT(sz,fnsuffix,instr)
77
78 DECLARE_IO(char,b,"b")
79 DECLARE_IO(short,w,"h")
80 DECLARE_IO(int,l,"")
81
82 #undef DECLARE_IO
83 #undef DECLARE_DYN_IN
84
85 /*
86 * Constant address IO functions
87 *
88 * These have to be macros for the 'J' constraint to work -
89 * +/-4096 immediate operand.
90 */
91 #define __outbc(value,port) \
92 ({ \
93 if (__PORT_PCIO((port))) \
94 __asm__ __volatile__( \
95 "strb %0, [%1, %2] @ outbc" \
96 : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \
97 else \
98 __asm__ __volatile__( \
99 "strb %0, [%1, #0] @ outbc" \
100 : : "r" (value), "r" ((port))); \
101 })
102
103 #define __inbc(port) \
104 ({ \
105 unsigned char result; \
106 if (__PORT_PCIO((port))) \
107 __asm__ __volatile__( \
108 "ldrb %0, [%1, %2] @ inbc" \
109 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
110 else \
111 __asm__ __volatile__( \
112 "ldrb %0, [%1, #0] @ inbc" \
113 : "=r" (result) : "r" ((port))); \
114 result; \
115 })
116
117 #define __outwc(value,port) \
118 ({ \
119 unsigned long v = value; \
120 if (__PORT_PCIO((port))) \
121 __asm__ __volatile__( \
122 "strh %0, [%1, %2] @ outwc" \
123 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
124 else \
125 __asm__ __volatile__( \
126 "strh %0, [%1, #0] @ outwc" \
127 : : "r" (v), "r" ((port))); \
128 })
129
130 #define __inwc(port) \
131 ({ \
132 unsigned short result; \
133 if (__PORT_PCIO((port))) \
134 __asm__ __volatile__( \
135 "ldrh %0, [%1, %2] @ inwc" \
136 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
137 else \
138 __asm__ __volatile__( \
139 "ldrh %0, [%1, #0] @ inwc" \
140 : "=r" (result) : "r" ((port))); \
141 result; \
142 })
143
144 #define __outlc(value,port) \
145 ({ \
146 unsigned long v = value; \
147 if (__PORT_PCIO((port))) \
148 __asm__ __volatile__( \
149 "str %0, [%1, %2] @ outlc" \
150 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
151 else \
152 __asm__ __volatile__( \
153 "str %0, [%1, #0] @ outlc" \
154 : : "r" (v), "r" ((port))); \
155 })
156
157 #define __inlc(port) \
158 ({ \
159 unsigned long result; \
160 if (__PORT_PCIO((port))) \
161 __asm__ __volatile__( \
162 "ldr %0, [%1, %2] @ inlc" \
163 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \
164 else \
165 __asm__ __volatile__( \
166 "ldr %0, [%1, #0] @ inlc" \
167 : "=r" (result) : "r" ((port))); \
168 result; \
169 })
170
171 #define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
172
173 #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
174 #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
175 #define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
176 #define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
177 #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
178 #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
179 #define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p))
180 /* the following macro is deprecated */
181 #define ioaddr(port) __ioaddr((port))
182
183 #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
184 #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
185 #define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l)
186
187 #define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
188 #define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
189 #define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l)
190
191 /*
192 * 1:1 mapping for ioremapped regions.
193 */
194 #define __mem_pci(x) (x)
195
196 #endif
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