include/asm-arm/arch-s3c2410/regs-iis.h

   1 /* linux/include/asm/arch-s3c2410/regs-iis.h
   2  *
   3  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
   4  *                    http://www.simtec.co.uk/products/SWLINUX/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2410 IIS register definition
  11  *
  12  *  Changelog:
  13  *    19-06-2003     BJD     Created file
  14  *    26-06-2003     BJD     Finished off definitions for register addresses
  15  *    12-03-2004     BJD     Updated include protection
  16  *    07-03-2005     BJD     Added FIFO size flags and S3C2440 MPLL
  17  *    05-04-2005     LCVR    Added IISFCON definitions for the S3C2400
  18  *    18-07-2005     DA      Change IISCON_MPLL to IISMOD_MPLL
  19  *                           Correct IISMOD_256FS and IISMOD_384FS
  20  *                           Add IISCON_PSCEN
  21  */
  22
  23 #ifndef __ASM_ARCH_REGS_IIS_H
  24 #define __ASM_ARCH_REGS_IIS_H
  25
  26 #define S3C2410_IISCON   (0x00)
  27
  28 #define S3C2410_IISCON_LRINDEX    (1<<8)
  29 #define S3C2410_IISCON_TXFIFORDY  (1<<7)
  30 #define S3C2410_IISCON_RXFIFORDY  (1<<6)
  31 #define S3C2410_IISCON_TXDMAEN    (1<<5)
  32 #define S3C2410_IISCON_RXDMAEN    (1<<4)
  33 #define S3C2410_IISCON_TXIDLE     (1<<3)
  34 #define S3C2410_IISCON_RXIDLE     (1<<2)
  35 #define S3C2410_IISCON_PSCEN      (1<<1)
  36 #define S3C2410_IISCON_IISEN      (1<<0)
  37
  38 #define S3C2410_IISMOD   (0x04)
  39
  40 #define S3C2440_IISMOD_MPLL       (1<<9)
  41 #define S3C2410_IISMOD_SLAVE      (1<<8)
  42 #define S3C2410_IISMOD_NOXFER     (0<<6)
  43 #define S3C2410_IISMOD_RXMODE     (1<<6)
  44 #define S3C2410_IISMOD_TXMODE     (2<<6)
  45 #define S3C2410_IISMOD_TXRXMODE   (3<<6)
  46 #define S3C2410_IISMOD_LR_LLOW    (0<<5)
  47 #define S3C2410_IISMOD_LR_RLOW    (1<<5)
  48 #define S3C2410_IISMOD_IIS        (0<<4)
  49 #define S3C2410_IISMOD_MSB        (1<<4)
  50 #define S3C2410_IISMOD_8BIT       (0<<3)
  51 #define S3C2410_IISMOD_16BIT      (1<<3)
  52 #define S3C2410_IISMOD_BITMASK    (1<<3)
  53 #define S3C2410_IISMOD_256FS      (0<<2)
  54 #define S3C2410_IISMOD_384FS      (1<<2)
  55 #define S3C2410_IISMOD_16FS       (0<<0)
  56 #define S3C2410_IISMOD_32FS       (1<<0)
  57 #define S3C2410_IISMOD_48FS       (2<<0)
  58
  59 #define S3C2410_IISPSR          (0x08)
  60 #define S3C2410_IISPSR_INTMASK  (31<<5)
  61 #define S3C2410_IISPSR_INTSHIFT (5)
  62 #define S3C2410_IISPSR_EXTMASK  (31<<0)
  63 #define S3C2410_IISPSR_EXTSHFIT (0)
  64
  65 #define S3C2410_IISFCON  (0x0c)
  66
  67 #define S3C2410_IISFCON_TXDMA     (1<<15)
  68 #define S3C2410_IISFCON_RXDMA     (1<<14)
  69 #define S3C2410_IISFCON_TXENABLE  (1<<13)
  70 #define S3C2410_IISFCON_RXENABLE  (1<<12)
  71 #define S3C2410_IISFCON_TXMASK    (0x3f << 6)
  72 #define S3C2410_IISFCON_TXSHIFT   (6)
  73 #define S3C2410_IISFCON_RXMASK    (0x3f)
  74 #define S3C2410_IISFCON_RXSHIFT   (0)
  75
  76 #define S3C2400_IISFCON_TXDMA     (1<<11)
  77 #define S3C2400_IISFCON_RXDMA     (1<<10)
  78 #define S3C2400_IISFCON_TXENABLE  (1<<9)
  79 #define S3C2400_IISFCON_RXENABLE  (1<<8)
  80 #define S3C2400_IISFCON_TXMASK    (0x07 << 4)
  81 #define S3C2400_IISFCON_TXSHIFT   (4)
  82 #define S3C2400_IISFCON_RXMASK    (0x07)
  83 #define S3C2400_IISFCON_RXSHIFT   (0)
  84
  85 #define S3C2410_IISFIFO  (0x10)
  86 #endif /* __ASM_ARCH_REGS_IIS_H */