include/asm-arm/system.h

   1 #ifndef __ASM_ARM_SYSTEM_H
   2 #define __ASM_ARM_SYSTEM_H
   3
   4 #ifdef __KERNEL__
   5
   6 #include <linux/config.h>
   7
   8 #define CPU_ARCH_UNKNOWN        0
   9 #define CPU_ARCH_ARMv3          1
  10 #define CPU_ARCH_ARMv4          2
  11 #define CPU_ARCH_ARMv4T         3
  12 #define CPU_ARCH_ARMv5          4
  13 #define CPU_ARCH_ARMv5T         5
  14 #define CPU_ARCH_ARMv5TE        6
  15 #define CPU_ARCH_ARMv5TEJ       7
  16 #define CPU_ARCH_ARMv6          8
  17
  18 /*
  19  * CR1 bits (CP#15 CR1)
  20  */
  21 #define CR_M    (1 << 0)        /* MMU enable                           */
  22 #define CR_A    (1 << 1)        /* Alignment abort enable               */
  23 #define CR_C    (1 << 2)        /* Dcache enable                        */
  24 #define CR_W    (1 << 3)        /* Write buffer enable                  */
  25 #define CR_P    (1 << 4)        /* 32-bit exception handler             */
  26 #define CR_D    (1 << 5)        /* 32-bit data address range            */
  27 #define CR_L    (1 << 6)        /* Implementation defined               */
  28 #define CR_B    (1 << 7)        /* Big endian                           */
  29 #define CR_S    (1 << 8)        /* System MMU protection                */
  30 #define CR_R    (1 << 9)        /* ROM MMU protection                   */
  31 #define CR_F    (1 << 10)       /* Implementation defined               */
  32 #define CR_Z    (1 << 11)       /* Implementation defined               */
  33 #define CR_I    (1 << 12)       /* Icache enable                        */
  34 #define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
  35 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
  36 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
  37 #define CR_DT   (1 << 16)
  38 #define CR_IT   (1 << 18)
  39 #define CR_ST   (1 << 19)
  40 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
  41 #define CR_U    (1 << 22)       /* Unaligned access operation           */
  42 #define CR_XP   (1 << 23)       /* Extended page tables                 */
  43 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
  44
  45 #define CPUID_ID        0
  46 #define CPUID_CACHETYPE 1
  47 #define CPUID_TCM       2
  48 #define CPUID_TLBTYPE   3
  49
  50 #define read_cpuid(reg)                                                 \
  51         ({                                                              \
  52                 unsigned int __val;                                     \
  53                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
  54                     : "=r" (__val)                                      \
  55                     :                                                   \
  56                     : "cc");                                            \
  57                 __val;                                                  \
  58         })
  59
  60 /*
  61  * This is used to ensure the compiler did actually allocate the register we
  62  * asked it for some inline assembly sequences.  Apparently we can't trust
  63  * the compiler from one version to another so a bit of paranoia won't hurt.
  64  * This string is meant to be concatenated with the inline asm string and
  65  * will cause compilation to stop on mismatch.
  66  * (for details, see gcc PR 15089)
  67  */
  68 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
  69
  70 #ifndef __ASSEMBLY__
  71
  72 #include <linux/linkage.h>
  73
  74 struct thread_info;
  75 struct task_struct;
  76
  77 /* information about the system we're running on */
  78 extern unsigned int system_rev;
  79 extern unsigned int system_serial_low;
  80 extern unsigned int system_serial_high;
  81 extern unsigned int mem_fclk_21285;
  82
  83 struct pt_regs;
  84
  85 void die(const char *msg, struct pt_regs *regs, int err)
  86                 __attribute__((noreturn));
  87
  88 struct siginfo;
  89 void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
  90                 unsigned long err, unsigned long trap);
  91
  92 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  93                                        struct pt_regs *),
  94                      int sig, const char *name);
  95
  96 #include <asm/proc-fns.h>
  97
  98 #define xchg(ptr,x) \
  99         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 100
 101 #define tas(ptr) (xchg((ptr),1))
 102
 103 extern asmlinkage void __backtrace(void);
 104 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
 105 extern void show_pte(struct mm_struct *mm, unsigned long addr);
 106 extern void __show_regs(struct pt_regs *);
 107
 108 extern int cpu_architecture(void);
 109 extern void cpu_init(void);
 110
 111 #define set_cr(x)                                       \
 112         __asm__ __volatile__(                           \
 113         "mcr    p15, 0, %0, c1, c0, 0   @ set CR"       \
 114         : : "r" (x) : "cc")
 115
 116 #define get_cr()                                        \
 117         ({                                              \
 118         unsigned int __val;                             \
 119         __asm__ __volatile__(                           \
 120         "mrc    p15, 0, %0, c1, c0, 0   @ get CR"       \
 121         : "=r" (__val) : : "cc");                       \
 122         __val;                                          \
 123         })
 124
 125 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 126 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
 127
 128 #define UDBG_UNDEFINED  (1 << 0)
 129 #define UDBG_SYSCALL    (1 << 1)
 130 #define UDBG_BADABORT   (1 << 2)
 131 #define UDBG_SEGV       (1 << 3)
 132 #define UDBG_BUS        (1 << 4)
 133
 134 extern unsigned int user_debug;
 135
 136 #if __LINUX_ARM_ARCH__ >= 4
 137 #define vectors_high()  (cr_alignment & CR_V)
 138 #else
 139 #define vectors_high()  (0)
 140 #endif
 141
 142 #if __LINUX_ARM_ARCH__ >= 6
 143 #define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
 144                                    : : "r" (0) : "memory")
 145 #else
 146 #define mb() __asm__ __volatile__ ("" : : : "memory")
 147 #endif
 148 #define rmb() mb()
 149 #define wmb() mb()
 150 #define read_barrier_depends() do { } while(0)
 151 #define set_mb(var, value)  do { var = value; mb(); } while (0)
 152 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
 153 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
 154
 155 /*
 156  * switch_mm() may do a full cache flush over the context switch,
 157  * so enable interrupts over the context switch to avoid high
 158  * latency.
 159  */
 160 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
 161
 162 /*
 163  * switch_to(prev, next) should switch from task `prev' to `next'
 164  * `prev' will never be the same as `next'.  schedule() itself
 165  * contains the memory barrier to tell GCC not to cache `current'.
 166  */
 167 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
 168
 169 #define switch_to(prev,next,last)                                       \
 170 do {                                                                    \
 171         last = __switch_to(prev,prev->thread_info,next->thread_info);   \
 172 } while (0)
 173
 174 /*
 175  * CPU interrupt mask handling.
 176  */
 177 #if __LINUX_ARM_ARCH__ >= 6
 178
 179 #define local_irq_save(x)                                       \
 180         ({                                                      \
 181         __asm__ __volatile__(                                   \
 182         "mrs    %0, cpsr                @ local_irq_save\n"     \
 183         "cpsid  i"                                              \
 184         : "=r" (x) : : "memory", "cc");                         \
 185         })
 186
 187 #define local_irq_enable()  __asm__("cpsie i    @ __sti" : : : "memory", "cc")
 188 #define local_irq_disable() __asm__("cpsid i    @ __cli" : : : "memory", "cc")
 189 #define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
 190 #define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
 191
 192 #else
 193
 194 /*
 195  * Save the current interrupt enable state & disable IRQs
 196  */
 197 #define local_irq_save(x)                                       \
 198         ({                                                      \
 199                 unsigned long temp;                             \
 200                 (void) (&temp == &x);                           \
 201         __asm__ __volatile__(                                   \
 202         "mrs    %0, cpsr                @ local_irq_save\n"     \
 203 "       orr     %1, %0, #128\n"                                 \
 204 "       msr     cpsr_c, %1"                                     \
 205         : "=r" (x), "=r" (temp)                                 \
 206         :                                                       \
 207         : "memory", "cc");                                      \
 208         })
 209
 210 /*
 211  * Enable IRQs
 212  */
 213 #define local_irq_enable()                                      \
 214         ({                                                      \
 215                 unsigned long temp;                             \
 216         __asm__ __volatile__(                                   \
 217         "mrs    %0, cpsr                @ local_irq_enable\n"   \
 218 "       bic     %0, %0, #128\n"                                 \
 219 "       msr     cpsr_c, %0"                                     \
 220         : "=r" (temp)                                           \
 221         :                                                       \
 222         : "memory", "cc");                                      \
 223         })
 224
 225 /*
 226  * Disable IRQs
 227  */
 228 #define local_irq_disable()                                     \
 229         ({                                                      \
 230                 unsigned long temp;                             \
 231         __asm__ __volatile__(                                   \
 232         "mrs    %0, cpsr                @ local_irq_disable\n"  \
 233 "       orr     %0, %0, #128\n"                                 \
 234 "       msr     cpsr_c, %0"                                     \
 235         : "=r" (temp)                                           \
 236         :                                                       \
 237         : "memory", "cc");                                      \
 238         })
 239
 240 /*
 241  * Enable FIQs
 242  */
 243 #define local_fiq_enable()                                      \
 244         ({                                                      \
 245                 unsigned long temp;                             \
 246         __asm__ __volatile__(                                   \
 247         "mrs    %0, cpsr                @ stf\n"                \
 248 "       bic     %0, %0, #64\n"                                  \
 249 "       msr     cpsr_c, %0"                                     \
 250         : "=r" (temp)                                           \
 251         :                                                       \
 252         : "memory", "cc");                                      \
 253         })
 254
 255 /*
 256  * Disable FIQs
 257  */
 258 #define local_fiq_disable()                                     \
 259         ({                                                      \
 260                 unsigned long temp;                             \
 261         __asm__ __volatile__(                                   \
 262         "mrs    %0, cpsr                @ clf\n"                \
 263 "       orr     %0, %0, #64\n"                                  \
 264 "       msr     cpsr_c, %0"                                     \
 265         : "=r" (temp)                                           \
 266         :                                                       \
 267         : "memory", "cc");                                      \
 268         })
 269
 270 #endif
 271
 272 /*
 273  * Save the current interrupt enable state.
 274  */
 275 #define local_save_flags(x)                                     \
 276         ({                                                      \
 277         __asm__ __volatile__(                                   \
 278         "mrs    %0, cpsr                @ local_save_flags"     \
 279         : "=r" (x) : : "memory", "cc");                         \
 280         })
 281
 282 /*
 283  * restore saved IRQ & FIQ state
 284  */
 285 #define local_irq_restore(x)                                    \
 286         __asm__ __volatile__(                                   \
 287         "msr    cpsr_c, %0              @ local_irq_restore\n"  \
 288         :                                                       \
 289         : "r" (x)                                               \
 290         : "memory", "cc")
 291
 292 #define irqs_disabled()                 \
 293 ({                                      \
 294         unsigned long flags;            \
 295         local_save_flags(flags);        \
 296         (int)(flags & PSR_I_BIT);       \
 297 })
 298
 299 #ifdef CONFIG_SMP
 300
 301 #define smp_mb()                mb()
 302 #define smp_rmb()               rmb()
 303 #define smp_wmb()               wmb()
 304 #define smp_read_barrier_depends()              read_barrier_depends()
 305
 306 #else
 307
 308 #define smp_mb()                barrier()
 309 #define smp_rmb()               barrier()
 310 #define smp_wmb()               barrier()
 311 #define smp_read_barrier_depends()              do { } while(0)
 312
 313 #endif /* CONFIG_SMP */
 314
 315 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 316 /*
 317  * On the StrongARM, "swp" is terminally broken since it bypasses the
 318  * cache totally.  This means that the cache becomes inconsistent, and,
 319  * since we use normal loads/stores as well, this is really bad.
 320  * Typically, this causes oopsen in filp_close, but could have other,
 321  * more disasterous effects.  There are two work-arounds:
 322  *  1. Disable interrupts and emulate the atomic swap
 323  *  2. Clean the cache, perform atomic swap, flush the cache
 324  *
 325  * We choose (1) since its the "easiest" to achieve here and is not
 326  * dependent on the processor type.
 327  *
 328  * NOTE that this solution won't work on an SMP system, so explcitly
 329  * forbid it here.
 330  */
 331 #define swp_is_buggy
 332 #endif
 333
 334 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 335 {
 336         extern void __bad_xchg(volatile void *, int);
 337         unsigned long ret;
 338 #ifdef swp_is_buggy
 339         unsigned long flags;
 340 #endif
 341 #if __LINUX_ARM_ARCH__ >= 6
 342         unsigned int tmp;
 343 #endif
 344
 345         switch (size) {
 346 #if __LINUX_ARM_ARCH__ >= 6
 347         case 1:
 348                 asm volatile("@ __xchg1\n"
 349                 "1:     ldrexb  %0, [%3]\n"
 350                 "       strexb  %1, %2, [%3]\n"
 351                 "       teq     %1, #0\n"
 352                 "       bne     1b"
 353                         : "=&r" (ret), "=&r" (tmp)
 354                         : "r" (x), "r" (ptr)
 355                         : "memory", "cc");
 356                 break;
 357         case 4:
 358                 asm volatile("@ __xchg4\n"
 359                 "1:     ldrex   %0, [%3]\n"
 360                 "       strex   %1, %2, [%3]\n"
 361                 "       teq     %1, #0\n"
 362                 "       bne     1b"
 363                         : "=&r" (ret), "=&r" (tmp)
 364                         : "r" (x), "r" (ptr)
 365                         : "memory", "cc");
 366                 break;
 367 #elif defined(swp_is_buggy)
 368 #ifdef CONFIG_SMP
 369 #error SMP is not supported on this platform
 370 #endif
 371         case 1:
 372                 local_irq_save(flags);
 373                 ret = *(volatile unsigned char *)ptr;
 374                 *(volatile unsigned char *)ptr = x;
 375                 local_irq_restore(flags);
 376                 break;
 377
 378         case 4:
 379                 local_irq_save(flags);
 380                 ret = *(volatile unsigned long *)ptr;
 381                 *(volatile unsigned long *)ptr = x;
 382                 local_irq_restore(flags);
 383                 break;
 384 #else
 385         case 1:
 386                 asm volatile("@ __xchg1\n"
 387                 "       swpb    %0, %1, [%2]"
 388                         : "=&r" (ret)
 389                         : "r" (x), "r" (ptr)
 390                         : "memory", "cc");
 391                 break;
 392         case 4:
 393                 asm volatile("@ __xchg4\n"
 394                 "       swp     %0, %1, [%2]"
 395                         : "=&r" (ret)
 396                         : "r" (x), "r" (ptr)
 397                         : "memory", "cc");
 398                 break;
 399 #endif
 400         default:
 401                 __bad_xchg(ptr, size), ret = 0;
 402                 break;
 403         }
 404
 405         return ret;
 406 }
 407
 408 #endif /* __ASSEMBLY__ */
 409
 410 #define arch_align_stack(x) (x)
 411
 412 #endif /* __KERNEL__ */
 413
 414 #endif