include/asm-mips/cpu-features.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003, 2004 Ralf Baechle
   7  */
   8 #ifndef __ASM_CPU_FEATURES_H
   9 #define __ASM_CPU_FEATURES_H
  10
  11 #include <linux/config.h>
  12
  13 #include <asm/cpu.h>
  14 #include <asm/cpu-info.h>
  15 #include <cpu-feature-overrides.h>
  16
  17 /*
  18  * SMP assumption: Options of CPU 0 are a superset of all processors.
  19  * This is true for all known MIPS systems.
  20  */
  21 #ifndef cpu_has_tlb
  22 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
  23 #endif
  24 #ifndef cpu_has_4kex
  25 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
  26 #endif
  27 #ifndef cpu_has_4ktlb
  28 #define cpu_has_4ktlb           (cpu_data[0].options & MIPS_CPU_4KTLB)
  29 #endif
  30 #ifndef cpu_has_fpu
  31 #define cpu_has_fpu             (cpu_data[0].options & MIPS_CPU_FPU)
  32 #endif
  33 #ifndef cpu_has_32fpr
  34 #define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
  35 #endif
  36 #ifndef cpu_has_counter
  37 #define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
  38 #endif
  39 #ifndef cpu_has_watch
  40 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
  41 #endif
  42 #ifndef cpu_has_mips16
  43 #define cpu_has_mips16          (cpu_data[0].options & MIPS_CPU_MIPS16)
  44 #endif
  45 #ifndef cpu_has_divec
  46 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
  47 #endif
  48 #ifndef cpu_has_vce
  49 #define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
  50 #endif
  51 #ifndef cpu_has_cache_cdex_p
  52 #define cpu_has_cache_cdex_p    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
  53 #endif
  54 #ifndef cpu_has_cache_cdex_s
  55 #define cpu_has_cache_cdex_s    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
  56 #endif
  57 #ifndef cpu_has_prefetch
  58 #define cpu_has_prefetch        (cpu_data[0].options & MIPS_CPU_PREFETCH)
  59 #endif
  60 #ifndef cpu_has_mcheck
  61 #define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
  62 #endif
  63 #ifndef cpu_has_ejtag
  64 #define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
  65 #endif
  66 #ifndef cpu_has_llsc
  67 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
  68 #endif
  69 #ifndef cpu_has_vtag_icache
  70 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
  71 #endif
  72 #ifndef cpu_has_dc_aliases
  73 #define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
  74 #endif
  75 #ifndef cpu_has_ic_fills_f_dc
  76 #define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
  77 #endif
  78
  79 /*
  80  * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
  81  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
  82  * don't.  For maintaining I-cache coherency this means we need to flush the
  83  * D-cache all the way back to whever the I-cache does refills from, so the
  84  * I-cache has a chance to see the new data at all.  Then we have to flush the
  85  * I-cache also.
  86  * Note we may have been rescheduled and may no longer be running on the CPU
  87  * that did the store so we can't optimize this into only doing the flush on
  88  * the local CPU.
  89  */
  90 #ifndef cpu_icache_snoops_remote_store
  91 #ifdef CONFIG_SMP
  92 #define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
  93 #else
  94 #define cpu_icache_snoops_remote_store  1
  95 #endif
  96 #endif
  97
  98 /*
  99  * Certain CPUs may throw bizarre exceptions if not the whole cacheline
 100  * contains valid instructions.  For these we ensure proper alignment of
 101  * signal trampolines and pad them to the size of a full cache lines with
 102  * nops.  This is also used in structure definitions so can't be a test macro
 103  * like the others.
 104  */
 105 #ifndef PLAT_TRAMPOLINE_STUFF_LINE
 106 #define PLAT_TRAMPOLINE_STUFF_LINE      0UL
 107 #endif
 108
 109 #ifdef CONFIG_32BIT
 110 # ifndef cpu_has_nofpuex
 111 # define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
 112 # endif
 113 # ifndef cpu_has_64bits
 114 # define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 115 # endif
 116 # ifndef cpu_has_64bit_zero_reg
 117 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 118 # endif
 119 # ifndef cpu_has_64bit_gp_regs
 120 # define cpu_has_64bit_gp_regs          0
 121 # endif
 122 # ifndef cpu_has_64bit_addresses
 123 # define cpu_has_64bit_addresses        0
 124 # endif
 125 #endif
 126
 127 #ifdef CONFIG_64BIT
 128 # ifndef cpu_has_nofpuex
 129 # define cpu_has_nofpuex                0
 130 # endif
 131 # ifndef cpu_has_64bits
 132 # define cpu_has_64bits                 1
 133 # endif
 134 # ifndef cpu_has_64bit_zero_reg
 135 # define cpu_has_64bit_zero_reg         1
 136 # endif
 137 # ifndef cpu_has_64bit_gp_regs
 138 # define cpu_has_64bit_gp_regs          1
 139 # endif
 140 # ifndef cpu_has_64bit_addresses
 141 # define cpu_has_64bit_addresses        1
 142 # endif
 143 #endif
 144
 145 #ifndef cpu_has_subset_pcaches
 146 #define cpu_has_subset_pcaches  (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
 147 #endif
 148
 149 #ifndef cpu_dcache_line_size
 150 #define cpu_dcache_line_size()  current_cpu_data.dcache.linesz
 151 #endif
 152 #ifndef cpu_icache_line_size
 153 #define cpu_icache_line_size()  current_cpu_data.icache.linesz
 154 #endif
 155 #ifndef cpu_scache_line_size
 156 #define cpu_scache_line_size()  current_cpu_data.scache.linesz
 157 #endif
 158
 159 #endif /* __ASM_CPU_FEATURES_H */