include/asm-mips/sn/sn0/hubmd.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
   7  *
   8  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
   9  * Copyright (C) 1999 by Ralf Baechle
  10  */
  11 #ifndef _ASM_SN_SN0_HUBMD_H
  12 #define _ASM_SN_SN0_HUBMD_H
  13
  14 #include <linux/config.h>
  15
  16 /*
  17  * Hub Memory/Directory interface registers
  18  */
  19 #define CACHE_SLINE_SIZE        128     /* Secondary cache line size on SN0 */
  20
  21 #define MAX_REGIONS             64
  22
  23 /* Hardware page size and shift */
  24
  25 #define MD_PAGE_SIZE            4096     /* Page size in bytes              */
  26 #define MD_PAGE_NUM_SHFT        12       /* Address to page number shift    */
  27
  28 /* Register offsets from LOCAL_HUB or REMOTE_HUB */
  29
  30 #define MD_BASE                 0x200000
  31 #define MD_BASE_PERF            0x210000
  32 #define MD_BASE_JUNK            0x220000
  33
  34 #define MD_IO_PROTECT           0x200000 /* MD and core register protection */
  35 #define MD_IO_PROT_OVRRD        0x200008 /* Clear my bit in MD_IO_PROTECT   */
  36 #define MD_HSPEC_PROTECT        0x200010 /* BDDIR, LBOOT, RBOOT protection  */
  37 #define MD_MEMORY_CONFIG        0x200018 /* Memory/Directory DIMM control   */
  38 #define MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
  39 #define MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
  40 #define MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
  41 #define MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
  42 #define MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
  43 #define MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
  44 #define MD_DIR_ERROR            0x200050 /* Directory DIMM error            */
  45 #define MD_DIR_ERROR_CLR        0x200058 /* Directory DIMM error clear      */
  46 #define MD_PROTOCOL_ERROR       0x200060 /* Directory protocol error        */
  47 #define MD_PROTOCOL_ERROR_CLR   0x200068 /* Directory protocol error clear  */
  48 #define MD_MEM_ERROR            0x200070 /* Memory DIMM error               */
  49 #define MD_MEM_ERROR_CLR        0x200078 /* Memory DIMM error clear         */
  50 #define MD_MISC_ERROR           0x200080 /* Miscellaneous MD error          */
  51 #define MD_MISC_ERROR_CLR       0x200088 /* Miscellaneous MD error clear    */
  52 #define MD_MEM_DIMM_INIT        0x200090 /* Memory DIMM mode initization.   */
  53 #define MD_DIR_DIMM_INIT        0x200098 /* Directory DIMM mode init.       */
  54 #define MD_MOQ_SIZE             0x2000a0 /* MD outgoing queue size          */
  55 #define MD_MLAN_CTL             0x2000a8 /* NIC (Microlan) control register */
  56
  57 #define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
  58 #define MD_PERF_CNT0            0x210010 /* Performance counter 0           */
  59 #define MD_PERF_CNT1            0x210018 /* Performance counter 1           */
  60 #define MD_PERF_CNT2            0x210020 /* Performance counter 2           */
  61 #define MD_PERF_CNT3            0x210028 /* Performance counter 3           */
  62 #define MD_PERF_CNT4            0x210030 /* Performance counter 4           */
  63 #define MD_PERF_CNT5            0x210038 /* Performance counter 5           */
  64
  65 #define MD_UREG0_0              0x220000 /* uController/UART 0 register     */
  66 #define MD_UREG0_1              0x220008 /* uController/UART 0 register     */
  67 #define MD_UREG0_2              0x220010 /* uController/UART 0 register     */
  68 #define MD_UREG0_3              0x220018 /* uController/UART 0 register     */
  69 #define MD_UREG0_4              0x220020 /* uController/UART 0 register     */
  70 #define MD_UREG0_5              0x220028 /* uController/UART 0 register     */
  71 #define MD_UREG0_6              0x220030 /* uController/UART 0 register     */
  72 #define MD_UREG0_7              0x220038 /* uController/UART 0 register     */
  73
  74 #define MD_SLOTID_USTAT         0x220048 /* Hub slot ID & UART/uCtlr status */
  75 #define MD_LED0                 0x220050 /* Eight-bit LED for CPU A         */
  76 #define MD_LED1                 0x220058 /* Eight-bit LED for CPU B         */
  77
  78 #define MD_UREG1_0              0x220080 /* uController/UART 1 register     */
  79 #define MD_UREG1_1              0x220088 /* uController/UART 1 register     */
  80 #define MD_UREG1_2              0x220090 /* uController/UART 1 register     */
  81 #define MD_UREG1_3              0x220098 /* uController/UART 1 register     */
  82 #define MD_UREG1_4              0x2200a0 /* uController/UART 1 register     */
  83 #define MD_UREG1_5              0x2200a8 /* uController/UART 1 register     */
  84 #define MD_UREG1_6              0x2200b0 /* uController/UART 1 register     */
  85 #define MD_UREG1_7              0x2200b8 /* uController/UART 1 register     */
  86 #define MD_UREG1_8              0x2200c0 /* uController/UART 1 register     */
  87 #define MD_UREG1_9              0x2200c8 /* uController/UART 1 register     */
  88 #define MD_UREG1_10             0x2200d0 /* uController/UART 1 register     */
  89 #define MD_UREG1_11             0x2200d8 /* uController/UART 1 register     */
  90 #define MD_UREG1_12             0x2200e0 /* uController/UART 1 register     */
  91 #define MD_UREG1_13             0x2200e8 /* uController/UART 1 register     */
  92 #define MD_UREG1_14             0x2200f0 /* uController/UART 1 register     */
  93 #define MD_UREG1_15             0x2200f8 /* uController/UART 1 register     */
  94
  95 #ifdef CONFIG_SGI_SN0_N_MODE
  96 #define MD_MEM_BANKS            4        /* 4 banks of memory max in N mode */
  97 #else
  98 #define MD_MEM_BANKS            8        /* 8 banks of memory max in M mode */
  99 #endif
 100
 101 /*
 102  * MD_MEMORY_CONFIG fields
 103  *
 104  *   MD_SIZE_xxx are useful for representing the size of a SIMM or bank
 105  *   (SIMM pair).  They correspond to the values needed for the bit
 106  *   triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
 107  *   Bits not used by the MD are used by software.
 108  */
 109
 110 #define MD_SIZE_EMPTY           0       /* Valid in MEMORY_CONFIG           */
 111 #define MD_SIZE_8MB             1
 112 #define MD_SIZE_16MB            2
 113 #define MD_SIZE_32MB            3       /* Broken in Hub 1                  */
 114 #define MD_SIZE_64MB            4       /* Valid in MEMORY_CONFIG           */
 115 #define MD_SIZE_128MB           5       /* Valid in MEMORY_CONFIG           */
 116 #define MD_SIZE_256MB           6
 117 #define MD_SIZE_512MB           7       /* Valid in MEMORY_CONFIG           */
 118 #define MD_SIZE_1GB             8
 119 #define MD_SIZE_2GB             9
 120 #define MD_SIZE_4GB             10
 121
 122 #define MD_SIZE_BYTES(size)     ((size) == 0 ? 0 : 0x400000L << (size))
 123 #define MD_SIZE_MBYTES(size)    ((size) == 0 ? 0 :   4       << (size))
 124
 125 #define MMC_FPROM_CYC_SHFT      49      /* Have to use UINT64_CAST, instead */
 126 #define MMC_FPROM_CYC_MASK      (UINT64_CAST 31 << 49)  /* of 'L' suffix,   */
 127 #define MMC_FPROM_WR_SHFT       44                      /* for assembler    */
 128 #define MMC_FPROM_WR_MASK       (UINT64_CAST 31 << 44)
 129 #define MMC_UCTLR_CYC_SHFT      39
 130 #define MMC_UCTLR_CYC_MASK      (UINT64_CAST 31 << 39)
 131 #define MMC_UCTLR_WR_SHFT       34
 132 #define MMC_UCTLR_WR_MASK       (UINT64_CAST 31 << 34)
 133 #define MMC_DIMM0_SEL_SHFT      32
 134 #define MMC_DIMM0_SEL_MASK      (UINT64_CAST 3 << 32)
 135 #define MMC_IO_PROT_EN_SHFT     31
 136 #define MMC_IO_PROT_EN_MASK     (UINT64_CAST 1 << 31)
 137 #define MMC_IO_PROT             (UINT64_CAST 1 << 31)
 138 #define MMC_ARB_MLSS_SHFT       30
 139 #define MMC_ARB_MLSS_MASK       (UINT64_CAST 1 << 30)
 140 #define MMC_ARB_MLSS            (UINT64_CAST 1 << 30)
 141 #define MMC_IGNORE_ECC_SHFT     29
 142 #define MMC_IGNORE_ECC_MASK     (UINT64_CAST 1 << 29)
 143 #define MMC_IGNORE_ECC          (UINT64_CAST 1 << 29)
 144 #define MMC_DIR_PREMIUM_SHFT    28
 145 #define MMC_DIR_PREMIUM_MASK    (UINT64_CAST 1 << 28)
 146 #define MMC_DIR_PREMIUM         (UINT64_CAST 1 << 28)
 147 #define MMC_REPLY_GUAR_SHFT     24
 148 #define MMC_REPLY_GUAR_MASK     (UINT64_CAST 15 << 24)
 149 #define MMC_BANK_SHFT(_b)       ((_b) * 3)
 150 #define MMC_BANK_MASK(_b)       (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
 151 #define MMC_BANK_ALL_MASK       0xffffff
 152 #define MMC_RESET_DEFAULTS      (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
 153                                  UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
 154                                  UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
 155                                  UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
 156                                  MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
 157                                  UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
 158                                  MMC_BANK_ALL_MASK)
 159
 160 /* MD_REFRESH_CONTROL fields */
 161
 162 #define MRC_ENABLE_SHFT         63
 163 #define MRC_ENABLE_MASK         (UINT64_CAST 1 << 63)
 164 #define MRC_ENABLE              (UINT64_CAST 1 << 63)
 165 #define MRC_COUNTER_SHFT        12
 166 #define MRC_COUNTER_MASK        (UINT64_CAST 0xfff << 12)
 167 #define MRC_CNT_THRESH_MASK     0xfff
 168 #define MRC_RESET_DEFAULTS      (UINT64_CAST 0x400)
 169
 170 /* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
 171
 172 #define MDI_SELECT_SHFT         32
 173 #define MDI_SELECT_MASK         (UINT64_CAST 0x0f << 32)
 174 #define MDI_DIMM_MODE_MASK      (UINT64_CAST 0xfff)
 175
 176 /* MD_MOQ_SIZE fields */
 177
 178 #define MMS_RP_SIZE_SHFT        8
 179 #define MMS_RP_SIZE_MASK        (UINT64_CAST 0x3f << 8)
 180 #define MMS_RQ_SIZE_SHFT        0
 181 #define MMS_RQ_SIZE_MASK        (UINT64_CAST 0x1f)
 182 #define MMS_RESET_DEFAULTS      (0x32 << 8 | 0x12)
 183
 184 /* MD_FANDOP_CAC_STAT fields */
 185
 186 #define MFC_VALID_SHFT          63
 187 #define MFC_VALID_MASK          (UINT64_CAST 1 << 63)
 188 #define MFC_VALID               (UINT64_CAST 1 << 63)
 189 #define MFC_ADDR_SHFT           6
 190 #define MFC_ADDR_MASK           (UINT64_CAST 0x3ffffff)
 191
 192 /* MD_MLAN_CTL fields */
 193
 194 #define MLAN_PHI1_SHFT          27
 195 #define MLAN_PHI1_MASK          (UINT64_CAST 0x7f << 27)
 196 #define MLAN_PHI0_SHFT          20
 197 #define MLAN_PHI0_MASK          (UINT64_CAST 0x7f << 27)
 198 #define MLAN_PULSE_SHFT         10
 199 #define MLAN_PULSE_MASK         (UINT64_CAST 0x3ff << 10)
 200 #define MLAN_SAMPLE_SHFT        2
 201 #define MLAN_SAMPLE_MASK        (UINT64_CAST 0xff << 2)
 202 #define MLAN_DONE_SHFT          1
 203 #define MLAN_DONE_MASK          2
 204 #define MLAN_DONE               (UINT64_CAST 0x02)
 205 #define MLAN_RD_DATA            (UINT64_CAST 0x01)
 206 #define MLAN_RESET_DEFAULTS     (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
 207                                  UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
 208
 209 /* MD_SLOTID_USTAT bit definitions */
 210
 211 #define MSU_CORECLK_TST_SHFT    7       /* You don't wanna know             */
 212 #define MSU_CORECLK_TST_MASK    (UINT64_CAST 1 << 7)
 213 #define MSU_CORECLK_TST         (UINT64_CAST 1 << 7)
 214 #define MSU_CORECLK_SHFT        6       /* You don't wanna know             */
 215 #define MSU_CORECLK_MASK        (UINT64_CAST 1 << 6)
 216 #define MSU_CORECLK             (UINT64_CAST 1 << 6)
 217 #define MSU_NETSYNC_SHFT        5       /* You don't wanna know             */
 218 #define MSU_NETSYNC_MASK        (UINT64_CAST 1 << 5)
 219 #define MSU_NETSYNC             (UINT64_CAST 1 << 5)
 220 #define MSU_FPROMRDY_SHFT       4       /* Flash PROM ready bit             */
 221 #define MSU_FPROMRDY_MASK       (UINT64_CAST 1 << 4)
 222 #define MSU_FPROMRDY            (UINT64_CAST 1 << 4)
 223 #define MSU_I2CINTR_SHFT                3       /* I2C interrupt bit   */
 224 #define MSU_I2CINTR_MASK                (UINT64_CAST 1 << 3)
 225 #define MSU_I2CINTR             (UINT64_CAST 1 << 3)
 226 #define MSU_SLOTID_MASK         0xff
 227 #define MSU_SN0_SLOTID_SHFT     0       /* Slot ID                          */
 228 #define MSU_SN0_SLOTID_MASK     (UINT64_CAST 7)
 229 #define MSU_SN00_SLOTID_SHFT    7
 230 #define MSU_SN00_SLOTID_MASK    (UINT64_CAST 0x80)
 231
 232 #define MSU_PIMM_PSC_SHFT       4
 233 #define MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
 234
 235 /* MD_MIG_DIFF_THRESH bit definitions */
 236
 237 #define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
 238 #define MD_MIG_DIFF_THRES_VALID_SHFT 63
 239 #define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
 240
 241 /* MD_MIG_VALUE_THRESH bit definitions */
 242
 243 #define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
 244 #define MD_MIG_VALUE_THRES_VALID_SHFT 63
 245 #define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
 246
 247 /* MD_MIG_CANDIDATE bit definitions */
 248
 249 #define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
 250 #define MD_MIG_CANDIDATE_VALID_SHFT 63
 251 #define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
 252 #define MD_MIG_CANDIDATE_TYPE_SHFT 30
 253 #define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
 254 #define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
 255 #define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
 256 #define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
 257 #define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
 258 #define MD_MIG_CANDIDATE_NODEID_SHFT 20
 259 #define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
 260 #define MD_MIG_CANDIDATE_ADDR_SHFT 14  /* The address starts at bit 14 */
 261
 262 /* Other MD definitions */
 263
 264 #define MD_BANK_SHFT            29                      /* log2(512 MB)     */
 265 #define MD_BANK_MASK            (UINT64_CAST 7 << 29)
 266 #define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
 267 #define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
 268
 269 /*
 270  * The following definitions cover the bit field definitions for the
 271  * various MD registers.  For multi-bit registers, we define both
 272  * a shift amount and a mask value.  By convention, if you want to
 273  * isolate a field, you should mask the field and then shift it down,
 274  * since this makes the masks useful without a shift.
 275  */
 276
 277 /* Directory entry states for both premium and standard SIMMs. */
 278
 279 #define MD_DIR_SHARED           (UINT64_CAST 0x0)       /* 000 */
 280 #define MD_DIR_POISONED         (UINT64_CAST 0x1)       /* 001 */
 281 #define MD_DIR_EXCLUSIVE        (UINT64_CAST 0x2)       /* 010 */
 282 #define MD_DIR_BUSY_SHARED      (UINT64_CAST 0x3)       /* 011 */
 283 #define MD_DIR_BUSY_EXCL        (UINT64_CAST 0x4)       /* 100 */
 284 #define MD_DIR_WAIT             (UINT64_CAST 0x5)       /* 101 */
 285 #define MD_DIR_UNOWNED          (UINT64_CAST 0x7)       /* 111 */
 286
 287 /*
 288  * The MD_DIR_FORCE_ECC bit can be added directory entry write data
 289  * to forcing the ECC to be written as-is instead of recalculated.
 290  */
 291
 292 #define MD_DIR_FORCE_ECC        (UINT64_CAST 1 << 63)
 293
 294 /*
 295  * Premium SIMM directory entry shifts and masks.  Each is valid only in the
 296  * context(s) indicated, where A, B, and C indicate the directory entry format
 297  * as shown, and low and/or high indicates which double-word of the entry.
 298  *
 299  * Format A:  STATE = shared, FINE = 1
 300  * Format B:  STATE = shared, FINE = 0
 301  * Format C:  STATE != shared (FINE must be 0)
 302  */
 303
 304 #define MD_PDIR_MASK            0xffffffffffff          /* Whole entry      */
 305 #define MD_PDIR_ECC_SHFT        0                       /* ABC low or high  */
 306 #define MD_PDIR_ECC_MASK        0x7f
 307 #define MD_PDIR_PRIO_SHFT       8                       /* ABC low          */
 308 #define MD_PDIR_PRIO_MASK       (0xf << 8)
 309 #define MD_PDIR_AX_SHFT         7                       /* ABC low          */
 310 #define MD_PDIR_AX_MASK         (1 << 7)
 311 #define MD_PDIR_AX              (1 << 7)
 312 #define MD_PDIR_FINE_SHFT       12                      /* ABC low          */
 313 #define MD_PDIR_FINE_MASK       (1 << 12)
 314 #define MD_PDIR_FINE            (1 << 12)
 315 #define MD_PDIR_OCT_SHFT        13                      /* A low            */
 316 #define MD_PDIR_OCT_MASK        (7 << 13)
 317 #define MD_PDIR_STATE_SHFT      13                      /* BC low           */
 318 #define MD_PDIR_STATE_MASK      (7 << 13)
 319 #define MD_PDIR_ONECNT_SHFT     16                      /* BC low           */
 320 #define MD_PDIR_ONECNT_MASK     (0x3f << 16)
 321 #define MD_PDIR_PTR_SHFT        22                      /* C low            */
 322 #define MD_PDIR_PTR_MASK        (UINT64_CAST 0x7ff << 22)
 323 #define MD_PDIR_VECMSB_SHFT     22                      /* AB low           */
 324 #define MD_PDIR_VECMSB_BITMASK  0x3ffffff
 325 #define MD_PDIR_VECMSB_BITSHFT  27
 326 #define MD_PDIR_VECMSB_MASK     (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
 327 #define MD_PDIR_CWOFF_SHFT      7                       /* C high           */
 328 #define MD_PDIR_CWOFF_MASK      (7 << 7)
 329 #define MD_PDIR_VECLSB_SHFT     10                      /* AB high          */
 330 #define MD_PDIR_VECLSB_BITMASK  (UINT64_CAST 0x3fffffffff)
 331 #define MD_PDIR_VECLSB_BITSHFT  0
 332 #define MD_PDIR_VECLSB_MASK     (MD_PDIR_VECLSB_BITMASK << 10)
 333
 334 /*
 335  * Directory initialization values
 336  */
 337
 338 #define MD_PDIR_INIT_LO         (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
 339                                  MD_PDIR_AX)
 340 #define MD_PDIR_INIT_HI         0
 341 #define MD_PDIR_INIT_PROT       (MD_PROT_RW << MD_PPROT_IO_SHFT | \
 342                                  MD_PROT_RW << MD_PPROT_SHFT)
 343
 344 /*
 345  * Standard SIMM directory entry shifts and masks.  Each is valid only in the
 346  * context(s) indicated, where A and C indicate the directory entry format
 347  * as shown, and low and/or high indicates which double-word of the entry.
 348  *
 349  * Format A:  STATE == shared
 350  * Format C:  STATE != shared
 351  */
 352
 353 #define MD_SDIR_MASK            0xffff                  /* Whole entry      */
 354 #define MD_SDIR_ECC_SHFT        0                       /* AC low or high   */
 355 #define MD_SDIR_ECC_MASK        0x1f
 356 #define MD_SDIR_PRIO_SHFT       6                       /* AC low           */
 357 #define MD_SDIR_PRIO_MASK       (1 << 6)
 358 #define MD_SDIR_AX_SHFT         5                       /* AC low           */
 359 #define MD_SDIR_AX_MASK         (1 << 5)
 360 #define MD_SDIR_AX              (1 << 5)
 361 #define MD_SDIR_STATE_SHFT      7                       /* AC low           */
 362 #define MD_SDIR_STATE_MASK      (7 << 7)
 363 #define MD_SDIR_PTR_SHFT        10                      /* C low            */
 364 #define MD_SDIR_PTR_MASK        (0x3f << 10)
 365 #define MD_SDIR_CWOFF_SHFT      5                       /* C high           */
 366 #define MD_SDIR_CWOFF_MASK      (7 << 5)
 367 #define MD_SDIR_VECMSB_SHFT     11                      /* A low            */
 368 #define MD_SDIR_VECMSB_BITMASK  0x1f
 369 #define MD_SDIR_VECMSB_BITSHFT  7
 370 #define MD_SDIR_VECMSB_MASK     (MD_SDIR_VECMSB_BITMASK << 11)
 371 #define MD_SDIR_VECLSB_SHFT     5                       /* A high           */
 372 #define MD_SDIR_VECLSB_BITMASK  0x7ff
 373 #define MD_SDIR_VECLSB_BITSHFT  0
 374 #define MD_SDIR_VECLSB_MASK     (MD_SDIR_VECLSB_BITMASK << 5)
 375
 376 /*
 377  * Directory initialization values
 378  */
 379
 380 #define MD_SDIR_INIT_LO         (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
 381                                  MD_SDIR_AX)
 382 #define MD_SDIR_INIT_HI         0
 383 #define MD_SDIR_INIT_PROT       (MD_PROT_RW << MD_SPROT_SHFT)
 384
 385 /* Protection and migration field values */
 386
 387 #define MD_PROT_RW              (UINT64_CAST 0x6)
 388 #define MD_PROT_RO              (UINT64_CAST 0x3)
 389 #define MD_PROT_NO              (UINT64_CAST 0x0)
 390 #define MD_PROT_BAD             (UINT64_CAST 0x5)
 391
 392 /* Premium SIMM protection entry shifts and masks. */
 393
 394 #define MD_PPROT_SHFT           0                       /* Prot. field      */
 395 #define MD_PPROT_MASK           7
 396 #define MD_PPROT_MIGMD_SHFT     3                       /* Migration mode   */
 397 #define MD_PPROT_MIGMD_MASK     (3 << 3)
 398 #define MD_PPROT_REFCNT_SHFT    5                       /* Reference count  */
 399 #define MD_PPROT_REFCNT_WIDTH   0x7ffff
 400 #define MD_PPROT_REFCNT_MASK    (MD_PPROT_REFCNT_WIDTH << 5)
 401
 402 #define MD_PPROT_IO_SHFT        45                      /* I/O Prot field   */
 403 #define MD_PPROT_IO_MASK        (UINT64_CAST 7 << 45)
 404
 405 /* Standard SIMM protection entry shifts and masks. */
 406
 407 #define MD_SPROT_SHFT           0                       /* Prot. field      */
 408 #define MD_SPROT_MASK           7
 409 #define MD_SPROT_MIGMD_SHFT     3                       /* Migration mode   */
 410 #define MD_SPROT_MIGMD_MASK     (3 << 3)
 411 #define MD_SPROT_REFCNT_SHFT    5                       /* Reference count  */
 412 #define MD_SPROT_REFCNT_WIDTH   0x7ff
 413 #define MD_SPROT_REFCNT_MASK    (MD_SPROT_REFCNT_WIDTH << 5)
 414
 415 /* Migration modes used in protection entries */
 416
 417 #define MD_PROT_MIGMD_IREL      (UINT64_CAST 0x3 << 3)
 418 #define MD_PROT_MIGMD_IABS      (UINT64_CAST 0x2 << 3)
 419 #define MD_PROT_MIGMD_PREL      (UINT64_CAST 0x1 << 3)
 420 #define MD_PROT_MIGMD_OFF       (UINT64_CAST 0x0 << 3)
 421
 422
 423 /*
 424  * Operations on page migration threshold register
 425  */
 426
 427 #ifndef __ASSEMBLY__
 428
 429 /*
 430  * LED register macros
 431  */
 432
 433 #define CPU_LED_ADDR(_nasid, _slice)                                       \
 434         (private.p_sn00 ?                                                  \
 435          REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
 436          REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
 437
 438 #define SET_CPU_LEDS(_nasid, _slice,  _val)                                \
 439         (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
 440
 441 #define SET_MY_LEDS(_v)                                                    \
 442         SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
 443
 444 /*
 445  * Operations on Memory/Directory DIMM control register
 446  */
 447
 448 #define DIRTYPE_PREMIUM 1
 449 #define DIRTYPE_STANDARD 0
 450 #define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
 451         (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
 452         MMC_DIR_PREMIUM_SHFT)
 453
 454
 455 /*
 456  * Operations on page migration count difference and absolute threshold
 457  * registers
 458  */
 459
 460 #define MD_MIG_DIFF_THRESH_GET(region) ( \
 461         REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
 462         MD_MIG_DIFF_THRES_VALUE_MASK)
 463
 464 #define MD_MIG_DIFF_THRESH_SET(region, value) (                         \
 465         REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
 466                 MD_MIG_DIFF_THRES_VALID_MASK | (value)))
 467
 468 #define MD_MIG_DIFF_THRESH_DISABLE(region) (                    \
 469         REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
 470                 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
 471                              & ~MD_MIG_DIFF_THRES_VALID_MASK))
 472
 473 #define MD_MIG_DIFF_THRESH_ENABLE(region) (                     \
 474         REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
 475                 REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
 476                              | MD_MIG_DIFF_THRES_VALID_MASK))
 477
 478 #define MD_MIG_DIFF_THRESH_IS_ENABLED(region) (                         \
 479         REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) &                    \
 480                MD_MIG_DIFF_THRES_VALID_MASK)
 481
 482 #define MD_MIG_VALUE_THRESH_GET(region) (                               \
 483         REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &  \
 484         MD_MIG_VALUE_THRES_VALUE_MASK)
 485
 486 #define MD_MIG_VALUE_THRESH_SET(region, value) (                        \
 487         REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
 488                 MD_MIG_VALUE_THRES_VALID_MASK | (value)))
 489
 490 #define MD_MIG_VALUE_THRESH_DISABLE(region) (                   \
 491         REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
 492                 REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH)               \
 493                              & ~MD_MIG_VALUE_THRES_VALID_MASK))
 494
 495 #define MD_MIG_VALUE_THRESH_ENABLE(region) (                    \
 496         REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
 497                 REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH)             \
 498                              | MD_MIG_VALUE_THRES_VALID_MASK))
 499
 500 #define MD_MIG_VALUE_THRESH_IS_ENABLED(region) (                        \
 501         REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &                    \
 502                MD_MIG_VALUE_THRES_VALID_MASK)
 503
 504 /*
 505  * Operations on page migration candidate register
 506  */
 507
 508 #define MD_MIG_CANDIDATE_GET(my_region_id) ( \
 509         REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
 510
 511 #define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
 512
 513 #define MD_MIG_CANDIDATE_NODEID(value) ( \
 514         ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
 515
 516 #define MD_MIG_CANDIDATE_TYPE(value) ( \
 517         ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
 518
 519 #define MD_MIG_CANDIDATE_VALID(value) ( \
 520         ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
 521
 522 /*
 523  * Macros to retrieve fields in the protection entry
 524  */
 525
 526 /* for Premium SIMM */
 527 #define MD_PPROT_REFCNT_GET(value) ( \
 528         ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
 529
 530 #define MD_PPROT_MIGMD_GET(value) ( \
 531         ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
 532
 533 /* for Standard SIMM */
 534 #define MD_SPROT_REFCNT_GET(value) ( \
 535         ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
 536
 537 #define MD_SPROT_MIGMD_GET(value) ( \
 538         ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
 539
 540 /*
 541  * Format of dir_error, mem_error, protocol_error and misc_error registers
 542  */
 543
 544 struct dir_error_reg {
 545         u64     uce_vld:   1,   /*    63: valid directory uce   */
 546                 ae_vld:    1,   /*    62: valid dir prot ecc error */
 547                 ce_vld:    1,   /*    61: valid correctable ECC err*/
 548                 rsvd1:    19,   /* 60-42: reserved              */
 549                 bad_prot:  3,   /* 41-39: encoding, bad access rights*/
 550                 bad_syn:   7,   /* 38-32: bad dir syndrome      */
 551                 rsvd2:     2,   /* 31-30: reserved              */
 552                 hspec_addr:27,  /* 29-03: bddir space bad entry */
 553                 uce_ovr:   1,   /*     2: multiple dir uce's    */
 554                 ae_ovr:    1,   /*     1: multiple prot ecc errs*/
 555                 ce_ovr:    1;   /*     0: multiple correctable errs */
 556 };
 557
 558 typedef union md_dir_error {
 559         u64     derr_reg;       /* the entire register          */
 560         struct dir_error_reg derr_fmt;  /* the register format          */
 561 } md_dir_error_t;
 562
 563
 564 struct mem_error_reg {
 565         u64     uce_vld:   1,   /*    63: valid memory uce      */
 566                 ce_vld:    1,   /*    62: valid correctable ECC err*/
 567                 rsvd1:    22,   /* 61-40: reserved              */
 568                 bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */
 569                 address:  29,   /* 31-03: bad entry pointer     */
 570                 rsvd2:     1,   /*     2: reserved              */
 571                 uce_ovr:   1,   /*     1: multiple mem uce's    */
 572                 ce_ovr:    1;   /*     0: multiple correctable errs */
 573 };
 574
 575
 576 typedef union md_mem_error {
 577         u64     merr_reg;       /* the entire register          */
 578         struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
 579 } md_mem_error_t;
 580
 581
 582 struct proto_error_reg {
 583         u64     valid:     1,   /*    63: valid protocol error  */
 584                 rsvd1:     2,   /* 62-61: reserved              */
 585                 initiator:11,   /* 60-50: id of request initiator*/
 586                 backoff:   2,   /* 49-48: backoff control       */
 587                 msg_type:  8,   /* 47-40: type of request       */
 588                 access:    2,   /* 39-38: access rights of initiator*/
 589                 priority:  1,   /*    37: priority level of requestor*/
 590                 dir_state: 4,   /* 36-33: state of directory    */
 591                 pointer_me:1,   /*    32: initiator same as dir ptr */
 592                 address:  29,   /* 31-03: request address       */
 593                 rsvd2:     2,   /* 02-01: reserved              */
 594                 overrun:   1;   /*     0: multiple protocol errs */
 595 };
 596
 597 typedef union md_proto_error {
 598         u64     perr_reg;       /* the entire register          */
 599         struct proto_error_reg  perr_fmt; /* format of the register     */
 600 } md_proto_error_t;
 601
 602
 603 struct md_sdir_high_fmt {
 604         unsigned short sd_hi_bvec : 11,
 605                        sd_hi_ecc  : 5;
 606 };
 607
 608
 609 typedef union md_sdir_high {
 610         /* The 16 bits of standard directory, upper word */
 611         unsigned short sd_hi_val;
 612         struct  md_sdir_high_fmt sd_hi_fmt;
 613 }md_sdir_high_t;
 614
 615
 616 struct md_sdir_low_shared_fmt {
 617         /* The meaning of lower directory, shared */
 618         unsigned short  sds_lo_bvec  : 5,
 619                         sds_lo_unused: 1,
 620                         sds_lo_state : 3,
 621                         sds_lo_prio  : 1,
 622                         sds_lo_ax    : 1,
 623                         sds_lo_ecc   : 5;
 624 };
 625
 626 struct md_sdir_low_exclusive_fmt {
 627         /* The meaning of lower directory, exclusive */
 628         unsigned short  sde_lo_ptr   : 6,
 629                         sde_lo_state : 3,
 630                         sde_lo_prio  : 1,
 631                         sde_lo_ax    : 1,
 632                         sde_lo_ecc   : 5;
 633 };
 634
 635
 636 typedef union md_sdir_low {
 637         /* The 16 bits of standard directory, lower word */
 638         unsigned short  sd_lo_val;
 639         struct  md_sdir_low_exclusive_fmt sde_lo_fmt;
 640         struct  md_sdir_low_shared_fmt sds_lo_fmt;
 641 }md_sdir_low_t;
 642
 643
 644
 645 struct md_pdir_high_fmt {
 646         u64     pd_hi_unused   : 16,
 647                 pd_hi_bvec     : 38,
 648                 pd_hi_unused1  : 3,
 649                 pd_hi_ecc      : 7;
 650 };
 651
 652
 653 typedef union md_pdir_high {
 654         /* The 48 bits of standard directory, upper word */
 655         u64     pd_hi_val;
 656         struct md_pdir_high_fmt pd_hi_fmt;
 657 }md_pdir_high_t;
 658
 659
 660 struct md_pdir_low_shared_fmt {
 661         /* The meaning of lower directory, shared */
 662         u64     pds_lo_unused   : 16,
 663                 pds_lo_bvec     : 26,
 664                 pds_lo_cnt      :  6,
 665                 pds_lo_state    :  3,
 666                 pds_lo_ste      :  1,
 667                 pds_lo_prio     :  4,
 668                 pds_lo_ax       :  1,
 669                 pds_lo_ecc      :  7;
 670 };
 671
 672 struct md_pdir_low_exclusive_fmt {
 673         /* The meaning of lower directory, exclusive */
 674         u64     pde_lo_unused   : 31,
 675                 pde_lo_ptr      : 11,
 676                 pde_lo_unused1  :  6,
 677                 pde_lo_state    :  3,
 678                 pde_lo_ste      :  1,
 679                 pde_lo_prio     :  4,
 680                 pde_lo_ax       :  1,
 681                 pde_lo_ecc      :  7;
 682 };
 683
 684
 685 typedef union md_pdir_loent {
 686         /* The 48 bits of premium directory, lower word */
 687         u64     pd_lo_val;
 688         struct md_pdir_low_exclusive_fmt pde_lo_fmt;
 689         struct md_pdir_low_shared_fmt   pds_lo_fmt;
 690 }md_pdir_low_t;
 691
 692
 693 /*
 694  *   the following two "union" definitions and two
 695  *   "struct" definitions are used in vmdump.c to
 696  *   represent directory memory information.
 697  */
 698
 699 typedef union   md_dir_high     {
 700         md_sdir_high_t  md_sdir_high;
 701         md_pdir_high_t  md_pdir_high;
 702 } md_dir_high_t;
 703
 704 typedef union   md_dir_low      {
 705         md_sdir_low_t   md_sdir_low;
 706         md_pdir_low_t   md_pdir_low;
 707 } md_dir_low_t;
 708
 709 typedef struct  bddir_entry     {
 710         md_dir_low_t    md_dir_low;
 711         md_dir_high_t   md_dir_high;
 712 } bddir_entry_t;
 713
 714 typedef struct  dir_mem_entry   {
 715         u64             prcpf[MAX_REGIONS];
 716         bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
 717 } dir_mem_entry_t;
 718
 719
 720
 721 typedef union md_perf_sel {
 722         u64     perf_sel_reg;
 723         struct  {
 724                 u64     perf_rsvd : 60,
 725                         perf_en   :  1,
 726                         perf_sel  :  3;
 727         } perf_sel_bits;
 728 } md_perf_sel_t;
 729
 730 typedef union md_perf_cnt {
 731         u64     perf_cnt;
 732         struct  {
 733                 u64     perf_rsvd : 44,
 734                         perf_cnt  : 20;
 735         } perf_cnt_bits;
 736 } md_perf_cnt_t;
 737
 738
 739 #endif /* !__ASSEMBLY__ */
 740
 741
 742 #define DIR_ERROR_VALID_MASK    0xe000000000000000
 743 #define DIR_ERROR_VALID_SHFT    61
 744 #define DIR_ERROR_VALID_UCE     0x8000000000000000
 745 #define DIR_ERROR_VALID_AE      0x4000000000000000
 746 #define DIR_ERROR_VALID_CE      0x2000000000000000
 747
 748 #define MEM_ERROR_VALID_MASK    0xc000000000000000
 749 #define MEM_ERROR_VALID_SHFT    62
 750 #define MEM_ERROR_VALID_UCE     0x8000000000000000
 751 #define MEM_ERROR_VALID_CE      0x4000000000000000
 752
 753 #define PROTO_ERROR_VALID_MASK  0x8000000000000000
 754
 755 #define MISC_ERROR_VALID_MASK   0x3ff
 756
 757 /*
 758  * Mask for hspec address that is stored in the dir error register.
 759  * This represents bits 29 through 3.
 760  */
 761 #define DIR_ERR_HSPEC_MASK      0x3ffffff8
 762 #define ERROR_HSPEC_MASK        0x3ffffff8
 763 #define ERROR_HSPEC_SHFT        3
 764 #define ERROR_ADDR_MASK         0xfffffff8
 765 #define ERROR_ADDR_SHFT         3
 766
 767 /*
 768  * MD_MISC_ERROR register defines.
 769  */
 770
 771 #define MMCE_VALID_MASK         0x3ff
 772 #define MMCE_ILL_MSG_SHFT       8
 773 #define MMCE_ILL_MSG_MASK       (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
 774 #define MMCE_ILL_REV_SHFT       6
 775 #define MMCE_ILL_REV_MASK       (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
 776 #define MMCE_LONG_PACK_SHFT     4
 777 #define MMCE_LONG_PACK_MASK     (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
 778 #define MMCE_SHORT_PACK_SHFT    2
 779 #define MMCE_SHORT_PACK_MASK    (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
 780 #define MMCE_BAD_DATA_SHFT      0
 781 #define MMCE_BAD_DATA_MASK      (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
 782
 783
 784 #define MD_PERF_COUNTERS        6
 785 #define MD_PERF_SETS            6
 786
 787 #define MEM_DIMM_MASK                           0xe0000000
 788 #define MEM_DIMM_SHFT                           29
 789
 790 #endif /* _ASM_SN_SN0_HUBMD_H */