2 * PowerPC memory management structures
4 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
23 #define STE_ESID_V 0x80
24 #define STE_ESID_KS 0x20
25 #define STE_ESID_KP 0x10
26 #define STE_ESID_N 0x08
28 #define STE_VSID_SHIFT 12
30 /* Location of cpu0's segment table */
31 #define STAB0_PAGE 0x6
32 #define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT)
35 extern char initial_stab
[];
36 #endif /* ! __ASSEMBLY */
42 #define SLB_NUM_BOLTED 3
43 #define SLB_CACHE_ENTRIES 8
45 /* Bits in the SLB ESID word */
46 #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
48 /* Bits in the SLB VSID word */
49 #define SLB_VSID_SHIFT 12
50 #define SLB_VSID_KS ASM_CONST(0x0000000000000800)
51 #define SLB_VSID_KP ASM_CONST(0x0000000000000400)
52 #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
53 #define SLB_VSID_L ASM_CONST(0x0000000000000100) /* largepage */
54 #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
55 #define SLB_VSID_LS ASM_CONST(0x0000000000000070) /* size of largepage */
57 #define SLB_VSID_KERNEL (SLB_VSID_KP)
58 #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
60 #define SLBIE_C (0x08000000)
66 #define HPTES_PER_GROUP 8
68 #define HPTE_V_AVPN_SHIFT 7
69 #define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80)
70 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
71 #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
72 #define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
73 #define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
74 #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
75 #define HPTE_V_VALID ASM_CONST(0x0000000000000001)
77 #define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
78 #define HPTE_R_TS ASM_CONST(0x4000000000000000)
79 #define HPTE_R_RPN_SHIFT 12
80 #define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
81 #define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
82 #define HPTE_R_PP ASM_CONST(0x0000000000000003)
84 /* Values for PP (assumes Ks=0, Kp=1) */
85 /* pp0 will always be 0 for linux */
86 #define PP_RWXX 0 /* Supervisor read/write, User none */
87 #define PP_RWRX 1 /* Supervisor read/write, User read */
88 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
89 #define PP_RXRX 3 /* Supervisor read, User read */
98 extern hpte_t
*htab_address
;
99 extern unsigned long htab_hash_mask
;
101 static inline unsigned long hpt_hash(unsigned long vpn
, int large
)
114 return (vsid
& 0x7fffffffffUL
) ^ page
;
117 static inline void __tlbie(unsigned long va
, int large
)
119 /* clear top 16 bits, non SLS segment */
120 va
&= ~(0xffffULL
<< 48);
124 asm volatile("tlbie %0,1" : : "r"(va
) : "memory");
127 asm volatile("tlbie %0,0" : : "r"(va
) : "memory");
131 static inline void tlbie(unsigned long va
, int large
)
133 asm volatile("ptesync": : :"memory");
135 asm volatile("eieio; tlbsync; ptesync": : :"memory");
138 static inline void __tlbiel(unsigned long va
)
140 /* clear top 16 bits, non SLS segment */
141 va
&= ~(0xffffULL
<< 48);
145 * Thanks to Alan Modra we are now able to use machine specific
146 * assembly instructions (like tlbiel) by using the gas -many flag.
147 * However we have to support older toolchains so for the moment
151 asm volatile("tlbiel %0" : : "r"(va
) : "memory");
153 asm volatile(".long 0x7c000224 | (%0 << 11)" : : "r"(va
) : "memory");
157 static inline void tlbiel(unsigned long va
)
159 asm volatile("ptesync": : :"memory");
161 asm volatile("ptesync": : :"memory");
164 static inline unsigned long slot2va(unsigned long hpte_v
, unsigned long slot
)
166 unsigned long avpn
= HPTE_V_AVPN_VAL(hpte_v
);
171 if (! (hpte_v
& HPTE_V_LARGE
)) {
172 unsigned long vpi
, pteg
;
174 pteg
= slot
/ HPTES_PER_GROUP
;
175 if (hpte_v
& HPTE_V_SECONDARY
)
178 vpi
= ((va
>> 28) ^ pteg
) & htab_hash_mask
;
180 va
|= vpi
<< PAGE_SHIFT
;
187 * Handle a fault by adding an HPTE. If the address can't be determined
188 * to be valid via Linux page tables, return 1. If handled return 0
190 extern int __hash_page(unsigned long ea
, unsigned long access
,
191 unsigned long vsid
, pte_t
*ptep
, unsigned long trap
,
194 extern void htab_finish_init(void);
196 extern void hpte_init_native(void);
197 extern void hpte_init_lpar(void);
198 extern void hpte_init_iSeries(void);
200 extern long pSeries_lpar_hpte_insert(unsigned long hpte_group
,
201 unsigned long va
, unsigned long prpn
,
202 unsigned long vflags
,
203 unsigned long rflags
);
204 extern long native_hpte_insert(unsigned long hpte_group
, unsigned long va
,
206 unsigned long vflags
, unsigned long rflags
);
208 extern void stabs_alloc(void);
210 #endif /* __ASSEMBLY__ */
215 * We first generate a 36-bit "proto-VSID". For kernel addresses this
216 * is equal to the ESID, for user addresses it is:
217 * (context << 15) | (esid & 0x7fff)
219 * The two forms are distinguishable because the top bit is 0 for user
220 * addresses, whereas the top two bits are 1 for kernel addresses.
221 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
224 * The proto-VSIDs are then scrambled into real VSIDs with the
225 * multiplicative hash:
227 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
228 * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
229 * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
231 * This scramble is only well defined for proto-VSIDs below
232 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
233 * reserved. VSID_MULTIPLIER is prime, so in particular it is
234 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
235 * Because the modulus is 2^n-1 we can compute it efficiently without
236 * a divide or extra multiply (see below).
238 * This scheme has several advantages over older methods:
240 * - We have VSIDs allocated for every kernel address
241 * (i.e. everything above 0xC000000000000000), except the very top
242 * segment, which simplifies several things.
244 * - We allow for 15 significant bits of ESID and 20 bits of
245 * context for user addresses. i.e. 8T (43 bits) of address space for
246 * up to 1M contexts (although the page table structure and context
247 * allocation will need changes to take advantage of this).
249 * - The scramble function gives robust scattering in the hash
250 * table (at least based on some initial results). The previous
251 * method was more susceptible to pathological cases giving excessive
255 * WARNING - If you change these you must make sure the asm
256 * implementations in slb_allocate (slb_low.S), do_stab_bolted
257 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
259 * You'll also need to change the precomputed VSID values in head.S
260 * which are used by the iSeries firmware.
263 #define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
265 #define VSID_MODULUS ((1UL<<VSID_BITS)-1)
267 #define CONTEXT_BITS 19
268 #define USER_ESID_BITS 16
270 #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
273 * This macro generates asm code to compute the VSID scramble
274 * function. Used in slb_allocate() and do_stab_bolted. The function
275 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
277 * rt = register continaing the proto-VSID and into which the
278 * VSID will be stored
279 * rx = scratch register (clobbered)
281 * - rt and rx must be different registers
282 * - The answer will end up in the low 36 bits of rt. The higher
283 * bits may contain other garbage, so you may need to mask the
286 #define ASM_VSID_SCRAMBLE(rt, rx) \
287 lis rx,VSID_MULTIPLIER@h; \
288 ori rx,rx,VSID_MULTIPLIER@l; \
289 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
291 srdi rx,rt,VSID_BITS; \
292 clrldi rt,rt,(64-VSID_BITS); \
293 add rt,rt,rx; /* add high and low bits */ \
294 /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
295 * 2^36-1+2^28-1. That in particular means that if r3 >= \
296 * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
297 * the bit clear, r3 already has the answer we want, if it \
298 * doesn't, the answer is the low 36 bits of r3+1. So in all \
299 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
301 srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
307 typedef unsigned long mm_context_id_t
;
311 #ifdef CONFIG_HUGETLB_PAGE
312 u16 low_htlb_areas
, high_htlb_areas
;
317 static inline unsigned long vsid_scramble(unsigned long protovsid
)
320 /* The code below is equivalent to this function for arguments
321 * < 2^VSID_BITS, which is all this should ever be called
322 * with. However gcc is not clever enough to compute the
323 * modulus (2^n-1) without a second multiply. */
324 return ((protovsid
* VSID_MULTIPLIER
) % VSID_MODULUS
);
328 x
= protovsid
* VSID_MULTIPLIER
;
329 x
= (x
>> VSID_BITS
) + (x
& VSID_MODULUS
);
330 return (x
+ ((x
+1) >> VSID_BITS
)) & VSID_MODULUS
;
334 /* This is only valid for addresses >= KERNELBASE */
335 static inline unsigned long get_kernel_vsid(unsigned long ea
)
337 return vsid_scramble(ea
>> SID_SHIFT
);
340 /* This is only valid for user addresses (which are below 2^41) */
341 static inline unsigned long get_vsid(unsigned long context
, unsigned long ea
)
343 return vsid_scramble((context
<< USER_ESID_BITS
)
344 | (ea
>> SID_SHIFT
));
347 #define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
348 #define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
350 #endif /* __ASSEMBLY */
352 #endif /* _PPC64_MMU_H_ */