include/asm-ppc64/pci.h

   1 #ifndef __PPC64_PCI_H
   2 #define __PPC64_PCI_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/dma-mapping.h>
  16
  17 #include <asm/machdep.h>
  18 #include <asm/scatterlist.h>
  19 #include <asm/io.h>
  20 #include <asm/prom.h>
  21
  22 #include <asm-generic/pci-dma-compat.h>
  23
  24 #define PCIBIOS_MIN_IO          0x1000
  25 #define PCIBIOS_MIN_MEM         0x10000000
  26
  27 struct pci_dev;
  28
  29 #ifdef CONFIG_PPC_ISERIES
  30 #define pcibios_scan_all_fns(a, b)      0
  31 #else
  32 extern int pcibios_scan_all_fns(struct pci_bus *bus, int devfn);
  33 #endif
  34
  35 static inline void pcibios_set_master(struct pci_dev *dev)
  36 {
  37         /* No special bus mastering setup handling */
  38 }
  39
  40 static inline void pcibios_penalize_isa_irq(int irq, int active)
  41 {
  42         /* We don't do dynamic PCI IRQ allocation */
  43 }
  44
  45 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
  46 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
  47 {
  48         if (ppc_md.pci_get_legacy_ide_irq)
  49                 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
  50         return channel ? 15 : 14;
  51 }
  52
  53 #define HAVE_ARCH_PCI_MWI 1
  54 static inline int pcibios_prep_mwi(struct pci_dev *dev)
  55 {
  56         /*
  57          * We would like to avoid touching the cacheline size or MWI bit
  58          * but we cant do that with the current pcibios_prep_mwi
  59          * interface. pSeries firmware sets the cacheline size (which is not
  60          * the cpu cacheline size in all cases) and hardware treats MWI
  61          * the same as memory write. So we dont touch the cacheline size
  62          * here and allow the generic code to set the MWI bit.
  63          */
  64         return 0;
  65 }
  66
  67 extern unsigned int pcibios_assign_all_busses(void);
  68
  69 extern struct dma_mapping_ops pci_dma_ops;
  70
  71 /* For DAC DMA, we currently don't support it by default, but
  72  * we let the platform override this
  73  */
  74 static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
  75 {
  76         if (pci_dma_ops.dac_dma_supported)
  77                 return pci_dma_ops.dac_dma_supported(&hwdev->dev, mask);
  78         return 0;
  79 }
  80
  81 #ifdef CONFIG_PCI
  82 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  83                                         enum pci_dma_burst_strategy *strat,
  84                                         unsigned long *strategy_parameter)
  85 {
  86         unsigned long cacheline_size;
  87         u8 byte;
  88
  89         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
  90         if (byte == 0)
  91                 cacheline_size = 1024;
  92         else
  93                 cacheline_size = (int) byte * 4;
  94
  95         *strat = PCI_DMA_BURST_MULTIPLE;
  96         *strategy_parameter = cacheline_size;
  97 }
  98 #endif
  99
 100 extern int pci_domain_nr(struct pci_bus *bus);
 101
 102 /* Decide whether to display the domain number in /proc */
 103 extern int pci_proc_domain(struct pci_bus *bus);
 104
 105 struct vm_area_struct;
 106 /* Map a range of PCI memory or I/O space for a device into user space */
 107 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
 108                         enum pci_mmap_state mmap_state, int write_combine);
 109
 110 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
 111 #define HAVE_PCI_MMAP   1
 112
 113 /* pci_unmap_{single,page} is not a nop, thus... */
 114 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
 115         dma_addr_t ADDR_NAME;
 116 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
 117         __u32 LEN_NAME;
 118 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
 119         ((PTR)->ADDR_NAME)
 120 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
 121         (((PTR)->ADDR_NAME) = (VAL))
 122 #define pci_unmap_len(PTR, LEN_NAME)                    \
 123         ((PTR)->LEN_NAME)
 124 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
 125         (((PTR)->LEN_NAME) = (VAL))
 126
 127 /* The PCI address space does equal the physical memory
 128  * address space.  The networking and block device layers use
 129  * this boolean for bounce buffer decisions.
 130  */
 131 #define PCI_DMA_BUS_IS_PHYS     (0)
 132
 133 extern void
 134 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
 135                         struct resource *res);
 136
 137 extern void
 138 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 139                         struct pci_bus_region *region);
 140
 141 static inline struct resource *
 142 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 143 {
 144         struct resource *root = NULL;
 145
 146         if (res->flags & IORESOURCE_IO)
 147                 root = &ioport_resource;
 148         if (res->flags & IORESOURCE_MEM)
 149                 root = &iomem_resource;
 150
 151         return root;
 152 }
 153
 154 extern int
 155 unmap_bus_range(struct pci_bus *bus);
 156
 157 extern int
 158 remap_bus_range(struct pci_bus *bus);
 159
 160 extern void
 161 pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus);
 162
 163 extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
 164
 165 extern int pci_read_irq_line(struct pci_dev *dev);
 166
 167 extern void pcibios_add_platform_entries(struct pci_dev *dev);
 168
 169 struct file;
 170 extern pgprot_t pci_phys_mem_access_prot(struct file *file,
 171                                          unsigned long offset,
 172                                          unsigned long size,
 173                                          pgprot_t prot);
 174
 175 #ifdef CONFIG_PPC_MULTIPLATFORM
 176 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
 177 extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
 178                                  const struct resource *rsrc,
 179                                  u64 *start, u64 *end);
 180 #endif /* CONFIG_PPC_MULTIPLATFORM */
 181
 182
 183 #endif  /* __KERNEL__ */
 184
 185 #endif /* __PPC64_PCI_H */