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[CONNECTOR]: Update documentation to match reality.
[linux-2.6/verdex.git] / include / sound / emu10k1.h
blob14cb2718cb77f1a0d00865ee8ff09e8456ae4fef
1 #ifndef __SOUND_EMU10K1_H
2 #define __SOUND_EMU10K1_H
3
4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
6 * Creative Labs, Inc.
7 * Definitions for EMU10K1 (SB Live!) chips
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26 #ifdef __KERNEL__
27
28 #include <sound/pcm.h>
29 #include <sound/rawmidi.h>
30 #include <sound/hwdep.h>
31 #include <sound/ac97_codec.h>
32 #include <sound/util_mem.h>
33 #include <sound/pcm-indirect.h>
34 #include <sound/timer.h>
35 #include <linux/interrupt.h>
36 #include <asm/io.h>
37
38 /* ------------------- DEFINES -------------------- */
39
40 #define EMUPAGESIZE 4096
41 #define MAXREQVOICES 8
42 #define MAXPAGES 8192
43 #define RESERVED 0
44 #define NUM_MIDI 16
45 #define NUM_G 64 /* use all channels */
46 #define NUM_FXSENDS 4
47 #define NUM_EFX_PLAYBACK 16
48
49 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
50 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
51 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit */
52
53 #define TMEMSIZE 256*1024
54 #define TMEMSIZEREG 4
55
56 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
57
58 // Audigy specify registers are prefixed with 'A_'
59
60 /************************************************************************************************/
61 /* PCI function 0 registers, address = <val> + PCIBASE0 */
62 /************************************************************************************************/
63
64 #define PTR 0x00 /* Indexed register set pointer register */
65 /* NOTE: The CHANNELNUM and ADDRESS words can */
66 /* be modified independently of each other. */
67 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
68 /* channel number of the register to be */
69 /* accessed. For non per-channel registers the */
70 /* value should be set to zero. */
71 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
72 #define A_PTR_ADDRESS_MASK 0x0fff0000
73
74 #define DATA 0x04 /* Indexed register set data register */
75
76 #define IPR 0x08 /* Global interrupt pending register */
77 /* Clear pending interrupts by writing a 1 to */
78 /* the relevant bits and zero to the other bits */
79 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
80 to interrupt */
81 #define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
82 which INTE bits enable it) */
83
84 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
85 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
86 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
87
88 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
89 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
90
91 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
92 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
93 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
94 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
95 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
96 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
97 #define IPR_MUTE 0x00040000 /* Mute button pressed */
98 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
99 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
100 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
101 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
102 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
103 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
104 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
105 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
106 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
107 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
108 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
109 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
110 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
111 /* highest set channel in CLIPL, CLIPH, HLIPL, */
112 /* or HLIPH. When IP is written with CL set, */
113 /* the bit in H/CLIPL or H/CLIPH corresponding */
114 /* to the CIN value written will be cleared. */
115
116 #define INTE 0x0c /* Interrupt enable register */
117 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
118 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
119 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
120 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
121 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
122 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
123 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
124 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
125 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
126 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
127 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
128 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
129 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
130 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
131 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
132 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
133 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
134 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
135
136 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
137 /* NOTE: There is no reason to use this under */
138 /* Linux, and it will cause odd hardware */
139 /* behavior and possibly random segfaults and */
140 /* lockups if enabled. */
141
142 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
143 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
144 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
145
146
147 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
148 /* NOTE: This bit must always be enabled */
149 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
150 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
151 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
152 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
153 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
154 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
155 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
156 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
157 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
158 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
159 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
160 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
161 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
162
163 #define WC 0x10 /* Wall Clock register */
164 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
165 #define WC_SAMPLECOUNTER 0x14060010
166 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
167 /* NOTE: Each channel takes 1/64th of a sample */
168 /* period to be serviced. */
169
170 #define HCFG 0x14 /* Hardware config register */
171 /* NOTE: There is no reason to use the legacy */
172 /* SoundBlaster emulation stuff described below */
173 /* under Linux, and all kinds of weird hardware */
174 /* behavior can result if you try. Don't. */
175 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
176 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
177 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
178 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
179 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
180 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
181 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
182 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
183 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
184 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
185 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
186 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
187 /* NOTE: The rest of the bits in this register */
188 /* _are_ relevant under Linux. */
189 #define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
190 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
191 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
192 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
193 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
194 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
195 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
196 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
197 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
198 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
199 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
200 /* 1 = Force all 3 async digital inputs to use */
201 /* the same async sample rate tracker (ZVIDEO) */
202 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
203 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
204 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
205 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
206 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
207 /* will automatically mute their output when */
208 /* they are not rate-locked to the external */
209 /* async audio source */
210 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
211 /* NOTE: This should generally never be used. */
212 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
213 /* NOTE: This should generally never be used. */
214 #define HCFG_LOCKTANKCACHE 0x01020014
215 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
216 /* NOTE: This is a 'cheap' way to implement a */
217 /* master mute function on the mute button, and */
218 /* in general should not be used unless a more */
219 /* sophisticated master mute function has not */
220 /* been written. */
221 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
222 /* Should be set to 1 when the EMU10K1 is */
223 /* completely initialized. */
224
225 //For Audigy, MPU port move to 0x70-0x74 ptr register
226
227 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
228
229 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
230 #define MUCMD_RESET 0xff /* RESET command */
231 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
232 /* NOTE: All other commands are ignored */
233
234 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
235 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
236 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
237
238 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
239 #define A_GPINPUT_MASK 0xff00
240 #define A_GPOUTPUT_MASK 0x00ff
241
242 // Audigy output/GPIO stuff taken from the kX drivers
243 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
244 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
245 #define A_IOCFG_ENABLE_DIGITAL 0x0004
246 #define A_IOCFG_UNKNOWN_20 0x0020
247 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
248 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
249 #define A_IOCFG_GPOUT2 0x0001 /* IR */
250 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
251 /* + digital for generic 10k2 */
252 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
253 #define A_IOCFG_FRONT_JACK 0x4000
254 #define A_IOCFG_REAR_JACK 0x8000
255 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
256
257 /* outputs:
258 * for audigy2 platinum: 0xa00
259 * for a2 platinum ex: 0x1c00
260 * for a1 platinum: 0x0
261 */
262
263 #define TIMER 0x1a /* Timer terminal count register */
264 /* NOTE: After the rate is changed, a maximum */
265 /* of 1024 sample periods should be allowed */
266 /* before the new rate is guaranteed accurate. */
267 #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
268 /* 0 == 1024 periods, [1..4] are not useful */
269 #define TIMER_RATE 0x0a00001a
270
271 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
272
273 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
274 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
275 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
276
277 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
278 #define PTR2 0x20 /* Indexed register set pointer register */
279 #define DATA2 0x24 /* Indexed register set data register */
280 #define IPR2 0x28 /* P16V interrupt pending register */
281 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
282 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
283 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
284 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
285 /* 0x00000100 Playback. Only in once per period.
286 * 0x00110000 Capture. Int on half buffer.
287 */
288 #define INTE2 0x2c /* P16V Interrupt enable register. */
289 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
290 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
291 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
292 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
293 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
294 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
295 #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
296 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
297 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
298 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
299 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
300 /* 0x00000000 2-channel output. */
301 /* 0x00000200 8-channel output. */
302 /* 0x00000004 pauses stream/irq fail. */
303 /* Rest of bits no nothing to sound output */
304 /* bit 0: Enable P16V audio.
305 * bit 1: Lock P16V record memory cache.
306 * bit 2: Lock P16V playback memory cache.
307 * bit 3: Dummy record insert zero samples.
308 * bit 8: Record 8-channel in phase.
309 * bit 9: Playback 8-channel in phase.
310 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
311 * bit 13: Playback mixer enable.
312 * bit 14: Route SRC48 mixer output to fx engine.
313 * bit 15: Enable IEEE 1394 chip.
314 */
315 #define IPR3 0x38 /* Cdif interrupt pending register */
316 #define INTE3 0x3c /* Cdif interrupt enable register. */
317 /************************************************************************************************/
318 /* PCI function 1 registers, address = <val> + PCIBASE1 */
319 /************************************************************************************************/
320
321 #define JOYSTICK1 0x00 /* Analog joystick port register */
322 #define JOYSTICK2 0x01 /* Analog joystick port register */
323 #define JOYSTICK3 0x02 /* Analog joystick port register */
324 #define JOYSTICK4 0x03 /* Analog joystick port register */
325 #define JOYSTICK5 0x04 /* Analog joystick port register */
326 #define JOYSTICK6 0x05 /* Analog joystick port register */
327 #define JOYSTICK7 0x06 /* Analog joystick port register */
328 #define JOYSTICK8 0x07 /* Analog joystick port register */
329
330 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
331 /* When reading, use these bitfields: */
332 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
333 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
334
335
336 /********************************************************************************************************/
337 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
338 /********************************************************************************************************/
339
340 #define CPF 0x00 /* Current pitch and fraction register */
341 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
342 #define CPF_CURRENTPITCH 0x10100000
343 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
344 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
345 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
346
347 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
348 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
349 #define PTRX_PITCHTARGET 0x10100001
350 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
351 #define PTRX_FXSENDAMOUNT_A 0x08080001
352 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
353 #define PTRX_FXSENDAMOUNT_B 0x08000001
354
355 #define CVCF 0x02 /* Current volume and filter cutoff register */
356 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
357 #define CVCF_CURRENTVOL 0x10100002
358 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
359 #define CVCF_CURRENTFILTER 0x10000002
360
361 #define VTFT 0x03 /* Volume target and filter cutoff target register */
362 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
363 #define VTFT_VOLUMETARGET 0x10100003
364 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
365 #define VTFT_FILTERTARGET 0x10000003
366
367 #define Z1 0x05 /* Filter delay memory 1 register */
368
369 #define Z2 0x04 /* Filter delay memory 2 register */
370
371 #define PSST 0x06 /* Send C amount and loop start address register */
372 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
373
374 #define PSST_FXSENDAMOUNT_C 0x08180006
375
376 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
377 #define PSST_LOOPSTARTADDR 0x18000006
378
379 #define DSL 0x07 /* Send D amount and loop start address register */
380 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
381
382 #define DSL_FXSENDAMOUNT_D 0x08180007
383
384 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
385 #define DSL_LOOPENDADDR 0x18000007
386
387 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
388 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
389 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
390 /* 1 == full band, 7 == lowpass */
391 /* ROM 0 is used when pitch shifting downward or less */
392 /* then 3 semitones upward. Increasingly higher ROM */
393 /* numbers are used, typically in steps of 3 semitones, */
394 /* as upward pitch shifting is performed. */
395 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
396 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
397 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
398 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
399 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
400 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
401 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
402 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
403 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
404 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
405 #define CCCA_CURRADDR 0x18000008
406
407 #define CCR 0x09 /* Cache control register */
408 #define CCR_CACHEINVALIDSIZE 0x07190009
409 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
410 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
411 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
412 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
413 #define CCR_READADDRESS 0x06100009
414 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
415 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
416 /* NOTE: This is valid only if CACHELOOPFLAG is set */
417 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
418 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
419
420 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
421 /* NOTE: This register is normally not used */
422 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
423
424 #define FXRT 0x0b /* Effects send routing register */
425 /* NOTE: It is illegal to assign the same routing to */
426 /* two effects sends. */
427 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
428 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
429 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
430 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
431
432 #define MAPA 0x0c /* Cache map A */
433
434 #define MAPB 0x0d /* Cache map B */
435
436 #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
437 #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
438
439 #define ENVVOL 0x10 /* Volume envelope register */
440 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
441 /* 0x8000-n == 666*n usec delay */
442
443 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
444 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
445 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
446 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
447 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
448
449 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
450 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
451 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
452 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
453 /* this channel and from writing to pitch, filter and */
454 /* volume targets. */
455 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
456 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
457
458 #define LFOVAL1 0x13 /* Modulation LFO value */
459 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
460 /* 0x8000-n == 666*n usec delay */
461
462 #define ENVVAL 0x14 /* Modulation envelope register */
463 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
464 /* 0x8000-n == 666*n usec delay */
465
466 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
467 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
468 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
469 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
470 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
471
472 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
473 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
474 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
475 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
476 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
477
478 #define LFOVAL2 0x17 /* Vibrato LFO register */
479 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
480 /* 0x8000-n == 666*n usec delay */
481
482 #define IP 0x18 /* Initial pitch register */
483 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
484 /* 4 bits of octave, 12 bits of fractional octave */
485 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
486
487 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
488 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
489 /* 6 most significant bits are semitones */
490 /* 2 least significant bits are fractions */
491 #define IFATN_FILTERCUTOFF 0x08080019
492 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
493 #define IFATN_ATTENUATION 0x08000019
494
495
496 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
497 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
498 /* Signed 2's complement, +/- one octave peak extremes */
499 #define PEFE_PITCHAMOUNT 0x0808001a
500 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
501 /* Signed 2's complement, +/- six octaves peak extremes */
502 #define PEFE_FILTERAMOUNT 0x0800001a
503 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
504 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
505 /* Signed 2's complement, +/- one octave extremes */
506 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
507 /* Signed 2's complement, +/- three octave extremes */
508
509
510 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
511 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
512 /* Signed 2's complement, with +/- 12dB extremes */
513
514 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
515 /* ??Hz steps, maximum of ?? Hz. */
516 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
517 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
518 /* Signed 2's complement, +/- one octave extremes */
519 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
520 /* 0.039Hz steps, maximum of 9.85 Hz. */
521
522 #define TEMPENV 0x1e /* Tempory envelope register */
523 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
524 /* NOTE: All channels contain internal variables; do */
525 /* not write to these locations. */
526
527 /* 1f something */
528
529 #define CD0 0x20 /* Cache data 0 register */
530 #define CD1 0x21 /* Cache data 1 register */
531 #define CD2 0x22 /* Cache data 2 register */
532 #define CD3 0x23 /* Cache data 3 register */
533 #define CD4 0x24 /* Cache data 4 register */
534 #define CD5 0x25 /* Cache data 5 register */
535 #define CD6 0x26 /* Cache data 6 register */
536 #define CD7 0x27 /* Cache data 7 register */
537 #define CD8 0x28 /* Cache data 8 register */
538 #define CD9 0x29 /* Cache data 9 register */
539 #define CDA 0x2a /* Cache data A register */
540 #define CDB 0x2b /* Cache data B register */
541 #define CDC 0x2c /* Cache data C register */
542 #define CDD 0x2d /* Cache data D register */
543 #define CDE 0x2e /* Cache data E register */
544 #define CDF 0x2f /* Cache data F register */
545
546 /* 0x30-3f seem to be the same as 0x20-2f */
547
548 #define PTB 0x40 /* Page table base register */
549 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
550
551 #define TCB 0x41 /* Tank cache base register */
552 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
553
554 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
555 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
556 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
557 /* NOTE: To guarantee phase coherency, both channels */
558 /* must be disabled prior to enabling both channels. */
559 #define A_ADCCR_RCHANENABLE 0x00000020
560 #define A_ADCCR_LCHANENABLE 0x00000010
561
562 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
563 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
564 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
565 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
566 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
567 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
568 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
569 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
570 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
571 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
572 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
573 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
574 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
575
576 #define FXWC 0x43 /* FX output write channels register */
577 /* When set, each bit enables the writing of the */
578 /* corresponding FX output channel (internal registers */
579 /* 0x20-0x3f) to host memory. This mode of recording */
580 /* is 16bit, 48KHz only. All 32 channels can be enabled */
581 /* simultaneously. */
582
583 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
584 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
585 #define FXWC_DEFAULTROUTE_A (1<<12)
586 #define FXWC_DEFAULTROUTE_D (1<<13)
587 #define FXWC_ADCLEFT (1<<18)
588 #define FXWC_CDROMSPDIFLEFT (1<<18)
589 #define FXWC_ADCRIGHT (1<<19)
590 #define FXWC_CDROMSPDIFRIGHT (1<<19)
591 #define FXWC_MIC (1<<20)
592 #define FXWC_ZOOMLEFT (1<<20)
593 #define FXWC_ZOOMRIGHT (1<<21)
594 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
595 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
596
597 #define TCBS 0x44 /* Tank cache buffer size register */
598 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
599 #define TCBS_BUFFSIZE_16K 0x00000000
600 #define TCBS_BUFFSIZE_32K 0x00000001
601 #define TCBS_BUFFSIZE_64K 0x00000002
602 #define TCBS_BUFFSIZE_128K 0x00000003
603 #define TCBS_BUFFSIZE_256K 0x00000004
604 #define TCBS_BUFFSIZE_512K 0x00000005
605 #define TCBS_BUFFSIZE_1024K 0x00000006
606 #define TCBS_BUFFSIZE_2048K 0x00000007
607
608 #define MICBA 0x45 /* AC97 microphone buffer address register */
609 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
610
611 #define ADCBA 0x46 /* ADC buffer address register */
612 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
613
614 #define FXBA 0x47 /* FX Buffer Address */
615 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
616
617 /* 0x48 something - word access, defaults to 3f */
618
619 #define MICBS 0x49 /* Microphone buffer size register */
620
621 #define ADCBS 0x4a /* ADC buffer size register */
622
623 #define FXBS 0x4b /* FX buffer size register */
624
625 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
626
627 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
628 #define ADCBS_BUFSIZE_NONE 0x00000000
629 #define ADCBS_BUFSIZE_384 0x00000001
630 #define ADCBS_BUFSIZE_448 0x00000002
631 #define ADCBS_BUFSIZE_512 0x00000003
632 #define ADCBS_BUFSIZE_640 0x00000004
633 #define ADCBS_BUFSIZE_768 0x00000005
634 #define ADCBS_BUFSIZE_896 0x00000006
635 #define ADCBS_BUFSIZE_1024 0x00000007
636 #define ADCBS_BUFSIZE_1280 0x00000008
637 #define ADCBS_BUFSIZE_1536 0x00000009
638 #define ADCBS_BUFSIZE_1792 0x0000000a
639 #define ADCBS_BUFSIZE_2048 0x0000000b
640 #define ADCBS_BUFSIZE_2560 0x0000000c
641 #define ADCBS_BUFSIZE_3072 0x0000000d
642 #define ADCBS_BUFSIZE_3584 0x0000000e
643 #define ADCBS_BUFSIZE_4096 0x0000000f
644 #define ADCBS_BUFSIZE_5120 0x00000010
645 #define ADCBS_BUFSIZE_6144 0x00000011
646 #define ADCBS_BUFSIZE_7168 0x00000012
647 #define ADCBS_BUFSIZE_8192 0x00000013
648 #define ADCBS_BUFSIZE_10240 0x00000014
649 #define ADCBS_BUFSIZE_12288 0x00000015
650 #define ADCBS_BUFSIZE_14366 0x00000016
651 #define ADCBS_BUFSIZE_16384 0x00000017
652 #define ADCBS_BUFSIZE_20480 0x00000018
653 #define ADCBS_BUFSIZE_24576 0x00000019
654 #define ADCBS_BUFSIZE_28672 0x0000001a
655 #define ADCBS_BUFSIZE_32768 0x0000001b
656 #define ADCBS_BUFSIZE_40960 0x0000001c
657 #define ADCBS_BUFSIZE_49152 0x0000001d
658 #define ADCBS_BUFSIZE_57344 0x0000001e
659 #define ADCBS_BUFSIZE_65536 0x0000001f
660
661
662 #define CDCS 0x50 /* CD-ROM digital channel status register */
663
664 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
665
666 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
667
668 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
669
670 #define A_DBG 0x53
671 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
672 #define A_DBG_ZC 0x40000000 /* zero tram counter */
673 #define A_DBG_STEP_ADDR 0x000003ff
674 #define A_DBG_SATURATION_OCCURED 0x20000000
675 #define A_DBG_SATURATION_ADDR 0x0ffc0000
676
677 // NOTE: 0x54,55,56: 64-bit
678 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
679
680 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
681
682 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
683
684 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
685 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
686 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
687 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
688 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
689 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
690 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
691 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
692 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
693 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
694 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
695 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
696 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
697 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
698 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
699 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
700 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
701 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
702 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
703 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
704 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
705 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
706 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
707
708 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
709 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
710
711 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
712
713 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
714
715 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
716
717 #define SOLEL 0x5c /* Stop on loop enable low register */
718
719 #define SOLEH 0x5d /* Stop on loop enable high register */
720
721 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
722 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
723 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
724 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
725 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
726
727 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
728 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
729 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
730 #define AC97SLOT_CNTR 0x10 /* Center enable */
731 #define AC97SLOT_LFE 0x20 /* LFE enable */
732
733 // NOTE: 0x60,61,62: 64-bit
734 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
735
736 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
737
738 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
739 /* NOTE: This one has no SPDIFLOCKED field */
740 /* Assumes sample lock */
741
742 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
743 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
744 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
745 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
746 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
747
748 /* Note that these values can vary +/- by a small amount */
749 #define SRCS_SPDIFRATE_44 0x0003acd9
750 #define SRCS_SPDIFRATE_48 0x00040000
751 #define SRCS_SPDIFRATE_96 0x00080000
752
753 #define MICIDX 0x63 /* Microphone recording buffer index register */
754 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
755 #define MICIDX_IDX 0x10000063
756
757 #define ADCIDX 0x64 /* ADC recording buffer index register */
758 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
759 #define ADCIDX_IDX 0x10000064
760
761 #define A_ADCIDX 0x63
762 #define A_ADCIDX_IDX 0x10000063
763
764 #define A_MICIDX 0x64
765 #define A_MICIDX_IDX 0x10000064
766
767 #define FXIDX 0x65 /* FX recording buffer index register */
768 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
769 #define FXIDX_IDX 0x10000065
770
771 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
772 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */
773
774 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */
775
776 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */
777
778 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */
779
780 // 0x6a,6b,6c used for some recording
781 // 0x6d unused
782 // 0x6e,6f - tanktable base / offset
783
784 /* This is the MPU port on the card (via the game port) */
785 #define A_MUDATA1 0x70
786 #define A_MUCMD1 0x71
787 #define A_MUSTAT1 A_MUCMD1
788
789 /* This is the MPU port on the Audigy Drive */
790 #define A_MUDATA2 0x72
791 #define A_MUCMD2 0x73
792 #define A_MUSTAT2 A_MUCMD2
793
794 /* The next two are the Audigy equivalent of FXWC */
795 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
796 /* Each bit selects a channel for recording */
797 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
798 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
799
800 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
801 #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
802 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
803 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */
804 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
805 #define A_SPDIF_48000 0x00000000
806 #define A_SPDIF_192000 0x00000020
807 #define A_SPDIF_96000 0x00000040
808 #define A_SPDIF_44100 0x00000080
809
810 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
811 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */
812 #define A_I2S_CAPTURE_192000 0x00000200
813 #define A_I2S_CAPTURE_96000 0x00000400
814 #define A_I2S_CAPTURE_44100 0x00000800
815
816 #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
817 #define A_PCM_48000 0x00000000
818 #define A_PCM_192000 0x00002000
819 #define A_PCM_96000 0x00004000
820 #define A_PCM_44100 0x00008000
821
822 /* 0x77,0x78,0x79 "something i2s-related" - default to 0x01080000 on my audigy 2 ZS --rlrevell */
823 /* 0x7a, 0x7b - lookup tables */
824
825 #define A_FXRT2 0x7c
826 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
827 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
828 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
829 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
830
831 #define A_SENDAMOUNTS 0x7d
832 #define A_FXSENDAMOUNT_E_MASK 0xFF000000
833 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
834 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
835 #define A_FXSENDAMOUNT_H_MASK 0x000000FF
836 /* 0x7c, 0x7e "high bit is used for filtering" */
837
838 /* The send amounts for this one are the same as used with the emu10k1 */
839 #define A_FXRT1 0x7e
840 #define A_FXRT_CHANNELA 0x0000003f
841 #define A_FXRT_CHANNELB 0x00003f00
842 #define A_FXRT_CHANNELC 0x003f0000
843 #define A_FXRT_CHANNELD 0x3f000000
844
845
846 /* Each FX general purpose register is 32 bits in length, all bits are used */
847 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
848 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
849
850 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
851 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
852
853 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
854 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
855 /* locations are for external TRAM. */
856 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
857 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
858
859 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
860 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
861 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
862 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
863 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
864 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
865 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
866
867 #define MICROCODEBASE 0x400 /* Microcode data base address */
868
869 /* Each DSP microcode instruction is mapped into 2 doublewords */
870 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
871 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
872 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
873 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
874 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
875 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
876
877
878 /* Audigy Soundcard have a different instruction format */
879 #define A_MICROCODEBASE 0x600
880 #define A_LOWORD_OPY_MASK 0x000007ff
881 #define A_LOWORD_OPX_MASK 0x007ff000
882 #define A_HIWORD_OPCODE_MASK 0x0f000000
883 #define A_HIWORD_RESULT_MASK 0x007ff000
884 #define A_HIWORD_OPA_MASK 0x000007ff
885
886
887 /* ------------------- STRUCTURES -------------------- */
888
889 typedef struct _snd_emu10k1 emu10k1_t;
890 typedef struct _snd_emu10k1_voice emu10k1_voice_t;
891 typedef struct _snd_emu10k1_pcm emu10k1_pcm_t;
892
893 typedef enum {
894 EMU10K1_EFX,
895 EMU10K1_PCM,
896 EMU10K1_SYNTH,
897 EMU10K1_MIDI
898 } emu10k1_voice_type_t;
899
900 struct _snd_emu10k1_voice {
901 emu10k1_t *emu;
902 int number;
903 unsigned int use: 1,
904 pcm: 1,
905 efx: 1,
906 synth: 1,
907 midi: 1;
908 void (*interrupt)(emu10k1_t *emu, emu10k1_voice_t *pvoice);
909
910 emu10k1_pcm_t *epcm;
911 };
912
913 typedef enum {
914 PLAYBACK_EMUVOICE,
915 PLAYBACK_EFX,
916 CAPTURE_AC97ADC,
917 CAPTURE_AC97MIC,
918 CAPTURE_EFX
919 } snd_emu10k1_pcm_type_t;
920
921 struct _snd_emu10k1_pcm {
922 emu10k1_t *emu;
923 snd_emu10k1_pcm_type_t type;
924 snd_pcm_substream_t *substream;
925 emu10k1_voice_t *voices[NUM_EFX_PLAYBACK];
926 emu10k1_voice_t *extra;
927 unsigned short running;
928 unsigned short first_ptr;
929 snd_util_memblk_t *memblk;
930 unsigned int start_addr;
931 unsigned int ccca_start_addr;
932 unsigned int capture_ipr; /* interrupt acknowledge mask */
933 unsigned int capture_inte; /* interrupt enable mask */
934 unsigned int capture_ba_reg; /* buffer address register */
935 unsigned int capture_bs_reg; /* buffer size register */
936 unsigned int capture_idx_reg; /* buffer index register */
937 unsigned int capture_cr_val; /* control value */
938 unsigned int capture_cr_val2; /* control value2 (for audigy) */
939 unsigned int capture_bs_val; /* buffer size value */
940 unsigned int capture_bufsize; /* buffer size in bytes */
941 };
942
943 typedef struct {
944 /* mono, left, right x 8 sends (4 on emu10k1) */
945 unsigned char send_routing[3][8];
946 unsigned char send_volume[3][8];
947 unsigned short attn[3];
948 emu10k1_pcm_t *epcm;
949 } emu10k1_pcm_mixer_t;
950
951 #define snd_emu10k1_compose_send_routing(route) \
952 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
953
954 #define snd_emu10k1_compose_audigy_fxrt1(route) \
955 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
956
957 #define snd_emu10k1_compose_audigy_fxrt2(route) \
958 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
959
960 typedef struct snd_emu10k1_memblk {
961 snd_util_memblk_t mem;
962 /* private part */
963 int first_page, last_page, pages, mapped_page;
964 unsigned int map_locked;
965 struct list_head mapped_link;
966 struct list_head mapped_order_link;
967 } emu10k1_memblk_t;
968
969 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
970
971 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
972
973 typedef struct {
974 struct list_head list; /* list link container */
975 unsigned int vcount;
976 unsigned int count; /* count of GPR (1..16) */
977 unsigned short gpr[32]; /* GPR number(s) */
978 unsigned int value[32];
979 unsigned int min; /* minimum range */
980 unsigned int max; /* maximum range */
981 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
982 snd_kcontrol_t *kcontrol;
983 } snd_emu10k1_fx8010_ctl_t;
984
985 typedef void (snd_fx8010_irq_handler_t)(emu10k1_t *emu, void *private_data);
986
987 typedef struct _snd_emu10k1_fx8010_irq {
988 struct _snd_emu10k1_fx8010_irq *next;
989 snd_fx8010_irq_handler_t *handler;
990 unsigned short gpr_running;
991 void *private_data;
992 } snd_emu10k1_fx8010_irq_t;
993
994 typedef struct {
995 unsigned int valid: 1,
996 opened: 1,
997 active: 1;
998 unsigned int channels; /* 16-bit channels count */
999 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1000 unsigned int buffer_size; /* count of buffered samples */
1001 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1002 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1003 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1004 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1005 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1006 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1007 unsigned char etram[32]; /* external TRAM address & data */
1008 snd_pcm_indirect_t pcm_rec;
1009 unsigned int tram_pos;
1010 unsigned int tram_shift;
1011 snd_emu10k1_fx8010_irq_t *irq;
1012 } snd_emu10k1_fx8010_pcm_t;
1013
1014 typedef struct {
1015 unsigned short fxbus_mask; /* used FX buses (bitmask) */
1016 unsigned short extin_mask; /* used external inputs (bitmask) */
1017 unsigned short extout_mask; /* used external outputs (bitmask) */
1018 unsigned short pad1;
1019 unsigned int itram_size; /* internal TRAM size in samples */
1020 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1021 unsigned int dbg; /* FX debugger register */
1022 unsigned char name[128];
1023 int gpr_size; /* size of allocated GPR controls */
1024 int gpr_count; /* count of used kcontrols */
1025 struct list_head gpr_ctl; /* GPR controls */
1026 struct semaphore lock;
1027 snd_emu10k1_fx8010_pcm_t pcm[8];
1028 spinlock_t irq_lock;
1029 snd_emu10k1_fx8010_irq_t *irq_handlers;
1030 } snd_emu10k1_fx8010_t;
1031
1032 #define emu10k1_gpr_ctl(n) list_entry(n, snd_emu10k1_fx8010_ctl_t, list)
1033
1034 typedef struct {
1035 struct _snd_emu10k1 *emu;
1036 snd_rawmidi_t *rmidi;
1037 snd_rawmidi_substream_t *substream_input;
1038 snd_rawmidi_substream_t *substream_output;
1039 unsigned int midi_mode;
1040 spinlock_t input_lock;
1041 spinlock_t output_lock;
1042 spinlock_t open_lock;
1043 int tx_enable, rx_enable;
1044 int port;
1045 int ipr_tx, ipr_rx;
1046 void (*interrupt)(emu10k1_t *emu, unsigned int status);
1047 } emu10k1_midi_t;
1048
1049 typedef struct {
1050 u32 vendor;
1051 u32 device;
1052 u32 subsystem;
1053 unsigned char revision;
1054 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1055 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1056 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1057 unsigned char ca0108_chip; /* Audigy 2 Value */
1058 unsigned char ca0151_chip; /* P16V */
1059 unsigned char spk71; /* Has 7.1 speakers */
1060 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1061 unsigned char spdif_bug; /* Has Spdif phasing bug */
1062 unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1063 unsigned char ecard; /* APS EEPROM */
1064 const char *driver;
1065 const char *name;
1066 const char *id; /* for backward compatibility - can be NULL if not needed */
1067 } emu_chip_details_t;
1068
1069 struct _snd_emu10k1 {
1070 int irq;
1071
1072 unsigned long port; /* I/O port number */
1073 unsigned int tos_link: 1, /* tos link detected */
1074 rear_ac97: 1; /* rear channels are on AC'97 */
1075 const emu_chip_details_t *card_capabilities; /* Contains profile of card capabilities */
1076 unsigned int audigy; /* is Audigy? */
1077 unsigned int revision; /* chip revision */
1078 unsigned int serial; /* serial number */
1079 unsigned short model; /* subsystem id */
1080 unsigned int card_type; /* EMU10K1_CARD_* */
1081 unsigned int ecard_ctrl; /* ecard control bits */
1082 unsigned long dma_mask; /* PCI DMA mask */
1083 int max_cache_pages; /* max memory size / PAGE_SIZE */
1084 struct snd_dma_buffer silent_page; /* silent page */
1085 struct snd_dma_buffer ptb_pages; /* page table pages */
1086 struct snd_dma_device p16v_dma_dev;
1087 struct snd_dma_buffer p16v_buffer;
1088
1089 snd_util_memhdr_t *memhdr; /* page allocation list */
1090 emu10k1_memblk_t *reserved_page; /* reserved page */
1091
1092 struct list_head mapped_link_head;
1093 struct list_head mapped_order_link_head;
1094 void **page_ptr_table;
1095 unsigned long *page_addr_table;
1096 spinlock_t memblk_lock;
1097
1098 unsigned int spdif_bits[3]; /* s/pdif out setup */
1099
1100 snd_emu10k1_fx8010_t fx8010; /* FX8010 info */
1101 int gpr_base;
1102
1103 ac97_t *ac97;
1104
1105 struct pci_dev *pci;
1106 snd_card_t *card;
1107 snd_pcm_t *pcm;
1108 snd_pcm_t *pcm_mic;
1109 snd_pcm_t *pcm_efx;
1110 snd_pcm_t *pcm_p16v;
1111
1112 spinlock_t synth_lock;
1113 void *synth;
1114 int (*get_synth_voice)(emu10k1_t *emu);
1115
1116 spinlock_t reg_lock;
1117 spinlock_t emu_lock;
1118 spinlock_t voice_lock;
1119 struct semaphore ptb_lock;
1120
1121 emu10k1_voice_t voices[NUM_G];
1122 emu10k1_voice_t p16v_voices[4];
1123 emu10k1_voice_t p16v_capture_voice;
1124 int p16v_device_offset;
1125 u32 p16v_capture_source;
1126 u32 p16v_capture_channel;
1127 emu10k1_pcm_mixer_t pcm_mixer[32];
1128 emu10k1_pcm_mixer_t efx_pcm_mixer[NUM_EFX_PLAYBACK];
1129 snd_kcontrol_t *ctl_send_routing;
1130 snd_kcontrol_t *ctl_send_volume;
1131 snd_kcontrol_t *ctl_attn;
1132 snd_kcontrol_t *ctl_efx_send_routing;
1133 snd_kcontrol_t *ctl_efx_send_volume;
1134 snd_kcontrol_t *ctl_efx_attn;
1135
1136 void (*hwvol_interrupt)(emu10k1_t *emu, unsigned int status);
1137 void (*capture_interrupt)(emu10k1_t *emu, unsigned int status);
1138 void (*capture_mic_interrupt)(emu10k1_t *emu, unsigned int status);
1139 void (*capture_efx_interrupt)(emu10k1_t *emu, unsigned int status);
1140 void (*spdif_interrupt)(emu10k1_t *emu, unsigned int status);
1141 void (*dsp_interrupt)(emu10k1_t *emu);
1142
1143 snd_pcm_substream_t *pcm_capture_substream;
1144 snd_pcm_substream_t *pcm_capture_mic_substream;
1145 snd_pcm_substream_t *pcm_capture_efx_substream;
1146 snd_pcm_substream_t *pcm_playback_efx_substream;
1147
1148 snd_timer_t *timer;
1149
1150 emu10k1_midi_t midi;
1151 emu10k1_midi_t midi2; /* for audigy */
1152
1153 unsigned int efx_voices_mask[2];
1154 unsigned int next_free_voice;
1155 };
1156
1157 int snd_emu10k1_create(snd_card_t * card,
1158 struct pci_dev *pci,
1159 unsigned short extin_mask,
1160 unsigned short extout_mask,
1161 long max_cache_bytes,
1162 int enable_ir,
1163 uint subsystem,
1164 emu10k1_t ** remu);
1165
1166 int snd_emu10k1_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1167 int snd_emu10k1_pcm_mic(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1168 int snd_emu10k1_pcm_efx(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1169 int snd_p16v_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1170 int snd_p16v_free(emu10k1_t * emu);
1171 int snd_p16v_mixer(emu10k1_t * emu);
1172 int snd_emu10k1_pcm_multi(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1173 int snd_emu10k1_fx8010_pcm(emu10k1_t * emu, int device, snd_pcm_t ** rpcm);
1174 int snd_emu10k1_mixer(emu10k1_t * emu, int pcm_device, int multi_device);
1175 int snd_emu10k1_timer(emu10k1_t * emu, int device);
1176 int snd_emu10k1_fx8010_new(emu10k1_t *emu, int device, snd_hwdep_t ** rhwdep);
1177
1178 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id, struct pt_regs *regs);
1179
1180 /* initialization */
1181 void snd_emu10k1_voice_init(emu10k1_t * emu, int voice);
1182 int snd_emu10k1_init_efx(emu10k1_t *emu);
1183 void snd_emu10k1_free_efx(emu10k1_t *emu);
1184 int snd_emu10k1_fx8010_tram_setup(emu10k1_t *emu, u32 size);
1185
1186 /* I/O functions */
1187 unsigned int snd_emu10k1_ptr_read(emu10k1_t * emu, unsigned int reg, unsigned int chn);
1188 void snd_emu10k1_ptr_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data);
1189 unsigned int snd_emu10k1_ptr20_read(emu10k1_t * emu, unsigned int reg, unsigned int chn);
1190 void snd_emu10k1_ptr20_write(emu10k1_t *emu, unsigned int reg, unsigned int chn, unsigned int data);
1191 unsigned int snd_emu10k1_efx_read(emu10k1_t *emu, unsigned int pc);
1192 void snd_emu10k1_intr_enable(emu10k1_t *emu, unsigned int intrenb);
1193 void snd_emu10k1_intr_disable(emu10k1_t *emu, unsigned int intrenb);
1194 void snd_emu10k1_voice_intr_enable(emu10k1_t *emu, unsigned int voicenum);
1195 void snd_emu10k1_voice_intr_disable(emu10k1_t *emu, unsigned int voicenum);
1196 void snd_emu10k1_voice_intr_ack(emu10k1_t *emu, unsigned int voicenum);
1197 void snd_emu10k1_voice_half_loop_intr_enable(emu10k1_t *emu, unsigned int voicenum);
1198 void snd_emu10k1_voice_half_loop_intr_disable(emu10k1_t *emu, unsigned int voicenum);
1199 void snd_emu10k1_voice_half_loop_intr_ack(emu10k1_t *emu, unsigned int voicenum);
1200 void snd_emu10k1_voice_set_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1201 void snd_emu10k1_voice_clear_loop_stop(emu10k1_t *emu, unsigned int voicenum);
1202 void snd_emu10k1_wait(emu10k1_t *emu, unsigned int wait);
1203 static inline unsigned int snd_emu10k1_wc(emu10k1_t *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1204 unsigned short snd_emu10k1_ac97_read(ac97_t *ac97, unsigned short reg);
1205 void snd_emu10k1_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short data);
1206 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1207
1208 /* memory allocation */
1209 snd_util_memblk_t *snd_emu10k1_alloc_pages(emu10k1_t *emu, snd_pcm_substream_t *substream);
1210 int snd_emu10k1_free_pages(emu10k1_t *emu, snd_util_memblk_t *blk);
1211 snd_util_memblk_t *snd_emu10k1_synth_alloc(emu10k1_t *emu, unsigned int size);
1212 int snd_emu10k1_synth_free(emu10k1_t *emu, snd_util_memblk_t *blk);
1213 int snd_emu10k1_synth_bzero(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, int size);
1214 int snd_emu10k1_synth_copy_from_user(emu10k1_t *emu, snd_util_memblk_t *blk, int offset, const char __user *data, int size);
1215 int snd_emu10k1_memblk_map(emu10k1_t *emu, emu10k1_memblk_t *blk);
1216
1217 /* voice allocation */
1218 int snd_emu10k1_voice_alloc(emu10k1_t *emu, emu10k1_voice_type_t type, int pair, emu10k1_voice_t **rvoice);
1219 int snd_emu10k1_voice_free(emu10k1_t *emu, emu10k1_voice_t *pvoice);
1220
1221 /* MIDI uart */
1222 int snd_emu10k1_midi(emu10k1_t * emu);
1223 int snd_emu10k1_audigy_midi(emu10k1_t * emu);
1224
1225 /* proc interface */
1226 int snd_emu10k1_proc_init(emu10k1_t * emu);
1227
1228 /* fx8010 irq handler */
1229 int snd_emu10k1_fx8010_register_irq_handler(emu10k1_t *emu,
1230 snd_fx8010_irq_handler_t *handler,
1231 unsigned char gpr_running,
1232 void *private_data,
1233 snd_emu10k1_fx8010_irq_t **r_irq);
1234 int snd_emu10k1_fx8010_unregister_irq_handler(emu10k1_t *emu,
1235 snd_emu10k1_fx8010_irq_t *irq);
1236
1237 #endif /* __KERNEL__ */
1238
1239 /*
1240 * ---- FX8010 ----
1241 */
1242
1243 #define EMU10K1_CARD_CREATIVE 0x00000000
1244 #define EMU10K1_CARD_EMUAPS 0x00000001
1245
1246 #define EMU10K1_FX8010_PCM_COUNT 8
1247
1248 /* instruction set */
1249 #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
1250 #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
1251 #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
1252 #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
1253 #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
1254 #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
1255 #define iACC3 0x06 /* R = A + X + Y ; saturation */
1256 #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
1257 #define iANDXOR 0x08 /* R = (A & X) ^ Y */
1258 #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
1259 #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
1260 #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
1261 #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
1262 #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
1263 #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
1264 #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
1265
1266 /* GPRs */
1267 #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
1268 #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
1269 #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
1270 #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
1271 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
1272
1273 #define C_00000000 0x40
1274 #define C_00000001 0x41
1275 #define C_00000002 0x42
1276 #define C_00000003 0x43
1277 #define C_00000004 0x44
1278 #define C_00000008 0x45
1279 #define C_00000010 0x46
1280 #define C_00000020 0x47
1281 #define C_00000100 0x48
1282 #define C_00010000 0x49
1283 #define C_00080000 0x4a
1284 #define C_10000000 0x4b
1285 #define C_20000000 0x4c
1286 #define C_40000000 0x4d
1287 #define C_80000000 0x4e
1288 #define C_7fffffff 0x4f
1289 #define C_ffffffff 0x50
1290 #define C_fffffffe 0x51
1291 #define C_c0000000 0x52
1292 #define C_4f1bbcdc 0x53
1293 #define C_5a7ef9db 0x54
1294 #define C_00100000 0x55 /* ?? */
1295 #define GPR_ACCU 0x56 /* ACCUM, accumulator */
1296 #define GPR_COND 0x57 /* CCR, condition register */
1297 #define GPR_NOISE0 0x58 /* noise source */
1298 #define GPR_NOISE1 0x59 /* noise source */
1299 #define GPR_IRQ 0x5a /* IRQ register */
1300 #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
1301 #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
1302 #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1303 #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1304 #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
1305 #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
1306
1307 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1308 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1309 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1310 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1311 #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
1312 #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
1313
1314 #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
1315 #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
1316 #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
1317 #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
1318 #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
1319 #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
1320 #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
1321 #define A_GPR(x) (A_FXGPREGBASE + (x))
1322
1323 /* cc_reg constants */
1324 #define CC_REG_NORMALIZED C_00000001
1325 #define CC_REG_BORROW C_00000002
1326 #define CC_REG_MINUS C_00000004
1327 #define CC_REG_ZERO C_00000008
1328 #define CC_REG_SATURATE C_00000010
1329 #define CC_REG_NONZERO C_00000100
1330
1331 /* FX buses */
1332 #define FXBUS_PCM_LEFT 0x00
1333 #define FXBUS_PCM_RIGHT 0x01
1334 #define FXBUS_PCM_LEFT_REAR 0x02
1335 #define FXBUS_PCM_RIGHT_REAR 0x03
1336 #define FXBUS_MIDI_LEFT 0x04
1337 #define FXBUS_MIDI_RIGHT 0x05
1338 #define FXBUS_PCM_CENTER 0x06
1339 #define FXBUS_PCM_LFE 0x07
1340 #define FXBUS_PCM_LEFT_FRONT 0x08
1341 #define FXBUS_PCM_RIGHT_FRONT 0x09
1342 #define FXBUS_MIDI_REVERB 0x0c
1343 #define FXBUS_MIDI_CHORUS 0x0d
1344 #define FXBUS_PCM_LEFT_SIDE 0x0e
1345 #define FXBUS_PCM_RIGHT_SIDE 0x0f
1346 #define FXBUS_PT_LEFT 0x14
1347 #define FXBUS_PT_RIGHT 0x15
1348
1349 /* Inputs */
1350 #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1351 #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1352 #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
1353 #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
1354 #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
1355 #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
1356 #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
1357 #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
1358 #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
1359 #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
1360 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
1361 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
1362 #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
1363 #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
1364
1365 /* Outputs */
1366 #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
1367 #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
1368 #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
1369 #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
1370 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
1371 #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
1372 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
1373 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
1374 #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
1375 #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
1376 #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
1377 #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
1378 #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
1379 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
1380 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
1381 #define EXTOUT_ACENTER 0x11 /* Analog Center */
1382 #define EXTOUT_ALFE 0x12 /* Analog LFE */
1383
1384 /* Audigy Inputs */
1385 #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
1386 #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
1387 #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
1388 #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
1389 #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
1390 #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
1391 #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
1392 #define A_EXTIN_LINE2_R 0x09 /* right */
1393 #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
1394 #define A_EXTIN_ADC_R 0x0b /* right */
1395 #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
1396 #define A_EXTIN_AUX2_R 0x0d /* - right */
1397
1398 /* Audigiy Outputs */
1399 #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
1400 #define A_EXTOUT_FRONT_R 0x01 /* right */
1401 #define A_EXTOUT_CENTER 0x02 /* digital front center */
1402 #define A_EXTOUT_LFE 0x03 /* digital front lfe */
1403 #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
1404 #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
1405 #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
1406 #define A_EXTOUT_REAR_R 0x07 /* right */
1407 #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
1408 #define A_EXTOUT_AFRONT_R 0x09 /* right */
1409 #define A_EXTOUT_ACENTER 0x0a /* analog center */
1410 #define A_EXTOUT_ALFE 0x0b /* analog LFE */
1411 #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
1412 #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
1413 #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
1414 #define A_EXTOUT_AREAR_R 0x0f /* right */
1415 #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
1416 #define A_EXTOUT_AC97_R 0x11 /* right */
1417 #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
1418 #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
1419 #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
1420
1421 /* Audigy constants */
1422 #define A_C_00000000 0xc0
1423 #define A_C_00000001 0xc1
1424 #define A_C_00000002 0xc2
1425 #define A_C_00000003 0xc3
1426 #define A_C_00000004 0xc4
1427 #define A_C_00000008 0xc5
1428 #define A_C_00000010 0xc6
1429 #define A_C_00000020 0xc7
1430 #define A_C_00000100 0xc8
1431 #define A_C_00010000 0xc9
1432 #define A_C_00000800 0xca
1433 #define A_C_10000000 0xcb
1434 #define A_C_20000000 0xcc
1435 #define A_C_40000000 0xcd
1436 #define A_C_80000000 0xce
1437 #define A_C_7fffffff 0xcf
1438 #define A_C_ffffffff 0xd0
1439 #define A_C_fffffffe 0xd1
1440 #define A_C_c0000000 0xd2
1441 #define A_C_4f1bbcdc 0xd3
1442 #define A_C_5a7ef9db 0xd4
1443 #define A_C_00100000 0xd5
1444 #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
1445 #define A_GPR_COND 0xd7 /* CCR, condition register */
1446 #define A_GPR_NOISE0 0xd8 /* noise source */
1447 #define A_GPR_NOISE1 0xd9 /* noise source */
1448 #define A_GPR_IRQ 0xda /* IRQ register */
1449 #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
1450 #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
1451
1452 /* definitions for debug register */
1453 #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
1454 #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
1455 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
1456 #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
1457 #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
1458 #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
1459 #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
1460
1461 /* tank memory address line */
1462 #ifndef __KERNEL__
1463 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
1464 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
1465 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
1466 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
1467 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
1468 #endif
1469
1470 typedef struct {
1471 unsigned int internal_tram_size; /* in samples */
1472 unsigned int external_tram_size; /* in samples */
1473 char fxbus_names[16][32]; /* names of FXBUSes */
1474 char extin_names[16][32]; /* names of external inputs */
1475 char extout_names[32][32]; /* names of external outputs */
1476 unsigned int gpr_controls; /* count of GPR controls */
1477 } emu10k1_fx8010_info_t;
1478
1479 #define EMU10K1_GPR_TRANSLATION_NONE 0
1480 #define EMU10K1_GPR_TRANSLATION_TABLE100 1
1481 #define EMU10K1_GPR_TRANSLATION_BASS 2
1482 #define EMU10K1_GPR_TRANSLATION_TREBLE 3
1483 #define EMU10K1_GPR_TRANSLATION_ONOFF 4
1484
1485 typedef struct {
1486 snd_ctl_elem_id_t id; /* full control ID definition */
1487 unsigned int vcount; /* visible count */
1488 unsigned int count; /* count of GPR (1..16) */
1489 unsigned short gpr[32]; /* GPR number(s) */
1490 unsigned int value[32]; /* initial values */
1491 unsigned int min; /* minimum range */
1492 unsigned int max; /* maximum range */
1493 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1494 } emu10k1_fx8010_control_gpr_t;
1495
1496 typedef struct {
1497 char name[128];
1498
1499 DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
1500 u_int32_t __user *gpr_map; /* initializers */
1501
1502 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
1503 emu10k1_fx8010_control_gpr_t __user *gpr_add_controls; /* GPR controls to add/replace */
1504
1505 unsigned int gpr_del_control_count; /* count of GPR controls to remove */
1506 snd_ctl_elem_id_t __user *gpr_del_controls; /* IDs of GPR controls to remove */
1507
1508 unsigned int gpr_list_control_count; /* count of GPR controls to list */
1509 unsigned int gpr_list_control_total; /* total count of GPR controls */
1510 emu10k1_fx8010_control_gpr_t __user *gpr_list_controls; /* listed GPR controls */
1511
1512 DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
1513 u_int32_t __user *tram_data_map; /* data initializers */
1514 u_int32_t __user *tram_addr_map; /* map initializers */
1515
1516 DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
1517 u_int32_t __user *code; /* one instruction - 64 bits */
1518 } emu10k1_fx8010_code_t;
1519
1520 typedef struct {
1521 unsigned int address; /* 31.bit == 1 -> external TRAM */
1522 unsigned int size; /* size in samples (4 bytes) */
1523 unsigned int *samples; /* pointer to samples (20-bit) */
1524 /* NULL->clear memory */
1525 } emu10k1_fx8010_tram_t;
1526
1527 typedef struct {
1528 unsigned int substream; /* substream number */
1529 unsigned int res1; /* reserved */
1530 unsigned int channels; /* 16-bit channels count, zero = remove this substream */
1531 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
1532 unsigned int buffer_size; /* count of buffered samples */
1533 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
1534 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1535 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1536 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1537 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1538 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1539 unsigned char pad; /* reserved */
1540 unsigned char etram[32]; /* external TRAM address & data (one per channel) */
1541 unsigned int res2; /* reserved */
1542 } emu10k1_fx8010_pcm_t;
1543
1544 #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, emu10k1_fx8010_info_t)
1545 #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, emu10k1_fx8010_code_t)
1546 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, emu10k1_fx8010_code_t)
1547 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
1548 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, emu10k1_fx8010_tram_t)
1549 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, emu10k1_fx8010_tram_t)
1550 #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, emu10k1_fx8010_pcm_t)
1551 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, emu10k1_fx8010_pcm_t)
1552 #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
1553 #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
1554 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
1555 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
1556 #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
1557
1558 #endif /* __SOUND_EMU10K1_H */
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