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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / block / cpqarray.c
blob6422651ec364197ed9418f4a3bafb966208a8417
1 /*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/pci.h>
25 #include <linux/bio.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/major.h>
31 #include <linux/fs.h>
32 #include <linux/blkpg.h>
33 #include <linux/timer.h>
34 #include <linux/proc_fs.h>
35 #include <linux/seq_file.h>
36 #include <linux/init.h>
37 #include <linux/hdreg.h>
38 #include <linux/spinlock.h>
39 #include <linux/blkdev.h>
40 #include <linux/genhd.h>
41 #include <linux/scatterlist.h>
42 #include <asm/uaccess.h>
43 #include <asm/io.h>
44
45
46 #define SMART2_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
47
48 #define DRIVER_NAME "Compaq SMART2 Driver (v 2.6.0)"
49 #define DRIVER_VERSION SMART2_DRIVER_VERSION(2,6,0)
50
51 /* Embedded module documentation macros - see modules.h */
52 /* Original author Chris Frantz - Compaq Computer Corporation */
53 MODULE_AUTHOR("Compaq Computer Corporation");
54 MODULE_DESCRIPTION("Driver for Compaq Smart2 Array Controllers version 2.6.0");
55 MODULE_LICENSE("GPL");
56
57 #include "cpqarray.h"
58 #include "ida_cmd.h"
59 #include "smart1,2.h"
60 #include "ida_ioctl.h"
61
62 #define READ_AHEAD 128
63 #define NR_CMDS 128 /* This could probably go as high as ~400 */
64
65 #define MAX_CTLR 8
66 #define CTLR_SHIFT 8
67
68 #define CPQARRAY_DMA_MASK 0xFFFFFFFF /* 32 bit DMA */
69
70 static int nr_ctlr;
71 static ctlr_info_t *hba[MAX_CTLR];
72
73 static int eisa[8];
74
75 #define NR_PRODUCTS ARRAY_SIZE(products)
76
77 /* board_id = Subsystem Device ID & Vendor ID
78 * product = Marketing Name for the board
79 * access = Address of the struct of function pointers
80 */
81 static struct board_type products[] = {
82 { 0x0040110E, "IDA", &smart1_access },
83 { 0x0140110E, "IDA-2", &smart1_access },
84 { 0x1040110E, "IAES", &smart1_access },
85 { 0x2040110E, "SMART", &smart1_access },
86 { 0x3040110E, "SMART-2/E", &smart2e_access },
87 { 0x40300E11, "SMART-2/P", &smart2_access },
88 { 0x40310E11, "SMART-2SL", &smart2_access },
89 { 0x40320E11, "Smart Array 3200", &smart2_access },
90 { 0x40330E11, "Smart Array 3100ES", &smart2_access },
91 { 0x40340E11, "Smart Array 221", &smart2_access },
92 { 0x40400E11, "Integrated Array", &smart4_access },
93 { 0x40480E11, "Compaq Raid LC2", &smart4_access },
94 { 0x40500E11, "Smart Array 4200", &smart4_access },
95 { 0x40510E11, "Smart Array 4250ES", &smart4_access },
96 { 0x40580E11, "Smart Array 431", &smart4_access },
97 };
98
99 /* define the PCI info for the PCI cards this driver can control */
100 static const struct pci_device_id cpqarray_pci_device_id[] =
101 {
102 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
103 0x0E11, 0x4058, 0, 0, 0}, /* SA431 */
104 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
105 0x0E11, 0x4051, 0, 0, 0}, /* SA4250ES */
106 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
107 0x0E11, 0x4050, 0, 0, 0}, /* SA4200 */
108 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
109 0x0E11, 0x4048, 0, 0, 0}, /* LC2 */
110 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
111 0x0E11, 0x4040, 0, 0, 0}, /* Integrated Array */
112 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
113 0x0E11, 0x4034, 0, 0, 0}, /* SA 221 */
114 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
115 0x0E11, 0x4033, 0, 0, 0}, /* SA 3100ES*/
116 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
117 0x0E11, 0x4032, 0, 0, 0}, /* SA 3200*/
118 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
119 0x0E11, 0x4031, 0, 0, 0}, /* SA 2SL*/
120 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
121 0x0E11, 0x4030, 0, 0, 0}, /* SA 2P */
122 { 0 }
123 };
124
125 MODULE_DEVICE_TABLE(pci, cpqarray_pci_device_id);
126
127 static struct gendisk *ida_gendisk[MAX_CTLR][NWD];
128
129 /* Debug... */
130 #define DBG(s) do { s } while(0)
131 /* Debug (general info)... */
132 #define DBGINFO(s) do { } while(0)
133 /* Debug Paranoid... */
134 #define DBGP(s) do { } while(0)
135 /* Debug Extra Paranoid... */
136 #define DBGPX(s) do { } while(0)
137
138 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev);
139 static void __iomem *remap_pci_mem(ulong base, ulong size);
140 static int cpqarray_eisa_detect(void);
141 static int pollcomplete(int ctlr);
142 static void getgeometry(int ctlr);
143 static void start_fwbk(int ctlr);
144
145 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool);
146 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool);
147
148 static void free_hba(int i);
149 static int alloc_cpqarray_hba(void);
150
151 static int sendcmd(
152 __u8 cmd,
153 int ctlr,
154 void *buff,
155 size_t size,
156 unsigned int blk,
157 unsigned int blkcnt,
158 unsigned int log_unit );
159
160 static int ida_open(struct block_device *bdev, fmode_t mode);
161 static int ida_release(struct gendisk *disk, fmode_t mode);
162 static int ida_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, unsigned long arg);
163 static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo);
164 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io);
165
166 static void do_ida_request(struct request_queue *q);
167 static void start_io(ctlr_info_t *h);
168
169 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c);
170 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c);
171 static inline void complete_command(cmdlist_t *cmd, int timeout);
172
173 static irqreturn_t do_ida_intr(int irq, void *dev_id);
174 static void ida_timer(unsigned long tdata);
175 static int ida_revalidate(struct gendisk *disk);
176 static int revalidate_allvol(ctlr_info_t *host);
177 static int cpqarray_register_ctlr(int ctlr, struct pci_dev *pdev);
178
179 #ifdef CONFIG_PROC_FS
180 static void ida_procinit(int i);
181 #else
182 static void ida_procinit(int i) {}
183 #endif
184
185 static inline drv_info_t *get_drv(struct gendisk *disk)
186 {
187 return disk->private_data;
188 }
189
190 static inline ctlr_info_t *get_host(struct gendisk *disk)
191 {
192 return disk->queue->queuedata;
193 }
194
195
196 static const struct block_device_operations ida_fops = {
197 .owner = THIS_MODULE,
198 .open = ida_open,
199 .release = ida_release,
200 .locked_ioctl = ida_ioctl,
201 .getgeo = ida_getgeo,
202 .revalidate_disk= ida_revalidate,
203 };
204
205
206 #ifdef CONFIG_PROC_FS
207
208 static struct proc_dir_entry *proc_array;
209 static const struct file_operations ida_proc_fops;
210
211 /*
212 * Get us a file in /proc/array that says something about each controller.
213 * Create /proc/array if it doesn't exist yet.
214 */
215 static void __init ida_procinit(int i)
216 {
217 if (proc_array == NULL) {
218 proc_array = proc_mkdir("driver/cpqarray", NULL);
219 if (!proc_array) return;
220 }
221
222 proc_create_data(hba[i]->devname, 0, proc_array, &ida_proc_fops, hba[i]);
223 }
224
225 /*
226 * Report information about this controller.
227 */
228 static int ida_proc_show(struct seq_file *m, void *v)
229 {
230 int i, ctlr;
231 ctlr_info_t *h = (ctlr_info_t*)m->private;
232 drv_info_t *drv;
233 #ifdef CPQ_PROC_PRINT_QUEUES
234 cmdlist_t *c;
235 unsigned long flags;
236 #endif
237
238 ctlr = h->ctlr;
239 seq_printf(m, "%s: Compaq %s Controller\n"
240 " Board ID: 0x%08lx\n"
241 " Firmware Revision: %c%c%c%c\n"
242 " Controller Sig: 0x%08lx\n"
243 " Memory Address: 0x%08lx\n"
244 " I/O Port: 0x%04x\n"
245 " IRQ: %d\n"
246 " Logical drives: %d\n"
247 " Physical drives: %d\n\n"
248 " Current Q depth: %d\n"
249 " Max Q depth since init: %d\n\n",
250 h->devname,
251 h->product_name,
252 (unsigned long)h->board_id,
253 h->firm_rev[0], h->firm_rev[1], h->firm_rev[2], h->firm_rev[3],
254 (unsigned long)h->ctlr_sig, (unsigned long)h->vaddr,
255 (unsigned int) h->io_mem_addr, (unsigned int)h->intr,
256 h->log_drives, h->phys_drives,
257 h->Qdepth, h->maxQsinceinit);
258
259 seq_puts(m, "Logical Drive Info:\n");
260
261 for(i=0; i<h->log_drives; i++) {
262 drv = &h->drv[i];
263 seq_printf(m, "ida/c%dd%d: blksz=%d nr_blks=%d\n",
264 ctlr, i, drv->blk_size, drv->nr_blks);
265 }
266
267 #ifdef CPQ_PROC_PRINT_QUEUES
268 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
269 seq_puts(m, "\nCurrent Queues:\n");
270
271 c = h->reqQ;
272 seq_printf(m, "reqQ = %p", c);
273 if (c) c=c->next;
274 while(c && c != h->reqQ) {
275 seq_printf(m, "->%p", c);
276 c=c->next;
277 }
278
279 c = h->cmpQ;
280 seq_printf(m, "\ncmpQ = %p", c);
281 if (c) c=c->next;
282 while(c && c != h->cmpQ) {
283 seq_printf(m, "->%p", c);
284 c=c->next;
285 }
286
287 seq_putc(m, '\n');
288 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
289 #endif
290 seq_printf(m, "nr_allocs = %d\nnr_frees = %d\n",
291 h->nr_allocs, h->nr_frees);
292 return 0;
293 }
294
295 static int ida_proc_open(struct inode *inode, struct file *file)
296 {
297 return single_open(file, ida_proc_show, PDE(inode)->data);
298 }
299
300 static const struct file_operations ida_proc_fops = {
301 .owner = THIS_MODULE,
302 .open = ida_proc_open,
303 .read = seq_read,
304 .llseek = seq_lseek,
305 .release = single_release,
306 };
307 #endif /* CONFIG_PROC_FS */
308
309 module_param_array(eisa, int, NULL, 0);
310
311 static void release_io_mem(ctlr_info_t *c)
312 {
313 /* if IO mem was not protected do nothing */
314 if( c->io_mem_addr == 0)
315 return;
316 release_region(c->io_mem_addr, c->io_mem_length);
317 c->io_mem_addr = 0;
318 c->io_mem_length = 0;
319 }
320
321 static void __devexit cpqarray_remove_one(int i)
322 {
323 int j;
324 char buff[4];
325
326 /* sendcmd will turn off interrupt, and send the flush...
327 * To write all data in the battery backed cache to disks
328 * no data returned, but don't want to send NULL to sendcmd */
329 if( sendcmd(FLUSH_CACHE, i, buff, 4, 0, 0, 0))
330 {
331 printk(KERN_WARNING "Unable to flush cache on controller %d\n",
332 i);
333 }
334 free_irq(hba[i]->intr, hba[i]);
335 iounmap(hba[i]->vaddr);
336 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
337 del_timer(&hba[i]->timer);
338 remove_proc_entry(hba[i]->devname, proc_array);
339 pci_free_consistent(hba[i]->pci_dev,
340 NR_CMDS * sizeof(cmdlist_t), (hba[i]->cmd_pool),
341 hba[i]->cmd_pool_dhandle);
342 kfree(hba[i]->cmd_pool_bits);
343 for(j = 0; j < NWD; j++) {
344 if (ida_gendisk[i][j]->flags & GENHD_FL_UP)
345 del_gendisk(ida_gendisk[i][j]);
346 put_disk(ida_gendisk[i][j]);
347 }
348 blk_cleanup_queue(hba[i]->queue);
349 release_io_mem(hba[i]);
350 free_hba(i);
351 }
352
353 static void __devexit cpqarray_remove_one_pci (struct pci_dev *pdev)
354 {
355 int i;
356 ctlr_info_t *tmp_ptr;
357
358 if (pci_get_drvdata(pdev) == NULL) {
359 printk( KERN_ERR "cpqarray: Unable to remove device \n");
360 return;
361 }
362
363 tmp_ptr = pci_get_drvdata(pdev);
364 i = tmp_ptr->ctlr;
365 if (hba[i] == NULL) {
366 printk(KERN_ERR "cpqarray: controller %d appears to have"
367 "already been removed \n", i);
368 return;
369 }
370 pci_set_drvdata(pdev, NULL);
371
372 cpqarray_remove_one(i);
373 }
374
375 /* removing an instance that was not removed automatically..
376 * must be an eisa card.
377 */
378 static void __devexit cpqarray_remove_one_eisa (int i)
379 {
380 if (hba[i] == NULL) {
381 printk(KERN_ERR "cpqarray: controller %d appears to have"
382 "already been removed \n", i);
383 return;
384 }
385 cpqarray_remove_one(i);
386 }
387
388 /* pdev is NULL for eisa */
389 static int __init cpqarray_register_ctlr( int i, struct pci_dev *pdev)
390 {
391 struct request_queue *q;
392 int j;
393
394 /*
395 * register block devices
396 * Find disks and fill in structs
397 * Get an interrupt, set the Q depth and get into /proc
398 */
399
400 /* If this successful it should insure that we are the only */
401 /* instance of the driver */
402 if (register_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname)) {
403 goto Enomem4;
404 }
405 hba[i]->access.set_intr_mask(hba[i], 0);
406 if (request_irq(hba[i]->intr, do_ida_intr,
407 IRQF_DISABLED|IRQF_SHARED, hba[i]->devname, hba[i]))
408 {
409 printk(KERN_ERR "cpqarray: Unable to get irq %d for %s\n",
410 hba[i]->intr, hba[i]->devname);
411 goto Enomem3;
412 }
413
414 for (j=0; j<NWD; j++) {
415 ida_gendisk[i][j] = alloc_disk(1 << NWD_SHIFT);
416 if (!ida_gendisk[i][j])
417 goto Enomem2;
418 }
419
420 hba[i]->cmd_pool = pci_alloc_consistent(
421 hba[i]->pci_dev, NR_CMDS * sizeof(cmdlist_t),
422 &(hba[i]->cmd_pool_dhandle));
423 hba[i]->cmd_pool_bits = kcalloc(
424 DIV_ROUND_UP(NR_CMDS, BITS_PER_LONG), sizeof(unsigned long),
425 GFP_KERNEL);
426
427 if (!hba[i]->cmd_pool_bits || !hba[i]->cmd_pool)
428 goto Enomem1;
429
430 memset(hba[i]->cmd_pool, 0, NR_CMDS * sizeof(cmdlist_t));
431 printk(KERN_INFO "cpqarray: Finding drives on %s",
432 hba[i]->devname);
433
434 spin_lock_init(&hba[i]->lock);
435 q = blk_init_queue(do_ida_request, &hba[i]->lock);
436 if (!q)
437 goto Enomem1;
438
439 hba[i]->queue = q;
440 q->queuedata = hba[i];
441
442 getgeometry(i);
443 start_fwbk(i);
444
445 ida_procinit(i);
446
447 if (pdev)
448 blk_queue_bounce_limit(q, hba[i]->pci_dev->dma_mask);
449
450 /* This is a hardware imposed limit. */
451 blk_queue_max_hw_segments(q, SG_MAX);
452
453 /* This is a driver limit and could be eliminated. */
454 blk_queue_max_phys_segments(q, SG_MAX);
455
456 init_timer(&hba[i]->timer);
457 hba[i]->timer.expires = jiffies + IDA_TIMER;
458 hba[i]->timer.data = (unsigned long)hba[i];
459 hba[i]->timer.function = ida_timer;
460 add_timer(&hba[i]->timer);
461
462 /* Enable IRQ now that spinlock and rate limit timer are set up */
463 hba[i]->access.set_intr_mask(hba[i], FIFO_NOT_EMPTY);
464
465 for(j=0; j<NWD; j++) {
466 struct gendisk *disk = ida_gendisk[i][j];
467 drv_info_t *drv = &hba[i]->drv[j];
468 sprintf(disk->disk_name, "ida/c%dd%d", i, j);
469 disk->major = COMPAQ_SMART2_MAJOR + i;
470 disk->first_minor = j<<NWD_SHIFT;
471 disk->fops = &ida_fops;
472 if (j && !drv->nr_blks)
473 continue;
474 blk_queue_logical_block_size(hba[i]->queue, drv->blk_size);
475 set_capacity(disk, drv->nr_blks);
476 disk->queue = hba[i]->queue;
477 disk->private_data = drv;
478 add_disk(disk);
479 }
480
481 /* done ! */
482 return(i);
483
484 Enomem1:
485 nr_ctlr = i;
486 kfree(hba[i]->cmd_pool_bits);
487 if (hba[i]->cmd_pool)
488 pci_free_consistent(hba[i]->pci_dev, NR_CMDS*sizeof(cmdlist_t),
489 hba[i]->cmd_pool, hba[i]->cmd_pool_dhandle);
490 Enomem2:
491 while (j--) {
492 put_disk(ida_gendisk[i][j]);
493 ida_gendisk[i][j] = NULL;
494 }
495 free_irq(hba[i]->intr, hba[i]);
496 Enomem3:
497 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
498 Enomem4:
499 if (pdev)
500 pci_set_drvdata(pdev, NULL);
501 release_io_mem(hba[i]);
502 free_hba(i);
503
504 printk( KERN_ERR "cpqarray: out of memory");
505
506 return -1;
507 }
508
509 static int __init cpqarray_init_one( struct pci_dev *pdev,
510 const struct pci_device_id *ent)
511 {
512 int i;
513
514 printk(KERN_DEBUG "cpqarray: Device 0x%x has been found at"
515 " bus %d dev %d func %d\n",
516 pdev->device, pdev->bus->number, PCI_SLOT(pdev->devfn),
517 PCI_FUNC(pdev->devfn));
518 i = alloc_cpqarray_hba();
519 if( i < 0 )
520 return (-1);
521 memset(hba[i], 0, sizeof(ctlr_info_t));
522 sprintf(hba[i]->devname, "ida%d", i);
523 hba[i]->ctlr = i;
524 /* Initialize the pdev driver private data */
525 pci_set_drvdata(pdev, hba[i]);
526
527 if (cpqarray_pci_init(hba[i], pdev) != 0) {
528 pci_set_drvdata(pdev, NULL);
529 release_io_mem(hba[i]);
530 free_hba(i);
531 return -1;
532 }
533
534 return (cpqarray_register_ctlr(i, pdev));
535 }
536
537 static struct pci_driver cpqarray_pci_driver = {
538 .name = "cpqarray",
539 .probe = cpqarray_init_one,
540 .remove = __devexit_p(cpqarray_remove_one_pci),
541 .id_table = cpqarray_pci_device_id,
542 };
543
544 /*
545 * This is it. Find all the controllers and register them.
546 * returns the number of block devices registered.
547 */
548 static int __init cpqarray_init(void)
549 {
550 int num_cntlrs_reg = 0;
551 int i;
552 int rc = 0;
553
554 /* detect controllers */
555 printk(DRIVER_NAME "\n");
556
557 rc = pci_register_driver(&cpqarray_pci_driver);
558 if (rc)
559 return rc;
560 cpqarray_eisa_detect();
561
562 for (i=0; i < MAX_CTLR; i++) {
563 if (hba[i] != NULL)
564 num_cntlrs_reg++;
565 }
566
567 if (num_cntlrs_reg)
568 return 0;
569 else {
570 pci_unregister_driver(&cpqarray_pci_driver);
571 return -ENODEV;
572 }
573 }
574
575 /* Function to find the first free pointer into our hba[] array */
576 /* Returns -1 if no free entries are left. */
577 static int alloc_cpqarray_hba(void)
578 {
579 int i;
580
581 for(i=0; i< MAX_CTLR; i++) {
582 if (hba[i] == NULL) {
583 hba[i] = kmalloc(sizeof(ctlr_info_t), GFP_KERNEL);
584 if(hba[i]==NULL) {
585 printk(KERN_ERR "cpqarray: out of memory.\n");
586 return (-1);
587 }
588 return (i);
589 }
590 }
591 printk(KERN_WARNING "cpqarray: This driver supports a maximum"
592 " of 8 controllers.\n");
593 return(-1);
594 }
595
596 static void free_hba(int i)
597 {
598 kfree(hba[i]);
599 hba[i]=NULL;
600 }
601
602 /*
603 * Find the IO address of the controller, its IRQ and so forth. Fill
604 * in some basic stuff into the ctlr_info_t structure.
605 */
606 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
607 {
608 ushort vendor_id, device_id, command;
609 unchar cache_line_size, latency_timer;
610 unchar irq, revision;
611 unsigned long addr[6];
612 __u32 board_id;
613
614 int i;
615
616 c->pci_dev = pdev;
617 pci_set_master(pdev);
618 if (pci_enable_device(pdev)) {
619 printk(KERN_ERR "cpqarray: Unable to Enable PCI device\n");
620 return -1;
621 }
622 vendor_id = pdev->vendor;
623 device_id = pdev->device;
624 irq = pdev->irq;
625
626 for(i=0; i<6; i++)
627 addr[i] = pci_resource_start(pdev, i);
628
629 if (pci_set_dma_mask(pdev, CPQARRAY_DMA_MASK) != 0)
630 {
631 printk(KERN_ERR "cpqarray: Unable to set DMA mask\n");
632 return -1;
633 }
634
635 pci_read_config_word(pdev, PCI_COMMAND, &command);
636 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
637 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
638 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency_timer);
639
640 pci_read_config_dword(pdev, 0x2c, &board_id);
641
642 /* check to see if controller has been disabled */
643 if(!(command & 0x02)) {
644 printk(KERN_WARNING
645 "cpqarray: controller appears to be disabled\n");
646 return(-1);
647 }
648
649 DBGINFO(
650 printk("vendor_id = %x\n", vendor_id);
651 printk("device_id = %x\n", device_id);
652 printk("command = %x\n", command);
653 for(i=0; i<6; i++)
654 printk("addr[%d] = %lx\n", i, addr[i]);
655 printk("revision = %x\n", revision);
656 printk("irq = %x\n", irq);
657 printk("cache_line_size = %x\n", cache_line_size);
658 printk("latency_timer = %x\n", latency_timer);
659 printk("board_id = %x\n", board_id);
660 );
661
662 c->intr = irq;
663
664 for(i=0; i<6; i++) {
665 if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO)
666 { /* IO space */
667 c->io_mem_addr = addr[i];
668 c->io_mem_length = pci_resource_end(pdev, i)
669 - pci_resource_start(pdev, i) + 1;
670 if(!request_region( c->io_mem_addr, c->io_mem_length,
671 "cpqarray"))
672 {
673 printk( KERN_WARNING "cpqarray I/O memory range already in use addr %lx length = %ld\n", c->io_mem_addr, c->io_mem_length);
674 c->io_mem_addr = 0;
675 c->io_mem_length = 0;
676 }
677 break;
678 }
679 }
680
681 c->paddr = 0;
682 for(i=0; i<6; i++)
683 if (!(pci_resource_flags(pdev, i) &
684 PCI_BASE_ADDRESS_SPACE_IO)) {
685 c->paddr = pci_resource_start (pdev, i);
686 break;
687 }
688 if (!c->paddr)
689 return -1;
690 c->vaddr = remap_pci_mem(c->paddr, 128);
691 if (!c->vaddr)
692 return -1;
693 c->board_id = board_id;
694
695 for(i=0; i<NR_PRODUCTS; i++) {
696 if (board_id == products[i].board_id) {
697 c->product_name = products[i].product_name;
698 c->access = *(products[i].access);
699 break;
700 }
701 }
702 if (i == NR_PRODUCTS) {
703 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
704 " to access the SMART Array controller %08lx\n",
705 (unsigned long)board_id);
706 return -1;
707 }
708
709 return 0;
710 }
711
712 /*
713 * Map (physical) PCI mem into (virtual) kernel space
714 */
715 static void __iomem *remap_pci_mem(ulong base, ulong size)
716 {
717 ulong page_base = ((ulong) base) & PAGE_MASK;
718 ulong page_offs = ((ulong) base) - page_base;
719 void __iomem *page_remapped = ioremap(page_base, page_offs+size);
720
721 return (page_remapped ? (page_remapped + page_offs) : NULL);
722 }
723
724 #ifndef MODULE
725 /*
726 * Config string is a comma separated set of i/o addresses of EISA cards.
727 */
728 static int cpqarray_setup(char *str)
729 {
730 int i, ints[9];
731
732 (void)get_options(str, ARRAY_SIZE(ints), ints);
733
734 for(i=0; i<ints[0] && i<8; i++)
735 eisa[i] = ints[i+1];
736 return 1;
737 }
738
739 __setup("smart2=", cpqarray_setup);
740
741 #endif
742
743 /*
744 * Find an EISA controller's signature. Set up an hba if we find it.
745 */
746 static int __init cpqarray_eisa_detect(void)
747 {
748 int i=0, j;
749 __u32 board_id;
750 int intr;
751 int ctlr;
752 int num_ctlr = 0;
753
754 while(i<8 && eisa[i]) {
755 ctlr = alloc_cpqarray_hba();
756 if(ctlr == -1)
757 break;
758 board_id = inl(eisa[i]+0xC80);
759 for(j=0; j < NR_PRODUCTS; j++)
760 if (board_id == products[j].board_id)
761 break;
762
763 if (j == NR_PRODUCTS) {
764 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
765 " to access the SMART Array controller %08lx\n", (unsigned long)board_id);
766 continue;
767 }
768
769 memset(hba[ctlr], 0, sizeof(ctlr_info_t));
770 hba[ctlr]->io_mem_addr = eisa[i];
771 hba[ctlr]->io_mem_length = 0x7FF;
772 if(!request_region(hba[ctlr]->io_mem_addr,
773 hba[ctlr]->io_mem_length,
774 "cpqarray"))
775 {
776 printk(KERN_WARNING "cpqarray: I/O range already in "
777 "use addr = %lx length = %ld\n",
778 hba[ctlr]->io_mem_addr,
779 hba[ctlr]->io_mem_length);
780 free_hba(ctlr);
781 continue;
782 }
783
784 /*
785 * Read the config register to find our interrupt
786 */
787 intr = inb(eisa[i]+0xCC0) >> 4;
788 if (intr & 1) intr = 11;
789 else if (intr & 2) intr = 10;
790 else if (intr & 4) intr = 14;
791 else if (intr & 8) intr = 15;
792
793 hba[ctlr]->intr = intr;
794 sprintf(hba[ctlr]->devname, "ida%d", nr_ctlr);
795 hba[ctlr]->product_name = products[j].product_name;
796 hba[ctlr]->access = *(products[j].access);
797 hba[ctlr]->ctlr = ctlr;
798 hba[ctlr]->board_id = board_id;
799 hba[ctlr]->pci_dev = NULL; /* not PCI */
800
801 DBGINFO(
802 printk("i = %d, j = %d\n", i, j);
803 printk("irq = %x\n", intr);
804 printk("product name = %s\n", products[j].product_name);
805 printk("board_id = %x\n", board_id);
806 );
807
808 num_ctlr++;
809 i++;
810
811 if (cpqarray_register_ctlr(ctlr, NULL) == -1)
812 printk(KERN_WARNING
813 "cpqarray: Can't register EISA controller %d\n",
814 ctlr);
815
816 }
817
818 return num_ctlr;
819 }
820
821 /*
822 * Open. Make sure the device is really there.
823 */
824 static int ida_open(struct block_device *bdev, fmode_t mode)
825 {
826 drv_info_t *drv = get_drv(bdev->bd_disk);
827 ctlr_info_t *host = get_host(bdev->bd_disk);
828
829 DBGINFO(printk("ida_open %s\n", bdev->bd_disk->disk_name));
830 /*
831 * Root is allowed to open raw volume zero even if it's not configured
832 * so array config can still work. I don't think I really like this,
833 * but I'm already using way to many device nodes to claim another one
834 * for "raw controller".
835 */
836 if (!drv->nr_blks) {
837 if (!capable(CAP_SYS_RAWIO))
838 return -ENXIO;
839 if (!capable(CAP_SYS_ADMIN) && drv != host->drv)
840 return -ENXIO;
841 }
842 host->usage_count++;
843 return 0;
844 }
845
846 /*
847 * Close. Sync first.
848 */
849 static int ida_release(struct gendisk *disk, fmode_t mode)
850 {
851 ctlr_info_t *host = get_host(disk);
852 host->usage_count--;
853 return 0;
854 }
855
856 /*
857 * Enqueuing and dequeuing functions for cmdlists.
858 */
859 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c)
860 {
861 if (*Qptr == NULL) {
862 *Qptr = c;
863 c->next = c->prev = c;
864 } else {
865 c->prev = (*Qptr)->prev;
866 c->next = (*Qptr);
867 (*Qptr)->prev->next = c;
868 (*Qptr)->prev = c;
869 }
870 }
871
872 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c)
873 {
874 if (c && c->next != c) {
875 if (*Qptr == c) *Qptr = c->next;
876 c->prev->next = c->next;
877 c->next->prev = c->prev;
878 } else {
879 *Qptr = NULL;
880 }
881 return c;
882 }
883
884 /*
885 * Get a request and submit it to the controller.
886 * This routine needs to grab all the requests it possibly can from the
887 * req Q and submit them. Interrupts are off (and need to be off) when you
888 * are in here (either via the dummy do_ida_request functions or by being
889 * called from the interrupt handler
890 */
891 static void do_ida_request(struct request_queue *q)
892 {
893 ctlr_info_t *h = q->queuedata;
894 cmdlist_t *c;
895 struct request *creq;
896 struct scatterlist tmp_sg[SG_MAX];
897 int i, dir, seg;
898
899 if (blk_queue_plugged(q))
900 goto startio;
901
902 queue_next:
903 creq = blk_peek_request(q);
904 if (!creq)
905 goto startio;
906
907 BUG_ON(creq->nr_phys_segments > SG_MAX);
908
909 if ((c = cmd_alloc(h,1)) == NULL)
910 goto startio;
911
912 blk_start_request(creq);
913
914 c->ctlr = h->ctlr;
915 c->hdr.unit = (drv_info_t *)(creq->rq_disk->private_data) - h->drv;
916 c->hdr.size = sizeof(rblk_t) >> 2;
917 c->size += sizeof(rblk_t);
918
919 c->req.hdr.blk = blk_rq_pos(creq);
920 c->rq = creq;
921 DBGPX(
922 printk("sector=%d, nr_sectors=%u\n",
923 blk_rq_pos(creq), blk_rq_sectors(creq));
924 );
925 sg_init_table(tmp_sg, SG_MAX);
926 seg = blk_rq_map_sg(q, creq, tmp_sg);
927
928 /* Now do all the DMA Mappings */
929 if (rq_data_dir(creq) == READ)
930 dir = PCI_DMA_FROMDEVICE;
931 else
932 dir = PCI_DMA_TODEVICE;
933 for( i=0; i < seg; i++)
934 {
935 c->req.sg[i].size = tmp_sg[i].length;
936 c->req.sg[i].addr = (__u32) pci_map_page(h->pci_dev,
937 sg_page(&tmp_sg[i]),
938 tmp_sg[i].offset,
939 tmp_sg[i].length, dir);
940 }
941 DBGPX( printk("Submitting %u sectors in %d segments\n", blk_rq_sectors(creq), seg); );
942 c->req.hdr.sg_cnt = seg;
943 c->req.hdr.blk_cnt = blk_rq_sectors(creq);
944 c->req.hdr.cmd = (rq_data_dir(creq) == READ) ? IDA_READ : IDA_WRITE;
945 c->type = CMD_RWREQ;
946
947 /* Put the request on the tail of the request queue */
948 addQ(&h->reqQ, c);
949 h->Qdepth++;
950 if (h->Qdepth > h->maxQsinceinit)
951 h->maxQsinceinit = h->Qdepth;
952
953 goto queue_next;
954
955 startio:
956 start_io(h);
957 }
958
959 /*
960 * start_io submits everything on a controller's request queue
961 * and moves it to the completion queue.
962 *
963 * Interrupts had better be off if you're in here
964 */
965 static void start_io(ctlr_info_t *h)
966 {
967 cmdlist_t *c;
968
969 while((c = h->reqQ) != NULL) {
970 /* Can't do anything if we're busy */
971 if (h->access.fifo_full(h) == 0)
972 return;
973
974 /* Get the first entry from the request Q */
975 removeQ(&h->reqQ, c);
976 h->Qdepth--;
977
978 /* Tell the controller to do our bidding */
979 h->access.submit_command(h, c);
980
981 /* Get onto the completion Q */
982 addQ(&h->cmpQ, c);
983 }
984 }
985
986 /*
987 * Mark all buffers that cmd was responsible for
988 */
989 static inline void complete_command(cmdlist_t *cmd, int timeout)
990 {
991 struct request *rq = cmd->rq;
992 int error = 0;
993 int i, ddir;
994
995 if (cmd->req.hdr.rcode & RCODE_NONFATAL &&
996 (hba[cmd->ctlr]->misc_tflags & MISC_NONFATAL_WARN) == 0) {
997 printk(KERN_NOTICE "Non Fatal error on ida/c%dd%d\n",
998 cmd->ctlr, cmd->hdr.unit);
999 hba[cmd->ctlr]->misc_tflags |= MISC_NONFATAL_WARN;
1000 }
1001 if (cmd->req.hdr.rcode & RCODE_FATAL) {
1002 printk(KERN_WARNING "Fatal error on ida/c%dd%d\n",
1003 cmd->ctlr, cmd->hdr.unit);
1004 error = -EIO;
1005 }
1006 if (cmd->req.hdr.rcode & RCODE_INVREQ) {
1007 printk(KERN_WARNING "Invalid request on ida/c%dd%d = (cmd=%x sect=%d cnt=%d sg=%d ret=%x)\n",
1008 cmd->ctlr, cmd->hdr.unit, cmd->req.hdr.cmd,
1009 cmd->req.hdr.blk, cmd->req.hdr.blk_cnt,
1010 cmd->req.hdr.sg_cnt, cmd->req.hdr.rcode);
1011 error = -EIO;
1012 }
1013 if (timeout)
1014 error = -EIO;
1015 /* unmap the DMA mapping for all the scatter gather elements */
1016 if (cmd->req.hdr.cmd == IDA_READ)
1017 ddir = PCI_DMA_FROMDEVICE;
1018 else
1019 ddir = PCI_DMA_TODEVICE;
1020 for(i=0; i<cmd->req.hdr.sg_cnt; i++)
1021 pci_unmap_page(hba[cmd->ctlr]->pci_dev, cmd->req.sg[i].addr,
1022 cmd->req.sg[i].size, ddir);
1023
1024 DBGPX(printk("Done with %p\n", rq););
1025 __blk_end_request_all(rq, error);
1026 }
1027
1028 /*
1029 * The controller will interrupt us upon completion of commands.
1030 * Find the command on the completion queue, remove it, tell the OS and
1031 * try to queue up more IO
1032 */
1033 static irqreturn_t do_ida_intr(int irq, void *dev_id)
1034 {
1035 ctlr_info_t *h = dev_id;
1036 cmdlist_t *c;
1037 unsigned long istat;
1038 unsigned long flags;
1039 __u32 a,a1;
1040
1041 istat = h->access.intr_pending(h);
1042 /* Is this interrupt for us? */
1043 if (istat == 0)
1044 return IRQ_NONE;
1045
1046 /*
1047 * If there are completed commands in the completion queue,
1048 * we had better do something about it.
1049 */
1050 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
1051 if (istat & FIFO_NOT_EMPTY) {
1052 while((a = h->access.command_completed(h))) {
1053 a1 = a; a &= ~3;
1054 if ((c = h->cmpQ) == NULL)
1055 {
1056 printk(KERN_WARNING "cpqarray: Completion of %08lx ignored\n", (unsigned long)a1);
1057 continue;
1058 }
1059 while(c->busaddr != a) {
1060 c = c->next;
1061 if (c == h->cmpQ)
1062 break;
1063 }
1064 /*
1065 * If we've found the command, take it off the
1066 * completion Q and free it
1067 */
1068 if (c->busaddr == a) {
1069 removeQ(&h->cmpQ, c);
1070 /* Check for invalid command.
1071 * Controller returns command error,
1072 * But rcode = 0.
1073 */
1074
1075 if((a1 & 0x03) && (c->req.hdr.rcode == 0))
1076 {
1077 c->req.hdr.rcode = RCODE_INVREQ;
1078 }
1079 if (c->type == CMD_RWREQ) {
1080 complete_command(c, 0);
1081 cmd_free(h, c, 1);
1082 } else if (c->type == CMD_IOCTL_PEND) {
1083 c->type = CMD_IOCTL_DONE;
1084 }
1085 continue;
1086 }
1087 }
1088 }
1089
1090 /*
1091 * See if we can queue up some more IO
1092 */
1093 do_ida_request(h->queue);
1094 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
1095 return IRQ_HANDLED;
1096 }
1097
1098 /*
1099 * This timer was for timing out requests that haven't happened after
1100 * IDA_TIMEOUT. That wasn't such a good idea. This timer is used to
1101 * reset a flags structure so we don't flood the user with
1102 * "Non-Fatal error" messages.
1103 */
1104 static void ida_timer(unsigned long tdata)
1105 {
1106 ctlr_info_t *h = (ctlr_info_t*)tdata;
1107
1108 h->timer.expires = jiffies + IDA_TIMER;
1109 add_timer(&h->timer);
1110 h->misc_tflags = 0;
1111 }
1112
1113 static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1114 {
1115 drv_info_t *drv = get_drv(bdev->bd_disk);
1116
1117 if (drv->cylinders) {
1118 geo->heads = drv->heads;
1119 geo->sectors = drv->sectors;
1120 geo->cylinders = drv->cylinders;
1121 } else {
1122 geo->heads = 0xff;
1123 geo->sectors = 0x3f;
1124 geo->cylinders = drv->nr_blks / (0xff*0x3f);
1125 }
1126
1127 return 0;
1128 }
1129
1130 /*
1131 * ida_ioctl does some miscellaneous stuff like reporting drive geometry,
1132 * setting readahead and submitting commands from userspace to the controller.
1133 */
1134 static int ida_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, unsigned long arg)
1135 {
1136 drv_info_t *drv = get_drv(bdev->bd_disk);
1137 ctlr_info_t *host = get_host(bdev->bd_disk);
1138 int error;
1139 ida_ioctl_t __user *io = (ida_ioctl_t __user *)arg;
1140 ida_ioctl_t *my_io;
1141
1142 switch(cmd) {
1143 case IDAGETDRVINFO:
1144 if (copy_to_user(&io->c.drv, drv, sizeof(drv_info_t)))
1145 return -EFAULT;
1146 return 0;
1147 case IDAPASSTHRU:
1148 if (!capable(CAP_SYS_RAWIO))
1149 return -EPERM;
1150 my_io = kmalloc(sizeof(ida_ioctl_t), GFP_KERNEL);
1151 if (!my_io)
1152 return -ENOMEM;
1153 error = -EFAULT;
1154 if (copy_from_user(my_io, io, sizeof(*my_io)))
1155 goto out_passthru;
1156 error = ida_ctlr_ioctl(host, drv - host->drv, my_io);
1157 if (error)
1158 goto out_passthru;
1159 error = -EFAULT;
1160 if (copy_to_user(io, my_io, sizeof(*my_io)))
1161 goto out_passthru;
1162 error = 0;
1163 out_passthru:
1164 kfree(my_io);
1165 return error;
1166 case IDAGETCTLRSIG:
1167 if (!arg) return -EINVAL;
1168 put_user(host->ctlr_sig, (int __user *)arg);
1169 return 0;
1170 case IDAREVALIDATEVOLS:
1171 if (MINOR(bdev->bd_dev) != 0)
1172 return -ENXIO;
1173 return revalidate_allvol(host);
1174 case IDADRIVERVERSION:
1175 if (!arg) return -EINVAL;
1176 put_user(DRIVER_VERSION, (unsigned long __user *)arg);
1177 return 0;
1178 case IDAGETPCIINFO:
1179 {
1180
1181 ida_pci_info_struct pciinfo;
1182
1183 if (!arg) return -EINVAL;
1184 pciinfo.bus = host->pci_dev->bus->number;
1185 pciinfo.dev_fn = host->pci_dev->devfn;
1186 pciinfo.board_id = host->board_id;
1187 if(copy_to_user((void __user *) arg, &pciinfo,
1188 sizeof( ida_pci_info_struct)))
1189 return -EFAULT;
1190 return(0);
1191 }
1192
1193 default:
1194 return -EINVAL;
1195 }
1196
1197 }
1198 /*
1199 * ida_ctlr_ioctl is for passing commands to the controller from userspace.
1200 * The command block (io) has already been copied to kernel space for us,
1201 * however, any elements in the sglist need to be copied to kernel space
1202 * or copied back to userspace.
1203 *
1204 * Only root may perform a controller passthru command, however I'm not doing
1205 * any serious sanity checking on the arguments. Doing an IDA_WRITE_MEDIA and
1206 * putting a 64M buffer in the sglist is probably a *bad* idea.
1207 */
1208 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io)
1209 {
1210 int ctlr = h->ctlr;
1211 cmdlist_t *c;
1212 void *p = NULL;
1213 unsigned long flags;
1214 int error;
1215
1216 if ((c = cmd_alloc(h, 0)) == NULL)
1217 return -ENOMEM;
1218 c->ctlr = ctlr;
1219 c->hdr.unit = (io->unit & UNITVALID) ? (io->unit & ~UNITVALID) : dsk;
1220 c->hdr.size = sizeof(rblk_t) >> 2;
1221 c->size += sizeof(rblk_t);
1222
1223 c->req.hdr.cmd = io->cmd;
1224 c->req.hdr.blk = io->blk;
1225 c->req.hdr.blk_cnt = io->blk_cnt;
1226 c->type = CMD_IOCTL_PEND;
1227
1228 /* Pre submit processing */
1229 switch(io->cmd) {
1230 case PASSTHRU_A:
1231 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1232 if (!p)
1233 {
1234 error = -ENOMEM;
1235 cmd_free(h, c, 0);
1236 return(error);
1237 }
1238 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1239 kfree(p);
1240 cmd_free(h, c, 0);
1241 return -EFAULT;
1242 }
1243 c->req.hdr.blk = pci_map_single(h->pci_dev, &(io->c),
1244 sizeof(ida_ioctl_t),
1245 PCI_DMA_BIDIRECTIONAL);
1246 c->req.sg[0].size = io->sg[0].size;
1247 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1248 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1249 c->req.hdr.sg_cnt = 1;
1250 break;
1251 case IDA_READ:
1252 case READ_FLASH_ROM:
1253 case SENSE_CONTROLLER_PERFORMANCE:
1254 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1255 if (!p)
1256 {
1257 error = -ENOMEM;
1258 cmd_free(h, c, 0);
1259 return(error);
1260 }
1261
1262 c->req.sg[0].size = io->sg[0].size;
1263 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1264 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1265 c->req.hdr.sg_cnt = 1;
1266 break;
1267 case IDA_WRITE:
1268 case IDA_WRITE_MEDIA:
1269 case DIAG_PASS_THRU:
1270 case COLLECT_BUFFER:
1271 case WRITE_FLASH_ROM:
1272 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1273 if (!p)
1274 {
1275 error = -ENOMEM;
1276 cmd_free(h, c, 0);
1277 return(error);
1278 }
1279 if (copy_from_user(p, io->sg[0].addr, io->sg[0].size)) {
1280 kfree(p);
1281 cmd_free(h, c, 0);
1282 return -EFAULT;
1283 }
1284 c->req.sg[0].size = io->sg[0].size;
1285 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1286 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1287 c->req.hdr.sg_cnt = 1;
1288 break;
1289 default:
1290 c->req.sg[0].size = sizeof(io->c);
1291 c->req.sg[0].addr = pci_map_single(h->pci_dev,&io->c,
1292 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1293 c->req.hdr.sg_cnt = 1;
1294 }
1295
1296 /* Put the request on the tail of the request queue */
1297 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1298 addQ(&h->reqQ, c);
1299 h->Qdepth++;
1300 start_io(h);
1301 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1302
1303 /* Wait for completion */
1304 while(c->type != CMD_IOCTL_DONE)
1305 schedule();
1306
1307 /* Unmap the DMA */
1308 pci_unmap_single(h->pci_dev, c->req.sg[0].addr, c->req.sg[0].size,
1309 PCI_DMA_BIDIRECTIONAL);
1310 /* Post submit processing */
1311 switch(io->cmd) {
1312 case PASSTHRU_A:
1313 pci_unmap_single(h->pci_dev, c->req.hdr.blk,
1314 sizeof(ida_ioctl_t),
1315 PCI_DMA_BIDIRECTIONAL);
1316 case IDA_READ:
1317 case DIAG_PASS_THRU:
1318 case SENSE_CONTROLLER_PERFORMANCE:
1319 case READ_FLASH_ROM:
1320 if (copy_to_user(io->sg[0].addr, p, io->sg[0].size)) {
1321 kfree(p);
1322 return -EFAULT;
1323 }
1324 /* fall through and free p */
1325 case IDA_WRITE:
1326 case IDA_WRITE_MEDIA:
1327 case COLLECT_BUFFER:
1328 case WRITE_FLASH_ROM:
1329 kfree(p);
1330 break;
1331 default:;
1332 /* Nothing to do */
1333 }
1334
1335 io->rcode = c->req.hdr.rcode;
1336 cmd_free(h, c, 0);
1337 return(0);
1338 }
1339
1340 /*
1341 * Commands are pre-allocated in a large block. Here we use a simple bitmap
1342 * scheme to suballocte them to the driver. Operations that are not time
1343 * critical (and can wait for kmalloc and possibly sleep) can pass in NULL
1344 * as the first argument to get a new command.
1345 */
1346 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool)
1347 {
1348 cmdlist_t * c;
1349 int i;
1350 dma_addr_t cmd_dhandle;
1351
1352 if (!get_from_pool) {
1353 c = (cmdlist_t*)pci_alloc_consistent(h->pci_dev,
1354 sizeof(cmdlist_t), &cmd_dhandle);
1355 if(c==NULL)
1356 return NULL;
1357 } else {
1358 do {
1359 i = find_first_zero_bit(h->cmd_pool_bits, NR_CMDS);
1360 if (i == NR_CMDS)
1361 return NULL;
1362 } while(test_and_set_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG)) != 0);
1363 c = h->cmd_pool + i;
1364 cmd_dhandle = h->cmd_pool_dhandle + i*sizeof(cmdlist_t);
1365 h->nr_allocs++;
1366 }
1367
1368 memset(c, 0, sizeof(cmdlist_t));
1369 c->busaddr = cmd_dhandle;
1370 return c;
1371 }
1372
1373 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool)
1374 {
1375 int i;
1376
1377 if (!got_from_pool) {
1378 pci_free_consistent(h->pci_dev, sizeof(cmdlist_t), c,
1379 c->busaddr);
1380 } else {
1381 i = c - h->cmd_pool;
1382 clear_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG));
1383 h->nr_frees++;
1384 }
1385 }
1386
1387 /***********************************************************************
1388 name: sendcmd
1389 Send a command to an IDA using the memory mapped FIFO interface
1390 and wait for it to complete.
1391 This routine should only be called at init time.
1392 ***********************************************************************/
1393 static int sendcmd(
1394 __u8 cmd,
1395 int ctlr,
1396 void *buff,
1397 size_t size,
1398 unsigned int blk,
1399 unsigned int blkcnt,
1400 unsigned int log_unit )
1401 {
1402 cmdlist_t *c;
1403 int complete;
1404 unsigned long temp;
1405 unsigned long i;
1406 ctlr_info_t *info_p = hba[ctlr];
1407
1408 c = cmd_alloc(info_p, 1);
1409 if(!c)
1410 return IO_ERROR;
1411 c->ctlr = ctlr;
1412 c->hdr.unit = log_unit;
1413 c->hdr.prio = 0;
1414 c->hdr.size = sizeof(rblk_t) >> 2;
1415 c->size += sizeof(rblk_t);
1416
1417 /* The request information. */
1418 c->req.hdr.next = 0;
1419 c->req.hdr.rcode = 0;
1420 c->req.bp = 0;
1421 c->req.hdr.sg_cnt = 1;
1422 c->req.hdr.reserved = 0;
1423
1424 if (size == 0)
1425 c->req.sg[0].size = 512;
1426 else
1427 c->req.sg[0].size = size;
1428
1429 c->req.hdr.blk = blk;
1430 c->req.hdr.blk_cnt = blkcnt;
1431 c->req.hdr.cmd = (unsigned char) cmd;
1432 c->req.sg[0].addr = (__u32) pci_map_single(info_p->pci_dev,
1433 buff, c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1434 /*
1435 * Disable interrupt
1436 */
1437 info_p->access.set_intr_mask(info_p, 0);
1438 /* Make sure there is room in the command FIFO */
1439 /* Actually it should be completely empty at this time. */
1440 for (i = 200000; i > 0; i--) {
1441 temp = info_p->access.fifo_full(info_p);
1442 if (temp != 0) {
1443 break;
1444 }
1445 udelay(10);
1446 DBG(
1447 printk(KERN_WARNING "cpqarray ida%d: idaSendPciCmd FIFO full,"
1448 " waiting!\n", ctlr);
1449 );
1450 }
1451 /*
1452 * Send the cmd
1453 */
1454 info_p->access.submit_command(info_p, c);
1455 complete = pollcomplete(ctlr);
1456
1457 pci_unmap_single(info_p->pci_dev, (dma_addr_t) c->req.sg[0].addr,
1458 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1459 if (complete != 1) {
1460 if (complete != c->busaddr) {
1461 printk( KERN_WARNING
1462 "cpqarray ida%d: idaSendPciCmd "
1463 "Invalid command list address returned! (%08lx)\n",
1464 ctlr, (unsigned long)complete);
1465 cmd_free(info_p, c, 1);
1466 return (IO_ERROR);
1467 }
1468 } else {
1469 printk( KERN_WARNING
1470 "cpqarray ida%d: idaSendPciCmd Timeout out, "
1471 "No command list address returned!\n",
1472 ctlr);
1473 cmd_free(info_p, c, 1);
1474 return (IO_ERROR);
1475 }
1476
1477 if (c->req.hdr.rcode & 0x00FE) {
1478 if (!(c->req.hdr.rcode & BIG_PROBLEM)) {
1479 printk( KERN_WARNING
1480 "cpqarray ida%d: idaSendPciCmd, error: "
1481 "Controller failed at init time "
1482 "cmd: 0x%x, return code = 0x%x\n",
1483 ctlr, c->req.hdr.cmd, c->req.hdr.rcode);
1484
1485 cmd_free(info_p, c, 1);
1486 return (IO_ERROR);
1487 }
1488 }
1489 cmd_free(info_p, c, 1);
1490 return (IO_OK);
1491 }
1492
1493 /*
1494 * revalidate_allvol is for online array config utilities. After a
1495 * utility reconfigures the drives in the array, it can use this function
1496 * (through an ioctl) to make the driver zap any previous disk structs for
1497 * that controller and get new ones.
1498 *
1499 * Right now I'm using the getgeometry() function to do this, but this
1500 * function should probably be finer grained and allow you to revalidate one
1501 * particualar logical volume (instead of all of them on a particular
1502 * controller).
1503 */
1504 static int revalidate_allvol(ctlr_info_t *host)
1505 {
1506 int ctlr = host->ctlr;
1507 int i;
1508 unsigned long flags;
1509
1510 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1511 if (host->usage_count > 1) {
1512 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1513 printk(KERN_WARNING "cpqarray: Device busy for volume"
1514 " revalidation (usage=%d)\n", host->usage_count);
1515 return -EBUSY;
1516 }
1517 host->usage_count++;
1518 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1519
1520 /*
1521 * Set the partition and block size structures for all volumes
1522 * on this controller to zero. We will reread all of this data
1523 */
1524 set_capacity(ida_gendisk[ctlr][0], 0);
1525 for (i = 1; i < NWD; i++) {
1526 struct gendisk *disk = ida_gendisk[ctlr][i];
1527 if (disk->flags & GENHD_FL_UP)
1528 del_gendisk(disk);
1529 }
1530 memset(host->drv, 0, sizeof(drv_info_t)*NWD);
1531
1532 /*
1533 * Tell the array controller not to give us any interrupts while
1534 * we check the new geometry. Then turn interrupts back on when
1535 * we're done.
1536 */
1537 host->access.set_intr_mask(host, 0);
1538 getgeometry(ctlr);
1539 host->access.set_intr_mask(host, FIFO_NOT_EMPTY);
1540
1541 for(i=0; i<NWD; i++) {
1542 struct gendisk *disk = ida_gendisk[ctlr][i];
1543 drv_info_t *drv = &host->drv[i];
1544 if (i && !drv->nr_blks)
1545 continue;
1546 blk_queue_logical_block_size(host->queue, drv->blk_size);
1547 set_capacity(disk, drv->nr_blks);
1548 disk->queue = host->queue;
1549 disk->private_data = drv;
1550 if (i)
1551 add_disk(disk);
1552 }
1553
1554 host->usage_count--;
1555 return 0;
1556 }
1557
1558 static int ida_revalidate(struct gendisk *disk)
1559 {
1560 drv_info_t *drv = disk->private_data;
1561 set_capacity(disk, drv->nr_blks);
1562 return 0;
1563 }
1564
1565 /********************************************************************
1566 name: pollcomplete
1567 Wait polling for a command to complete.
1568 The memory mapped FIFO is polled for the completion.
1569 Used only at init time, interrupts disabled.
1570 ********************************************************************/
1571 static int pollcomplete(int ctlr)
1572 {
1573 int done;
1574 int i;
1575
1576 /* Wait (up to 2 seconds) for a command to complete */
1577
1578 for (i = 200000; i > 0; i--) {
1579 done = hba[ctlr]->access.command_completed(hba[ctlr]);
1580 if (done == 0) {
1581 udelay(10); /* a short fixed delay */
1582 } else
1583 return (done);
1584 }
1585 /* Invalid address to tell caller we ran out of time */
1586 return 1;
1587 }
1588 /*****************************************************************
1589 start_fwbk
1590 Starts controller firmwares background processing.
1591 Currently only the Integrated Raid controller needs this done.
1592 If the PCI mem address registers are written to after this,
1593 data corruption may occur
1594 *****************************************************************/
1595 static void start_fwbk(int ctlr)
1596 {
1597 id_ctlr_t *id_ctlr_buf;
1598 int ret_code;
1599
1600 if( (hba[ctlr]->board_id != 0x40400E11)
1601 && (hba[ctlr]->board_id != 0x40480E11) )
1602
1603 /* Not a Integrated Raid, so there is nothing for us to do */
1604 return;
1605 printk(KERN_DEBUG "cpqarray: Starting firmware's background"
1606 " processing\n");
1607 /* Command does not return anything, but idasend command needs a
1608 buffer */
1609 id_ctlr_buf = kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1610 if(id_ctlr_buf==NULL)
1611 {
1612 printk(KERN_WARNING "cpqarray: Out of memory. "
1613 "Unable to start background processing.\n");
1614 return;
1615 }
1616 ret_code = sendcmd(RESUME_BACKGROUND_ACTIVITY, ctlr,
1617 id_ctlr_buf, 0, 0, 0, 0);
1618 if(ret_code != IO_OK)
1619 printk(KERN_WARNING "cpqarray: Unable to start"
1620 " background processing\n");
1621
1622 kfree(id_ctlr_buf);
1623 }
1624 /*****************************************************************
1625 getgeometry
1626 Get ida logical volume geometry from the controller
1627 This is a large bit of code which once existed in two flavors,
1628 It is used only at init time.
1629 *****************************************************************/
1630 static void getgeometry(int ctlr)
1631 {
1632 id_log_drv_t *id_ldrive;
1633 id_ctlr_t *id_ctlr_buf;
1634 sense_log_drv_stat_t *id_lstatus_buf;
1635 config_t *sense_config_buf;
1636 unsigned int log_unit, log_index;
1637 int ret_code, size;
1638 drv_info_t *drv;
1639 ctlr_info_t *info_p = hba[ctlr];
1640 int i;
1641
1642 info_p->log_drv_map = 0;
1643
1644 id_ldrive = kzalloc(sizeof(id_log_drv_t), GFP_KERNEL);
1645 if (!id_ldrive) {
1646 printk( KERN_ERR "cpqarray: out of memory.\n");
1647 goto err_0;
1648 }
1649
1650 id_ctlr_buf = kzalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1651 if (!id_ctlr_buf) {
1652 printk( KERN_ERR "cpqarray: out of memory.\n");
1653 goto err_1;
1654 }
1655
1656 id_lstatus_buf = kzalloc(sizeof(sense_log_drv_stat_t), GFP_KERNEL);
1657 if (!id_lstatus_buf) {
1658 printk( KERN_ERR "cpqarray: out of memory.\n");
1659 goto err_2;
1660 }
1661
1662 sense_config_buf = kzalloc(sizeof(config_t), GFP_KERNEL);
1663 if (!sense_config_buf) {
1664 printk( KERN_ERR "cpqarray: out of memory.\n");
1665 goto err_3;
1666 }
1667
1668 info_p->phys_drives = 0;
1669 info_p->log_drv_map = 0;
1670 info_p->drv_assign_map = 0;
1671 info_p->drv_spare_map = 0;
1672 info_p->mp_failed_drv_map = 0; /* only initialized here */
1673 /* Get controllers info for this logical drive */
1674 ret_code = sendcmd(ID_CTLR, ctlr, id_ctlr_buf, 0, 0, 0, 0);
1675 if (ret_code == IO_ERROR) {
1676 /*
1677 * If can't get controller info, set the logical drive map to 0,
1678 * so the idastubopen will fail on all logical drives
1679 * on the controller.
1680 */
1681 printk(KERN_ERR "cpqarray: error sending ID controller\n");
1682 goto err_4;
1683 }
1684
1685 info_p->log_drives = id_ctlr_buf->nr_drvs;
1686 for(i=0;i<4;i++)
1687 info_p->firm_rev[i] = id_ctlr_buf->firm_rev[i];
1688 info_p->ctlr_sig = id_ctlr_buf->cfg_sig;
1689
1690 printk(" (%s)\n", info_p->product_name);
1691 /*
1692 * Initialize logical drive map to zero
1693 */
1694 log_index = 0;
1695 /*
1696 * Get drive geometry for all logical drives
1697 */
1698 if (id_ctlr_buf->nr_drvs > 16)
1699 printk(KERN_WARNING "cpqarray ida%d: This driver supports "
1700 "16 logical drives per controller.\n. "
1701 " Additional drives will not be "
1702 "detected\n", ctlr);
1703
1704 for (log_unit = 0;
1705 (log_index < id_ctlr_buf->nr_drvs)
1706 && (log_unit < NWD);
1707 log_unit++) {
1708 size = sizeof(sense_log_drv_stat_t);
1709
1710 /*
1711 Send "Identify logical drive status" cmd
1712 */
1713 ret_code = sendcmd(SENSE_LOG_DRV_STAT,
1714 ctlr, id_lstatus_buf, size, 0, 0, log_unit);
1715 if (ret_code == IO_ERROR) {
1716 /*
1717 If can't get logical drive status, set
1718 the logical drive map to 0, so the
1719 idastubopen will fail for all logical drives
1720 on the controller.
1721 */
1722 info_p->log_drv_map = 0;
1723 printk( KERN_WARNING
1724 "cpqarray ida%d: idaGetGeometry - Controller"
1725 " failed to report status of logical drive %d\n"
1726 "Access to this controller has been disabled\n",
1727 ctlr, log_unit);
1728 goto err_4;
1729 }
1730 /*
1731 Make sure the logical drive is configured
1732 */
1733 if (id_lstatus_buf->status != LOG_NOT_CONF) {
1734 ret_code = sendcmd(ID_LOG_DRV, ctlr, id_ldrive,
1735 sizeof(id_log_drv_t), 0, 0, log_unit);
1736 /*
1737 If error, the bit for this
1738 logical drive won't be set and
1739 idastubopen will return error.
1740 */
1741 if (ret_code != IO_ERROR) {
1742 drv = &info_p->drv[log_unit];
1743 drv->blk_size = id_ldrive->blk_size;
1744 drv->nr_blks = id_ldrive->nr_blks;
1745 drv->cylinders = id_ldrive->drv.cyl;
1746 drv->heads = id_ldrive->drv.heads;
1747 drv->sectors = id_ldrive->drv.sect_per_track;
1748 info_p->log_drv_map |= (1 << log_unit);
1749
1750 printk(KERN_INFO "cpqarray ida/c%dd%d: blksz=%d nr_blks=%d\n",
1751 ctlr, log_unit, drv->blk_size, drv->nr_blks);
1752 ret_code = sendcmd(SENSE_CONFIG,
1753 ctlr, sense_config_buf,
1754 sizeof(config_t), 0, 0, log_unit);
1755 if (ret_code == IO_ERROR) {
1756 info_p->log_drv_map = 0;
1757 printk(KERN_ERR "cpqarray: error sending sense config\n");
1758 goto err_4;
1759 }
1760
1761 info_p->phys_drives =
1762 sense_config_buf->ctlr_phys_drv;
1763 info_p->drv_assign_map
1764 |= sense_config_buf->drv_asgn_map;
1765 info_p->drv_assign_map
1766 |= sense_config_buf->spare_asgn_map;
1767 info_p->drv_spare_map
1768 |= sense_config_buf->spare_asgn_map;
1769 } /* end of if no error on id_ldrive */
1770 log_index = log_index + 1;
1771 } /* end of if logical drive configured */
1772 } /* end of for log_unit */
1773
1774 /* Free all the buffers and return */
1775 err_4:
1776 kfree(sense_config_buf);
1777 err_3:
1778 kfree(id_lstatus_buf);
1779 err_2:
1780 kfree(id_ctlr_buf);
1781 err_1:
1782 kfree(id_ldrive);
1783 err_0:
1784 return;
1785 }
1786
1787 static void __exit cpqarray_exit(void)
1788 {
1789 int i;
1790
1791 pci_unregister_driver(&cpqarray_pci_driver);
1792
1793 /* Double check that all controller entries have been removed */
1794 for(i=0; i<MAX_CTLR; i++) {
1795 if (hba[i] != NULL) {
1796 printk(KERN_WARNING "cpqarray: Removing EISA "
1797 "controller %d\n", i);
1798 cpqarray_remove_one_eisa(i);
1799 }
1800 }
1801
1802 remove_proc_entry("driver/cpqarray", NULL);
1803 }
1804
1805 module_init(cpqarray_init)
1806 module_exit(cpqarray_exit)
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