drivers/dma/shdma.h

   1 /*
   2  * Renesas SuperH DMA Engine support
   3  *
   4  * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
   5  * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
   6  *
   7  * This is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  */
  13 #ifndef __DMA_SHDMA_H
  14 #define __DMA_SHDMA_H
  15
  16 #include <linux/device.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/dmaengine.h>
  19
  20 #define SH_DMA_TCR_MAX 0x00FFFFFF       /* 16MB */
  21
  22 struct sh_dmae_regs {
  23         u32 sar; /* SAR / source address */
  24         u32 dar; /* DAR / destination address */
  25         u32 tcr; /* TCR / transfer count */
  26 };
  27
  28 struct sh_desc {
  29         struct list_head tx_list;
  30         struct sh_dmae_regs hw;
  31         struct list_head node;
  32         struct dma_async_tx_descriptor async_tx;
  33         int mark;
  34 };
  35
  36 struct sh_dmae_chan {
  37         dma_cookie_t completed_cookie;  /* The maximum cookie completed */
  38         spinlock_t desc_lock;                   /* Descriptor operation lock */
  39         struct list_head ld_queue;              /* Link descriptors queue */
  40         struct list_head ld_free;               /* Link descriptors free */
  41         struct dma_chan common;                 /* DMA common channel */
  42         struct device *dev;                             /* Channel device */
  43         struct tasklet_struct tasklet;  /* Tasklet */
  44         int descs_allocated;                    /* desc count */
  45         int id;                         /* Raw id of this channel */
  46         char dev_id[16];        /* unique name per DMAC of channel */
  47
  48         /* Set chcr */
  49         int (*set_chcr)(struct sh_dmae_chan *sh_chan, u32 regs);
  50         /* Set DMA resource */
  51         int (*set_dmars)(struct sh_dmae_chan *sh_chan, u16 res);
  52 };
  53
  54 struct sh_dmae_device {
  55         struct dma_device common;
  56         struct sh_dmae_chan *chan[MAX_DMA_CHANNELS];
  57         struct sh_dmae_pdata pdata;
  58 };
  59
  60 #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
  61 #define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
  62 #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
  63
  64 #endif  /* __DMA_SHDMA_H */