drivers/edac/amd76x_edac.c

   1 /*
   2  * AMD 76x Memory Controller kernel module
   3  * (C) 2003 Linux Networx (http://lnxi.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Thayne Harbaugh
   8  * Based on work by Dan Hollis <goemon at anime dot net> and others.
   9  *      http://www.anime.net/~goemon/linux-ecc/
  10  *
  11  * $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/pci.h>
  18 #include <linux/pci_ids.h>
  19 #include <linux/slab.h>
  20 #include <linux/edac.h>
  21 #include "edac_core.h"
  22
  23 #define AMD76X_REVISION " Ver: 2.0.2 "  __DATE__
  24 #define EDAC_MOD_STR    "amd76x_edac"
  25
  26 #define amd76x_printk(level, fmt, arg...) \
  27         edac_printk(level, "amd76x", fmt, ##arg)
  28
  29 #define amd76x_mc_printk(mci, level, fmt, arg...) \
  30         edac_mc_chipset_printk(mci, level, "amd76x", fmt, ##arg)
  31
  32 #define AMD76X_NR_CSROWS 8
  33 #define AMD76X_NR_CHANS  1
  34 #define AMD76X_NR_DIMMS  4
  35
  36 /* AMD 76x register addresses - device 0 function 0 - PCI bridge */
  37
  38 #define AMD76X_ECC_MODE_STATUS  0x48    /* Mode and status of ECC (32b)
  39                                          *
  40                                          * 31:16 reserved
  41                                          * 15:14 SERR enabled: x1=ue 1x=ce
  42                                          * 13    reserved
  43                                          * 12    diag: disabled, enabled
  44                                          * 11:10 mode: dis, EC, ECC, ECC+scrub
  45                                          *  9:8  status: x1=ue 1x=ce
  46                                          *  7:4  UE cs row
  47                                          *  3:0  CE cs row
  48                                          */
  49
  50 #define AMD76X_DRAM_MODE_STATUS 0x58    /* DRAM Mode and status (32b)
  51                                          *
  52                                          * 31:26 clock disable 5 - 0
  53                                          * 25    SDRAM init
  54                                          * 24    reserved
  55                                          * 23    mode register service
  56                                          * 22:21 suspend to RAM
  57                                          * 20    burst refresh enable
  58                                          * 19    refresh disable
  59                                          * 18    reserved
  60                                          * 17:16 cycles-per-refresh
  61                                          * 15:8  reserved
  62                                          *  7:0  x4 mode enable 7 - 0
  63                                          */
  64
  65 #define AMD76X_MEM_BASE_ADDR    0xC0    /* Memory base address (8 x 32b)
  66                                          *
  67                                          * 31:23 chip-select base
  68                                          * 22:16 reserved
  69                                          * 15:7  chip-select mask
  70                                          *  6:3  reserved
  71                                          *  2:1  address mode
  72                                          *  0    chip-select enable
  73                                          */
  74
  75 struct amd76x_error_info {
  76         u32 ecc_mode_status;
  77 };
  78
  79 enum amd76x_chips {
  80         AMD761 = 0,
  81         AMD762
  82 };
  83
  84 struct amd76x_dev_info {
  85         const char *ctl_name;
  86 };
  87
  88 static const struct amd76x_dev_info amd76x_devs[] = {
  89         [AMD761] = {
  90                 .ctl_name = "AMD761"},
  91         [AMD762] = {
  92                 .ctl_name = "AMD762"},
  93 };
  94
  95 static struct edac_pci_ctl_info *amd76x_pci;
  96
  97 /**
  98  *      amd76x_get_error_info   -       fetch error information
  99  *      @mci: Memory controller
 100  *      @info: Info to fill in
 101  *
 102  *      Fetch and store the AMD76x ECC status. Clear pending status
 103  *      on the chip so that further errors will be reported
 104  */
 105 static void amd76x_get_error_info(struct mem_ctl_info *mci,
 106                                 struct amd76x_error_info *info)
 107 {
 108         struct pci_dev *pdev;
 109
 110         pdev = to_pci_dev(mci->dev);
 111         pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
 112                         &info->ecc_mode_status);
 113
 114         if (info->ecc_mode_status & BIT(8))
 115                 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
 116                                  (u32) BIT(8), (u32) BIT(8));
 117
 118         if (info->ecc_mode_status & BIT(9))
 119                 pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
 120                                  (u32) BIT(9), (u32) BIT(9));
 121 }
 122
 123 /**
 124  *      amd76x_process_error_info       -       Error check
 125  *      @mci: Memory controller
 126  *      @info: Previously fetched information from chip
 127  *      @handle_errors: 1 if we should do recovery
 128  *
 129  *      Process the chip state and decide if an error has occurred.
 130  *      A return of 1 indicates an error. Also if handle_errors is true
 131  *      then attempt to handle and clean up after the error
 132  */
 133 static int amd76x_process_error_info(struct mem_ctl_info *mci,
 134                                 struct amd76x_error_info *info,
 135                                 int handle_errors)
 136 {
 137         int error_found;
 138         u32 row;
 139
 140         error_found = 0;
 141
 142         /*
 143          *      Check for an uncorrectable error
 144          */
 145         if (info->ecc_mode_status & BIT(8)) {
 146                 error_found = 1;
 147
 148                 if (handle_errors) {
 149                         row = (info->ecc_mode_status >> 4) & 0xf;
 150                         edac_mc_handle_ue(mci, mci->csrows[row].first_page, 0,
 151                                         row, mci->ctl_name);
 152                 }
 153         }
 154
 155         /*
 156          *      Check for a correctable error
 157          */
 158         if (info->ecc_mode_status & BIT(9)) {
 159                 error_found = 1;
 160
 161                 if (handle_errors) {
 162                         row = info->ecc_mode_status & 0xf;
 163                         edac_mc_handle_ce(mci, mci->csrows[row].first_page, 0,
 164                                         0, row, 0, mci->ctl_name);
 165                 }
 166         }
 167
 168         return error_found;
 169 }
 170
 171 /**
 172  *      amd76x_check    -       Poll the controller
 173  *      @mci: Memory controller
 174  *
 175  *      Called by the poll handlers this function reads the status
 176  *      from the controller and checks for errors.
 177  */
 178 static void amd76x_check(struct mem_ctl_info *mci)
 179 {
 180         struct amd76x_error_info info;
 181         debugf3("%s()\n", __func__);
 182         amd76x_get_error_info(mci, &info);
 183         amd76x_process_error_info(mci, &info, 1);
 184 }
 185
 186 static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
 187                         enum edac_type edac_mode)
 188 {
 189         struct csrow_info *csrow;
 190         u32 mba, mba_base, mba_mask, dms;
 191         int index;
 192
 193         for (index = 0; index < mci->nr_csrows; index++) {
 194                 csrow = &mci->csrows[index];
 195
 196                 /* find the DRAM Chip Select Base address and mask */
 197                 pci_read_config_dword(pdev,
 198                                 AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
 199
 200                 if (!(mba & BIT(0)))
 201                         continue;
 202
 203                 mba_base = mba & 0xff800000UL;
 204                 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
 205                 pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
 206                 csrow->first_page = mba_base >> PAGE_SHIFT;
 207                 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
 208                 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
 209                 csrow->page_mask = mba_mask >> PAGE_SHIFT;
 210                 csrow->grain = csrow->nr_pages << PAGE_SHIFT;
 211                 csrow->mtype = MEM_RDDR;
 212                 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
 213                 csrow->edac_mode = edac_mode;
 214         }
 215 }
 216
 217 /**
 218  *      amd76x_probe1   -       Perform set up for detected device
 219  *      @pdev; PCI device detected
 220  *      @dev_idx: Device type index
 221  *
 222  *      We have found an AMD76x and now need to set up the memory
 223  *      controller status reporting. We configure and set up the
 224  *      memory controller reporting and claim the device.
 225  */
 226 static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
 227 {
 228         static const enum edac_type ems_modes[] = {
 229                 EDAC_NONE,
 230                 EDAC_EC,
 231                 EDAC_SECDED,
 232                 EDAC_SECDED
 233         };
 234         struct mem_ctl_info *mci = NULL;
 235         u32 ems;
 236         u32 ems_mode;
 237         struct amd76x_error_info discard;
 238
 239         debugf0("%s()\n", __func__);
 240         pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
 241         ems_mode = (ems >> 10) & 0x3;
 242         mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS, 0);
 243
 244         if (mci == NULL) {
 245                 return -ENOMEM;
 246         }
 247
 248         debugf0("%s(): mci = %p\n", __func__, mci);
 249         mci->dev = &pdev->dev;
 250         mci->mtype_cap = MEM_FLAG_RDDR;
 251         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
 252         mci->edac_cap = ems_mode ?
 253                 (EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
 254         mci->mod_name = EDAC_MOD_STR;
 255         mci->mod_ver = AMD76X_REVISION;
 256         mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
 257         mci->dev_name = pci_name(pdev);
 258         mci->edac_check = amd76x_check;
 259         mci->ctl_page_to_phys = NULL;
 260
 261         amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
 262         amd76x_get_error_info(mci, &discard);   /* clear counters */
 263
 264         /* Here we assume that we will never see multiple instances of this
 265          * type of memory controller.  The ID is therefore hardcoded to 0.
 266          */
 267         if (edac_mc_add_mc(mci)) {
 268                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 269                 goto fail;
 270         }
 271
 272         /* allocating generic PCI control info */
 273         amd76x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
 274         if (!amd76x_pci) {
 275                 printk(KERN_WARNING
 276                         "%s(): Unable to create PCI control\n",
 277                         __func__);
 278                 printk(KERN_WARNING
 279                         "%s(): PCI error report via EDAC not setup\n",
 280                         __func__);
 281         }
 282
 283         /* get this far and it's successful */
 284         debugf3("%s(): success\n", __func__);
 285         return 0;
 286
 287 fail:
 288         edac_mc_free(mci);
 289         return -ENODEV;
 290 }
 291
 292 /* returns count (>= 0), or negative on error */
 293 static int __devinit amd76x_init_one(struct pci_dev *pdev,
 294                                 const struct pci_device_id *ent)
 295 {
 296         debugf0("%s()\n", __func__);
 297
 298         /* don't need to call pci_device_enable() */
 299         return amd76x_probe1(pdev, ent->driver_data);
 300 }
 301
 302 /**
 303  *      amd76x_remove_one       -       driver shutdown
 304  *      @pdev: PCI device being handed back
 305  *
 306  *      Called when the driver is unloaded. Find the matching mci
 307  *      structure for the device then delete the mci and free the
 308  *      resources.
 309  */
 310 static void __devexit amd76x_remove_one(struct pci_dev *pdev)
 311 {
 312         struct mem_ctl_info *mci;
 313
 314         debugf0("%s()\n", __func__);
 315
 316         if (amd76x_pci)
 317                 edac_pci_release_generic_ctl(amd76x_pci);
 318
 319         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 320                 return;
 321
 322         edac_mc_free(mci);
 323 }
 324
 325 static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
 326         {
 327          PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 328          AMD762},
 329         {
 330          PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 331          AMD761},
 332         {
 333          0,
 334          }                      /* 0 terminated list. */
 335 };
 336
 337 MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
 338
 339 static struct pci_driver amd76x_driver = {
 340         .name = EDAC_MOD_STR,
 341         .probe = amd76x_init_one,
 342         .remove = __devexit_p(amd76x_remove_one),
 343         .id_table = amd76x_pci_tbl,
 344 };
 345
 346 static int __init amd76x_init(void)
 347 {
 348        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
 349        opstate_init();
 350
 351         return pci_register_driver(&amd76x_driver);
 352 }
 353
 354 static void __exit amd76x_exit(void)
 355 {
 356         pci_unregister_driver(&amd76x_driver);
 357 }
 358
 359 module_init(amd76x_init);
 360 module_exit(amd76x_exit);
 361
 362 MODULE_LICENSE("GPL");
 363 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
 364 MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
 365
 366 module_param(edac_op_state, int, 0444);
 367 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");