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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / gpu / drm / i915 / i915_dma.c
blob92aeb918e0c02481fa7909972add10e59b1a0f27
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/vgaarb.h>
38
39 /* Really want an OS-independent resettable timer. Would like to have
40 * this loop run for (eg) 3 sec, but have the timer reset every time
41 * the head pointer changes, so that EBUSY only happens if the ring
42 * actually stalls for (eg) 3 seconds.
43 */
44 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
45 {
46 drm_i915_private_t *dev_priv = dev->dev_private;
47 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
48 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
49 u32 last_acthd = I915_READ(acthd_reg);
50 u32 acthd;
51 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
52 int i;
53
54 trace_i915_ring_wait_begin (dev);
55
56 for (i = 0; i < 100000; i++) {
57 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
58 acthd = I915_READ(acthd_reg);
59 ring->space = ring->head - (ring->tail + 8);
60 if (ring->space < 0)
61 ring->space += ring->Size;
62 if (ring->space >= n) {
63 trace_i915_ring_wait_end (dev);
64 return 0;
65 }
66
67 if (dev->primary->master) {
68 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
69 if (master_priv->sarea_priv)
70 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
71 }
72
73
74 if (ring->head != last_head)
75 i = 0;
76 if (acthd != last_acthd)
77 i = 0;
78
79 last_head = ring->head;
80 last_acthd = acthd;
81 msleep_interruptible(10);
82
83 }
84
85 trace_i915_ring_wait_end (dev);
86 return -EBUSY;
87 }
88
89 /* As a ringbuffer is only allowed to wrap between instructions, fill
90 * the tail with NOOPs.
91 */
92 int i915_wrap_ring(struct drm_device *dev)
93 {
94 drm_i915_private_t *dev_priv = dev->dev_private;
95 volatile unsigned int *virt;
96 int rem;
97
98 rem = dev_priv->ring.Size - dev_priv->ring.tail;
99 if (dev_priv->ring.space < rem) {
100 int ret = i915_wait_ring(dev, rem, __func__);
101 if (ret)
102 return ret;
103 }
104 dev_priv->ring.space -= rem;
105
106 virt = (unsigned int *)
107 (dev_priv->ring.virtual_start + dev_priv->ring.tail);
108 rem /= 4;
109 while (rem--)
110 *virt++ = MI_NOOP;
111
112 dev_priv->ring.tail = 0;
113
114 return 0;
115 }
116
117 /**
118 * Sets up the hardware status page for devices that need a physical address
119 * in the register.
120 */
121 static int i915_init_phys_hws(struct drm_device *dev)
122 {
123 drm_i915_private_t *dev_priv = dev->dev_private;
124 /* Program Hardware Status Page */
125 dev_priv->status_page_dmah =
126 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
127
128 if (!dev_priv->status_page_dmah) {
129 DRM_ERROR("Can not allocate hardware status page\n");
130 return -ENOMEM;
131 }
132 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
133 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
134
135 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
136
137 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
138 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
139 return 0;
140 }
141
142 /**
143 * Frees the hardware status page, whether it's a physical address or a virtual
144 * address set up by the X Server.
145 */
146 static void i915_free_hws(struct drm_device *dev)
147 {
148 drm_i915_private_t *dev_priv = dev->dev_private;
149 if (dev_priv->status_page_dmah) {
150 drm_pci_free(dev, dev_priv->status_page_dmah);
151 dev_priv->status_page_dmah = NULL;
152 }
153
154 if (dev_priv->status_gfx_addr) {
155 dev_priv->status_gfx_addr = 0;
156 drm_core_ioremapfree(&dev_priv->hws_map, dev);
157 }
158
159 /* Need to rewrite hardware status page */
160 I915_WRITE(HWS_PGA, 0x1ffff000);
161 }
162
163 void i915_kernel_lost_context(struct drm_device * dev)
164 {
165 drm_i915_private_t *dev_priv = dev->dev_private;
166 struct drm_i915_master_private *master_priv;
167 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
168
169 /*
170 * We should never lose context on the ring with modesetting
171 * as we don't expose it to userspace
172 */
173 if (drm_core_check_feature(dev, DRIVER_MODESET))
174 return;
175
176 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
177 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
178 ring->space = ring->head - (ring->tail + 8);
179 if (ring->space < 0)
180 ring->space += ring->Size;
181
182 if (!dev->primary->master)
183 return;
184
185 master_priv = dev->primary->master->driver_priv;
186 if (ring->head == ring->tail && master_priv->sarea_priv)
187 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
188 }
189
190 static int i915_dma_cleanup(struct drm_device * dev)
191 {
192 drm_i915_private_t *dev_priv = dev->dev_private;
193 /* Make sure interrupts are disabled here because the uninstall ioctl
194 * may not have been called from userspace and after dev_private
195 * is freed, it's too late.
196 */
197 if (dev->irq_enabled)
198 drm_irq_uninstall(dev);
199
200 if (dev_priv->ring.virtual_start) {
201 drm_core_ioremapfree(&dev_priv->ring.map, dev);
202 dev_priv->ring.virtual_start = NULL;
203 dev_priv->ring.map.handle = NULL;
204 dev_priv->ring.map.size = 0;
205 }
206
207 /* Clear the HWS virtual address at teardown */
208 if (I915_NEED_GFX_HWS(dev))
209 i915_free_hws(dev);
210
211 return 0;
212 }
213
214 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
215 {
216 drm_i915_private_t *dev_priv = dev->dev_private;
217 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
218
219 master_priv->sarea = drm_getsarea(dev);
220 if (master_priv->sarea) {
221 master_priv->sarea_priv = (drm_i915_sarea_t *)
222 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
223 } else {
224 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
225 }
226
227 if (init->ring_size != 0) {
228 if (dev_priv->ring.ring_obj != NULL) {
229 i915_dma_cleanup(dev);
230 DRM_ERROR("Client tried to initialize ringbuffer in "
231 "GEM mode\n");
232 return -EINVAL;
233 }
234
235 dev_priv->ring.Size = init->ring_size;
236
237 dev_priv->ring.map.offset = init->ring_start;
238 dev_priv->ring.map.size = init->ring_size;
239 dev_priv->ring.map.type = 0;
240 dev_priv->ring.map.flags = 0;
241 dev_priv->ring.map.mtrr = 0;
242
243 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
244
245 if (dev_priv->ring.map.handle == NULL) {
246 i915_dma_cleanup(dev);
247 DRM_ERROR("can not ioremap virtual address for"
248 " ring buffer\n");
249 return -ENOMEM;
250 }
251 }
252
253 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
254
255 dev_priv->cpp = init->cpp;
256 dev_priv->back_offset = init->back_offset;
257 dev_priv->front_offset = init->front_offset;
258 dev_priv->current_page = 0;
259 if (master_priv->sarea_priv)
260 master_priv->sarea_priv->pf_current_page = 0;
261
262 /* Allow hardware batchbuffers unless told otherwise.
263 */
264 dev_priv->allow_batchbuffer = 1;
265
266 return 0;
267 }
268
269 static int i915_dma_resume(struct drm_device * dev)
270 {
271 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
272
273 DRM_DEBUG_DRIVER("%s\n", __func__);
274
275 if (dev_priv->ring.map.handle == NULL) {
276 DRM_ERROR("can not ioremap virtual address for"
277 " ring buffer\n");
278 return -ENOMEM;
279 }
280
281 /* Program Hardware Status Page */
282 if (!dev_priv->hw_status_page) {
283 DRM_ERROR("Can not find hardware status page\n");
284 return -EINVAL;
285 }
286 DRM_DEBUG_DRIVER("hw status page @ %p\n",
287 dev_priv->hw_status_page);
288
289 if (dev_priv->status_gfx_addr != 0)
290 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
291 else
292 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
293 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
294
295 return 0;
296 }
297
298 static int i915_dma_init(struct drm_device *dev, void *data,
299 struct drm_file *file_priv)
300 {
301 drm_i915_init_t *init = data;
302 int retcode = 0;
303
304 switch (init->func) {
305 case I915_INIT_DMA:
306 retcode = i915_initialize(dev, init);
307 break;
308 case I915_CLEANUP_DMA:
309 retcode = i915_dma_cleanup(dev);
310 break;
311 case I915_RESUME_DMA:
312 retcode = i915_dma_resume(dev);
313 break;
314 default:
315 retcode = -EINVAL;
316 break;
317 }
318
319 return retcode;
320 }
321
322 /* Implement basically the same security restrictions as hardware does
323 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
324 *
325 * Most of the calculations below involve calculating the size of a
326 * particular instruction. It's important to get the size right as
327 * that tells us where the next instruction to check is. Any illegal
328 * instruction detected will be given a size of zero, which is a
329 * signal to abort the rest of the buffer.
330 */
331 static int do_validate_cmd(int cmd)
332 {
333 switch (((cmd >> 29) & 0x7)) {
334 case 0x0:
335 switch ((cmd >> 23) & 0x3f) {
336 case 0x0:
337 return 1; /* MI_NOOP */
338 case 0x4:
339 return 1; /* MI_FLUSH */
340 default:
341 return 0; /* disallow everything else */
342 }
343 break;
344 case 0x1:
345 return 0; /* reserved */
346 case 0x2:
347 return (cmd & 0xff) + 2; /* 2d commands */
348 case 0x3:
349 if (((cmd >> 24) & 0x1f) <= 0x18)
350 return 1;
351
352 switch ((cmd >> 24) & 0x1f) {
353 case 0x1c:
354 return 1;
355 case 0x1d:
356 switch ((cmd >> 16) & 0xff) {
357 case 0x3:
358 return (cmd & 0x1f) + 2;
359 case 0x4:
360 return (cmd & 0xf) + 2;
361 default:
362 return (cmd & 0xffff) + 2;
363 }
364 case 0x1e:
365 if (cmd & (1 << 23))
366 return (cmd & 0xffff) + 1;
367 else
368 return 1;
369 case 0x1f:
370 if ((cmd & (1 << 23)) == 0) /* inline vertices */
371 return (cmd & 0x1ffff) + 2;
372 else if (cmd & (1 << 17)) /* indirect random */
373 if ((cmd & 0xffff) == 0)
374 return 0; /* unknown length, too hard */
375 else
376 return (((cmd & 0xffff) + 1) / 2) + 1;
377 else
378 return 2; /* indirect sequential */
379 default:
380 return 0;
381 }
382 default:
383 return 0;
384 }
385
386 return 0;
387 }
388
389 static int validate_cmd(int cmd)
390 {
391 int ret = do_validate_cmd(cmd);
392
393 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
394
395 return ret;
396 }
397
398 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
399 {
400 drm_i915_private_t *dev_priv = dev->dev_private;
401 int i;
402 RING_LOCALS;
403
404 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
405 return -EINVAL;
406
407 BEGIN_LP_RING((dwords+1)&~1);
408
409 for (i = 0; i < dwords;) {
410 int cmd, sz;
411
412 cmd = buffer[i];
413
414 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
415 return -EINVAL;
416
417 OUT_RING(cmd);
418
419 while (++i, --sz) {
420 OUT_RING(buffer[i]);
421 }
422 }
423
424 if (dwords & 1)
425 OUT_RING(0);
426
427 ADVANCE_LP_RING();
428
429 return 0;
430 }
431
432 int
433 i915_emit_box(struct drm_device *dev,
434 struct drm_clip_rect *boxes,
435 int i, int DR1, int DR4)
436 {
437 drm_i915_private_t *dev_priv = dev->dev_private;
438 struct drm_clip_rect box = boxes[i];
439 RING_LOCALS;
440
441 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
442 DRM_ERROR("Bad box %d,%d..%d,%d\n",
443 box.x1, box.y1, box.x2, box.y2);
444 return -EINVAL;
445 }
446
447 if (IS_I965G(dev)) {
448 BEGIN_LP_RING(4);
449 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
450 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
451 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
452 OUT_RING(DR4);
453 ADVANCE_LP_RING();
454 } else {
455 BEGIN_LP_RING(6);
456 OUT_RING(GFX_OP_DRAWRECT_INFO);
457 OUT_RING(DR1);
458 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
459 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
460 OUT_RING(DR4);
461 OUT_RING(0);
462 ADVANCE_LP_RING();
463 }
464
465 return 0;
466 }
467
468 /* XXX: Emitting the counter should really be moved to part of the IRQ
469 * emit. For now, do it in both places:
470 */
471
472 static void i915_emit_breadcrumb(struct drm_device *dev)
473 {
474 drm_i915_private_t *dev_priv = dev->dev_private;
475 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
476 RING_LOCALS;
477
478 dev_priv->counter++;
479 if (dev_priv->counter > 0x7FFFFFFFUL)
480 dev_priv->counter = 0;
481 if (master_priv->sarea_priv)
482 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
483
484 BEGIN_LP_RING(4);
485 OUT_RING(MI_STORE_DWORD_INDEX);
486 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
487 OUT_RING(dev_priv->counter);
488 OUT_RING(0);
489 ADVANCE_LP_RING();
490 }
491
492 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
493 drm_i915_cmdbuffer_t *cmd,
494 struct drm_clip_rect *cliprects,
495 void *cmdbuf)
496 {
497 int nbox = cmd->num_cliprects;
498 int i = 0, count, ret;
499
500 if (cmd->sz & 0x3) {
501 DRM_ERROR("alignment");
502 return -EINVAL;
503 }
504
505 i915_kernel_lost_context(dev);
506
507 count = nbox ? nbox : 1;
508
509 for (i = 0; i < count; i++) {
510 if (i < nbox) {
511 ret = i915_emit_box(dev, cliprects, i,
512 cmd->DR1, cmd->DR4);
513 if (ret)
514 return ret;
515 }
516
517 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
518 if (ret)
519 return ret;
520 }
521
522 i915_emit_breadcrumb(dev);
523 return 0;
524 }
525
526 static int i915_dispatch_batchbuffer(struct drm_device * dev,
527 drm_i915_batchbuffer_t * batch,
528 struct drm_clip_rect *cliprects)
529 {
530 drm_i915_private_t *dev_priv = dev->dev_private;
531 int nbox = batch->num_cliprects;
532 int i = 0, count;
533 RING_LOCALS;
534
535 if ((batch->start | batch->used) & 0x7) {
536 DRM_ERROR("alignment");
537 return -EINVAL;
538 }
539
540 i915_kernel_lost_context(dev);
541
542 count = nbox ? nbox : 1;
543
544 for (i = 0; i < count; i++) {
545 if (i < nbox) {
546 int ret = i915_emit_box(dev, cliprects, i,
547 batch->DR1, batch->DR4);
548 if (ret)
549 return ret;
550 }
551
552 if (!IS_I830(dev) && !IS_845G(dev)) {
553 BEGIN_LP_RING(2);
554 if (IS_I965G(dev)) {
555 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
556 OUT_RING(batch->start);
557 } else {
558 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
559 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
560 }
561 ADVANCE_LP_RING();
562 } else {
563 BEGIN_LP_RING(4);
564 OUT_RING(MI_BATCH_BUFFER);
565 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
566 OUT_RING(batch->start + batch->used - 4);
567 OUT_RING(0);
568 ADVANCE_LP_RING();
569 }
570 }
571
572 i915_emit_breadcrumb(dev);
573
574 return 0;
575 }
576
577 static int i915_dispatch_flip(struct drm_device * dev)
578 {
579 drm_i915_private_t *dev_priv = dev->dev_private;
580 struct drm_i915_master_private *master_priv =
581 dev->primary->master->driver_priv;
582 RING_LOCALS;
583
584 if (!master_priv->sarea_priv)
585 return -EINVAL;
586
587 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
588 __func__,
589 dev_priv->current_page,
590 master_priv->sarea_priv->pf_current_page);
591
592 i915_kernel_lost_context(dev);
593
594 BEGIN_LP_RING(2);
595 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
596 OUT_RING(0);
597 ADVANCE_LP_RING();
598
599 BEGIN_LP_RING(6);
600 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
601 OUT_RING(0);
602 if (dev_priv->current_page == 0) {
603 OUT_RING(dev_priv->back_offset);
604 dev_priv->current_page = 1;
605 } else {
606 OUT_RING(dev_priv->front_offset);
607 dev_priv->current_page = 0;
608 }
609 OUT_RING(0);
610 ADVANCE_LP_RING();
611
612 BEGIN_LP_RING(2);
613 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
614 OUT_RING(0);
615 ADVANCE_LP_RING();
616
617 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
618
619 BEGIN_LP_RING(4);
620 OUT_RING(MI_STORE_DWORD_INDEX);
621 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
622 OUT_RING(dev_priv->counter);
623 OUT_RING(0);
624 ADVANCE_LP_RING();
625
626 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
627 return 0;
628 }
629
630 static int i915_quiescent(struct drm_device * dev)
631 {
632 drm_i915_private_t *dev_priv = dev->dev_private;
633
634 i915_kernel_lost_context(dev);
635 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
636 }
637
638 static int i915_flush_ioctl(struct drm_device *dev, void *data,
639 struct drm_file *file_priv)
640 {
641 int ret;
642
643 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
644
645 mutex_lock(&dev->struct_mutex);
646 ret = i915_quiescent(dev);
647 mutex_unlock(&dev->struct_mutex);
648
649 return ret;
650 }
651
652 static int i915_batchbuffer(struct drm_device *dev, void *data,
653 struct drm_file *file_priv)
654 {
655 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
656 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
657 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
658 master_priv->sarea_priv;
659 drm_i915_batchbuffer_t *batch = data;
660 int ret;
661 struct drm_clip_rect *cliprects = NULL;
662
663 if (!dev_priv->allow_batchbuffer) {
664 DRM_ERROR("Batchbuffer ioctl disabled\n");
665 return -EINVAL;
666 }
667
668 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
669 batch->start, batch->used, batch->num_cliprects);
670
671 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
672
673 if (batch->num_cliprects < 0)
674 return -EINVAL;
675
676 if (batch->num_cliprects) {
677 cliprects = kcalloc(batch->num_cliprects,
678 sizeof(struct drm_clip_rect),
679 GFP_KERNEL);
680 if (cliprects == NULL)
681 return -ENOMEM;
682
683 ret = copy_from_user(cliprects, batch->cliprects,
684 batch->num_cliprects *
685 sizeof(struct drm_clip_rect));
686 if (ret != 0)
687 goto fail_free;
688 }
689
690 mutex_lock(&dev->struct_mutex);
691 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
692 mutex_unlock(&dev->struct_mutex);
693
694 if (sarea_priv)
695 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
696
697 fail_free:
698 kfree(cliprects);
699
700 return ret;
701 }
702
703 static int i915_cmdbuffer(struct drm_device *dev, void *data,
704 struct drm_file *file_priv)
705 {
706 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
707 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
708 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
709 master_priv->sarea_priv;
710 drm_i915_cmdbuffer_t *cmdbuf = data;
711 struct drm_clip_rect *cliprects = NULL;
712 void *batch_data;
713 int ret;
714
715 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
716 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
717
718 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
719
720 if (cmdbuf->num_cliprects < 0)
721 return -EINVAL;
722
723 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
724 if (batch_data == NULL)
725 return -ENOMEM;
726
727 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
728 if (ret != 0)
729 goto fail_batch_free;
730
731 if (cmdbuf->num_cliprects) {
732 cliprects = kcalloc(cmdbuf->num_cliprects,
733 sizeof(struct drm_clip_rect), GFP_KERNEL);
734 if (cliprects == NULL)
735 goto fail_batch_free;
736
737 ret = copy_from_user(cliprects, cmdbuf->cliprects,
738 cmdbuf->num_cliprects *
739 sizeof(struct drm_clip_rect));
740 if (ret != 0)
741 goto fail_clip_free;
742 }
743
744 mutex_lock(&dev->struct_mutex);
745 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
746 mutex_unlock(&dev->struct_mutex);
747 if (ret) {
748 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
749 goto fail_clip_free;
750 }
751
752 if (sarea_priv)
753 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
754
755 fail_clip_free:
756 kfree(cliprects);
757 fail_batch_free:
758 kfree(batch_data);
759
760 return ret;
761 }
762
763 static int i915_flip_bufs(struct drm_device *dev, void *data,
764 struct drm_file *file_priv)
765 {
766 int ret;
767
768 DRM_DEBUG_DRIVER("%s\n", __func__);
769
770 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
771
772 mutex_lock(&dev->struct_mutex);
773 ret = i915_dispatch_flip(dev);
774 mutex_unlock(&dev->struct_mutex);
775
776 return ret;
777 }
778
779 static int i915_getparam(struct drm_device *dev, void *data,
780 struct drm_file *file_priv)
781 {
782 drm_i915_private_t *dev_priv = dev->dev_private;
783 drm_i915_getparam_t *param = data;
784 int value;
785
786 if (!dev_priv) {
787 DRM_ERROR("called with no initialization\n");
788 return -EINVAL;
789 }
790
791 switch (param->param) {
792 case I915_PARAM_IRQ_ACTIVE:
793 value = dev->pdev->irq ? 1 : 0;
794 break;
795 case I915_PARAM_ALLOW_BATCHBUFFER:
796 value = dev_priv->allow_batchbuffer ? 1 : 0;
797 break;
798 case I915_PARAM_LAST_DISPATCH:
799 value = READ_BREADCRUMB(dev_priv);
800 break;
801 case I915_PARAM_CHIPSET_ID:
802 value = dev->pci_device;
803 break;
804 case I915_PARAM_HAS_GEM:
805 value = dev_priv->has_gem;
806 break;
807 case I915_PARAM_NUM_FENCES_AVAIL:
808 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
809 break;
810 default:
811 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
812 param->param);
813 return -EINVAL;
814 }
815
816 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
817 DRM_ERROR("DRM_COPY_TO_USER failed\n");
818 return -EFAULT;
819 }
820
821 return 0;
822 }
823
824 static int i915_setparam(struct drm_device *dev, void *data,
825 struct drm_file *file_priv)
826 {
827 drm_i915_private_t *dev_priv = dev->dev_private;
828 drm_i915_setparam_t *param = data;
829
830 if (!dev_priv) {
831 DRM_ERROR("called with no initialization\n");
832 return -EINVAL;
833 }
834
835 switch (param->param) {
836 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
837 break;
838 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
839 dev_priv->tex_lru_log_granularity = param->value;
840 break;
841 case I915_SETPARAM_ALLOW_BATCHBUFFER:
842 dev_priv->allow_batchbuffer = param->value;
843 break;
844 case I915_SETPARAM_NUM_USED_FENCES:
845 if (param->value > dev_priv->num_fence_regs ||
846 param->value < 0)
847 return -EINVAL;
848 /* Userspace can use first N regs */
849 dev_priv->fence_reg_start = param->value;
850 break;
851 default:
852 DRM_DEBUG_DRIVER("unknown parameter %d\n",
853 param->param);
854 return -EINVAL;
855 }
856
857 return 0;
858 }
859
860 static int i915_set_status_page(struct drm_device *dev, void *data,
861 struct drm_file *file_priv)
862 {
863 drm_i915_private_t *dev_priv = dev->dev_private;
864 drm_i915_hws_addr_t *hws = data;
865
866 if (!I915_NEED_GFX_HWS(dev))
867 return -EINVAL;
868
869 if (!dev_priv) {
870 DRM_ERROR("called with no initialization\n");
871 return -EINVAL;
872 }
873
874 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
875 WARN(1, "tried to set status page when mode setting active\n");
876 return 0;
877 }
878
879 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
880
881 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
882
883 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
884 dev_priv->hws_map.size = 4*1024;
885 dev_priv->hws_map.type = 0;
886 dev_priv->hws_map.flags = 0;
887 dev_priv->hws_map.mtrr = 0;
888
889 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
890 if (dev_priv->hws_map.handle == NULL) {
891 i915_dma_cleanup(dev);
892 dev_priv->status_gfx_addr = 0;
893 DRM_ERROR("can not ioremap virtual address for"
894 " G33 hw status page\n");
895 return -ENOMEM;
896 }
897 dev_priv->hw_status_page = dev_priv->hws_map.handle;
898
899 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
900 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
901 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
902 dev_priv->status_gfx_addr);
903 DRM_DEBUG_DRIVER("load hws at %p\n",
904 dev_priv->hw_status_page);
905 return 0;
906 }
907
908 static int i915_get_bridge_dev(struct drm_device *dev)
909 {
910 struct drm_i915_private *dev_priv = dev->dev_private;
911
912 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
913 if (!dev_priv->bridge_dev) {
914 DRM_ERROR("bridge device not found\n");
915 return -1;
916 }
917 return 0;
918 }
919
920 /**
921 * i915_probe_agp - get AGP bootup configuration
922 * @pdev: PCI device
923 * @aperture_size: returns AGP aperture configured size
924 * @preallocated_size: returns size of BIOS preallocated AGP space
925 *
926 * Since Intel integrated graphics are UMA, the BIOS has to set aside
927 * some RAM for the framebuffer at early boot. This code figures out
928 * how much was set aside so we can use it for our own purposes.
929 */
930 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
931 uint32_t *preallocated_size,
932 uint32_t *start)
933 {
934 struct drm_i915_private *dev_priv = dev->dev_private;
935 u16 tmp = 0;
936 unsigned long overhead;
937 unsigned long stolen;
938
939 /* Get the fb aperture size and "stolen" memory amount. */
940 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
941
942 *aperture_size = 1024 * 1024;
943 *preallocated_size = 1024 * 1024;
944
945 switch (dev->pdev->device) {
946 case PCI_DEVICE_ID_INTEL_82830_CGC:
947 case PCI_DEVICE_ID_INTEL_82845G_IG:
948 case PCI_DEVICE_ID_INTEL_82855GM_IG:
949 case PCI_DEVICE_ID_INTEL_82865_IG:
950 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
951 *aperture_size *= 64;
952 else
953 *aperture_size *= 128;
954 break;
955 default:
956 /* 9xx supports large sizes, just look at the length */
957 *aperture_size = pci_resource_len(dev->pdev, 2);
958 break;
959 }
960
961 /*
962 * Some of the preallocated space is taken by the GTT
963 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
964 */
965 if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev))
966 overhead = 4096;
967 else
968 overhead = (*aperture_size / 1024) + 4096;
969
970 switch (tmp & INTEL_GMCH_GMS_MASK) {
971 case INTEL_855_GMCH_GMS_DISABLED:
972 DRM_ERROR("video memory is disabled\n");
973 return -1;
974 case INTEL_855_GMCH_GMS_STOLEN_1M:
975 stolen = 1 * 1024 * 1024;
976 break;
977 case INTEL_855_GMCH_GMS_STOLEN_4M:
978 stolen = 4 * 1024 * 1024;
979 break;
980 case INTEL_855_GMCH_GMS_STOLEN_8M:
981 stolen = 8 * 1024 * 1024;
982 break;
983 case INTEL_855_GMCH_GMS_STOLEN_16M:
984 stolen = 16 * 1024 * 1024;
985 break;
986 case INTEL_855_GMCH_GMS_STOLEN_32M:
987 stolen = 32 * 1024 * 1024;
988 break;
989 case INTEL_915G_GMCH_GMS_STOLEN_48M:
990 stolen = 48 * 1024 * 1024;
991 break;
992 case INTEL_915G_GMCH_GMS_STOLEN_64M:
993 stolen = 64 * 1024 * 1024;
994 break;
995 case INTEL_GMCH_GMS_STOLEN_128M:
996 stolen = 128 * 1024 * 1024;
997 break;
998 case INTEL_GMCH_GMS_STOLEN_256M:
999 stolen = 256 * 1024 * 1024;
1000 break;
1001 case INTEL_GMCH_GMS_STOLEN_96M:
1002 stolen = 96 * 1024 * 1024;
1003 break;
1004 case INTEL_GMCH_GMS_STOLEN_160M:
1005 stolen = 160 * 1024 * 1024;
1006 break;
1007 case INTEL_GMCH_GMS_STOLEN_224M:
1008 stolen = 224 * 1024 * 1024;
1009 break;
1010 case INTEL_GMCH_GMS_STOLEN_352M:
1011 stolen = 352 * 1024 * 1024;
1012 break;
1013 default:
1014 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1015 tmp & INTEL_GMCH_GMS_MASK);
1016 return -1;
1017 }
1018 *preallocated_size = stolen - overhead;
1019 *start = overhead;
1020
1021 return 0;
1022 }
1023
1024 #define PTE_ADDRESS_MASK 0xfffff000
1025 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1026 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1027 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1028 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1029 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1030 #define PTE_VALID (1 << 0)
1031
1032 /**
1033 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1034 * @dev: drm device
1035 * @gtt_addr: address to translate
1036 *
1037 * Some chip functions require allocations from stolen space but need the
1038 * physical address of the memory in question. We use this routine
1039 * to get a physical address suitable for register programming from a given
1040 * GTT address.
1041 */
1042 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1043 unsigned long gtt_addr)
1044 {
1045 unsigned long *gtt;
1046 unsigned long entry, phys;
1047 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1048 int gtt_offset, gtt_size;
1049
1050 if (IS_I965G(dev)) {
1051 if (IS_G4X(dev) || IS_IGDNG(dev)) {
1052 gtt_offset = 2*1024*1024;
1053 gtt_size = 2*1024*1024;
1054 } else {
1055 gtt_offset = 512*1024;
1056 gtt_size = 512*1024;
1057 }
1058 } else {
1059 gtt_bar = 3;
1060 gtt_offset = 0;
1061 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1062 }
1063
1064 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1065 gtt_size);
1066 if (!gtt) {
1067 DRM_ERROR("ioremap of GTT failed\n");
1068 return 0;
1069 }
1070
1071 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1072
1073 DRM_DEBUG("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1074
1075 /* Mask out these reserved bits on this hardware. */
1076 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1077 IS_I945G(dev) || IS_I945GM(dev)) {
1078 entry &= ~PTE_ADDRESS_MASK_HIGH;
1079 }
1080
1081 /* If it's not a mapping type we know, then bail. */
1082 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1083 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1084 iounmap(gtt);
1085 return 0;
1086 }
1087
1088 if (!(entry & PTE_VALID)) {
1089 DRM_ERROR("bad GTT entry in stolen space\n");
1090 iounmap(gtt);
1091 return 0;
1092 }
1093
1094 iounmap(gtt);
1095
1096 phys =(entry & PTE_ADDRESS_MASK) |
1097 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1098
1099 DRM_DEBUG("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1100
1101 return phys;
1102 }
1103
1104 static void i915_warn_stolen(struct drm_device *dev)
1105 {
1106 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1107 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1108 }
1109
1110 static void i915_setup_compression(struct drm_device *dev, int size)
1111 {
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1113 struct drm_mm_node *compressed_fb, *compressed_llb;
1114 unsigned long cfb_base, ll_base;
1115
1116 /* Leave 1M for line length buffer & misc. */
1117 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1118 if (!compressed_fb) {
1119 i915_warn_stolen(dev);
1120 return;
1121 }
1122
1123 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1124 if (!compressed_fb) {
1125 i915_warn_stolen(dev);
1126 return;
1127 }
1128
1129 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1130 if (!cfb_base) {
1131 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1132 drm_mm_put_block(compressed_fb);
1133 }
1134
1135 if (!IS_GM45(dev)) {
1136 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1137 4096, 0);
1138 if (!compressed_llb) {
1139 i915_warn_stolen(dev);
1140 return;
1141 }
1142
1143 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1144 if (!compressed_llb) {
1145 i915_warn_stolen(dev);
1146 return;
1147 }
1148
1149 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1150 if (!ll_base) {
1151 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1152 drm_mm_put_block(compressed_fb);
1153 drm_mm_put_block(compressed_llb);
1154 }
1155 }
1156
1157 dev_priv->cfb_size = size;
1158
1159 if (IS_GM45(dev)) {
1160 g4x_disable_fbc(dev);
1161 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1162 } else {
1163 i8xx_disable_fbc(dev);
1164 I915_WRITE(FBC_CFB_BASE, cfb_base);
1165 I915_WRITE(FBC_LL_BASE, ll_base);
1166 }
1167
1168 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1169 ll_base, size >> 20);
1170 }
1171
1172 /* true = enable decode, false = disable decoder */
1173 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1174 {
1175 struct drm_device *dev = cookie;
1176
1177 intel_modeset_vga_set_state(dev, state);
1178 if (state)
1179 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1180 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1181 else
1182 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1183 }
1184
1185 static int i915_load_modeset_init(struct drm_device *dev,
1186 unsigned long prealloc_start,
1187 unsigned long prealloc_size,
1188 unsigned long agp_size)
1189 {
1190 struct drm_i915_private *dev_priv = dev->dev_private;
1191 int fb_bar = IS_I9XX(dev) ? 2 : 0;
1192 int ret = 0;
1193
1194 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1195 0xff000000;
1196
1197 if (IS_MOBILE(dev) || IS_I9XX(dev))
1198 dev_priv->cursor_needs_physical = true;
1199 else
1200 dev_priv->cursor_needs_physical = false;
1201
1202 if (IS_I965G(dev) || IS_G33(dev))
1203 dev_priv->cursor_needs_physical = false;
1204
1205 /* Basic memrange allocator for stolen space (aka vram) */
1206 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1207 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1208
1209 /* We're off and running w/KMS */
1210 dev_priv->mm.suspended = 0;
1211
1212 /* Let GEM Manage from end of prealloc space to end of aperture.
1213 *
1214 * However, leave one page at the end still bound to the scratch page.
1215 * There are a number of places where the hardware apparently
1216 * prefetches past the end of the object, and we've seen multiple
1217 * hangs with the GPU head pointer stuck in a batchbuffer bound
1218 * at the last page of the aperture. One page should be enough to
1219 * keep any prefetching inside of the aperture.
1220 */
1221 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1222
1223 mutex_lock(&dev->struct_mutex);
1224 ret = i915_gem_init_ringbuffer(dev);
1225 mutex_unlock(&dev->struct_mutex);
1226 if (ret)
1227 goto out;
1228
1229 /* Try to set up FBC with a reasonable compressed buffer size */
1230 if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) &&
1231 i915_powersave) {
1232 int cfb_size;
1233
1234 /* Try to get an 8M buffer... */
1235 if (prealloc_size > (9*1024*1024))
1236 cfb_size = 8*1024*1024;
1237 else /* fall back to 7/8 of the stolen space */
1238 cfb_size = prealloc_size * 7 / 8;
1239 i915_setup_compression(dev, cfb_size);
1240 }
1241
1242 /* Allow hardware batchbuffers unless told otherwise.
1243 */
1244 dev_priv->allow_batchbuffer = 1;
1245
1246 ret = intel_init_bios(dev);
1247 if (ret)
1248 DRM_INFO("failed to find VBIOS tables\n");
1249
1250 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1251 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1252 if (ret)
1253 goto destroy_ringbuffer;
1254
1255 ret = drm_irq_install(dev);
1256 if (ret)
1257 goto destroy_ringbuffer;
1258
1259 /* Always safe in the mode setting case. */
1260 /* FIXME: do pre/post-mode set stuff in core KMS code */
1261 dev->vblank_disable_allowed = 1;
1262
1263 /*
1264 * Initialize the hardware status page IRQ location.
1265 */
1266
1267 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1268
1269 intel_modeset_init(dev);
1270
1271 drm_helper_initial_config(dev);
1272
1273 return 0;
1274
1275 destroy_ringbuffer:
1276 i915_gem_cleanup_ringbuffer(dev);
1277 out:
1278 return ret;
1279 }
1280
1281 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1282 {
1283 struct drm_i915_master_private *master_priv;
1284
1285 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1286 if (!master_priv)
1287 return -ENOMEM;
1288
1289 master->driver_priv = master_priv;
1290 return 0;
1291 }
1292
1293 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1294 {
1295 struct drm_i915_master_private *master_priv = master->driver_priv;
1296
1297 if (!master_priv)
1298 return;
1299
1300 kfree(master_priv);
1301
1302 master->driver_priv = NULL;
1303 }
1304
1305 static void i915_get_mem_freq(struct drm_device *dev)
1306 {
1307 drm_i915_private_t *dev_priv = dev->dev_private;
1308 u32 tmp;
1309
1310 if (!IS_IGD(dev))
1311 return;
1312
1313 tmp = I915_READ(CLKCFG);
1314
1315 switch (tmp & CLKCFG_FSB_MASK) {
1316 case CLKCFG_FSB_533:
1317 dev_priv->fsb_freq = 533; /* 133*4 */
1318 break;
1319 case CLKCFG_FSB_800:
1320 dev_priv->fsb_freq = 800; /* 200*4 */
1321 break;
1322 case CLKCFG_FSB_667:
1323 dev_priv->fsb_freq = 667; /* 167*4 */
1324 break;
1325 case CLKCFG_FSB_400:
1326 dev_priv->fsb_freq = 400; /* 100*4 */
1327 break;
1328 }
1329
1330 switch (tmp & CLKCFG_MEM_MASK) {
1331 case CLKCFG_MEM_533:
1332 dev_priv->mem_freq = 533;
1333 break;
1334 case CLKCFG_MEM_667:
1335 dev_priv->mem_freq = 667;
1336 break;
1337 case CLKCFG_MEM_800:
1338 dev_priv->mem_freq = 800;
1339 break;
1340 }
1341 }
1342
1343 /**
1344 * i915_driver_load - setup chip and create an initial config
1345 * @dev: DRM device
1346 * @flags: startup flags
1347 *
1348 * The driver load routine has to do several things:
1349 * - drive output discovery via intel_modeset_init()
1350 * - initialize the memory manager
1351 * - allocate initial config memory
1352 * - setup the DRM framebuffer with the allocated memory
1353 */
1354 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1355 {
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 resource_size_t base, size;
1358 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1359 uint32_t agp_size, prealloc_size, prealloc_start;
1360
1361 /* i915 has 4 more counters */
1362 dev->counters += 4;
1363 dev->types[6] = _DRM_STAT_IRQ;
1364 dev->types[7] = _DRM_STAT_PRIMARY;
1365 dev->types[8] = _DRM_STAT_SECONDARY;
1366 dev->types[9] = _DRM_STAT_DMA;
1367
1368 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1369 if (dev_priv == NULL)
1370 return -ENOMEM;
1371
1372 dev->dev_private = (void *)dev_priv;
1373 dev_priv->dev = dev;
1374
1375 /* Add register map (needed for suspend/resume) */
1376 base = drm_get_resource_start(dev, mmio_bar);
1377 size = drm_get_resource_len(dev, mmio_bar);
1378
1379 if (i915_get_bridge_dev(dev)) {
1380 ret = -EIO;
1381 goto free_priv;
1382 }
1383
1384 dev_priv->regs = ioremap(base, size);
1385 if (!dev_priv->regs) {
1386 DRM_ERROR("failed to map registers\n");
1387 ret = -EIO;
1388 goto put_bridge;
1389 }
1390
1391 dev_priv->mm.gtt_mapping =
1392 io_mapping_create_wc(dev->agp->base,
1393 dev->agp->agp_info.aper_size * 1024*1024);
1394 if (dev_priv->mm.gtt_mapping == NULL) {
1395 ret = -EIO;
1396 goto out_rmmap;
1397 }
1398
1399 /* Set up a WC MTRR for non-PAT systems. This is more common than
1400 * one would think, because the kernel disables PAT on first
1401 * generation Core chips because WC PAT gets overridden by a UC
1402 * MTRR if present. Even if a UC MTRR isn't present.
1403 */
1404 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1405 dev->agp->agp_info.aper_size *
1406 1024 * 1024,
1407 MTRR_TYPE_WRCOMB, 1);
1408 if (dev_priv->mm.gtt_mtrr < 0) {
1409 DRM_INFO("MTRR allocation failed. Graphics "
1410 "performance may suffer.\n");
1411 }
1412
1413 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
1414 if (ret)
1415 goto out_iomapfree;
1416
1417 dev_priv->wq = create_workqueue("i915");
1418 if (dev_priv->wq == NULL) {
1419 DRM_ERROR("Failed to create our workqueue.\n");
1420 ret = -ENOMEM;
1421 goto out_iomapfree;
1422 }
1423
1424 /* enable GEM by default */
1425 dev_priv->has_gem = 1;
1426
1427 if (prealloc_size > agp_size * 3 / 4) {
1428 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1429 "memory stolen.\n",
1430 prealloc_size / 1024, agp_size / 1024);
1431 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1432 "updating the BIOS to fix).\n");
1433 dev_priv->has_gem = 0;
1434 }
1435
1436 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1437 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1438 if (IS_G4X(dev) || IS_IGDNG(dev)) {
1439 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1440 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1441 }
1442
1443 i915_gem_load(dev);
1444
1445 /* Init HWS */
1446 if (!I915_NEED_GFX_HWS(dev)) {
1447 ret = i915_init_phys_hws(dev);
1448 if (ret != 0)
1449 goto out_workqueue_free;
1450 }
1451
1452 i915_get_mem_freq(dev);
1453
1454 /* On the 945G/GM, the chipset reports the MSI capability on the
1455 * integrated graphics even though the support isn't actually there
1456 * according to the published specs. It doesn't appear to function
1457 * correctly in testing on 945G.
1458 * This may be a side effect of MSI having been made available for PEG
1459 * and the registers being closely associated.
1460 *
1461 * According to chipset errata, on the 965GM, MSI interrupts may
1462 * be lost or delayed, but we use them anyways to avoid
1463 * stuck interrupts on some machines.
1464 */
1465 if (!IS_I945G(dev) && !IS_I945GM(dev))
1466 pci_enable_msi(dev->pdev);
1467
1468 spin_lock_init(&dev_priv->user_irq_lock);
1469 spin_lock_init(&dev_priv->error_lock);
1470 dev_priv->user_irq_refcount = 0;
1471 dev_priv->trace_irq_seqno = 0;
1472
1473 ret = drm_vblank_init(dev, I915_NUM_PIPE);
1474
1475 if (ret) {
1476 (void) i915_driver_unload(dev);
1477 return ret;
1478 }
1479
1480 /* Start out suspended */
1481 dev_priv->mm.suspended = 1;
1482
1483 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1484 ret = i915_load_modeset_init(dev, prealloc_start,
1485 prealloc_size, agp_size);
1486 if (ret < 0) {
1487 DRM_ERROR("failed to init modeset\n");
1488 goto out_workqueue_free;
1489 }
1490 }
1491
1492 /* Must be done after probing outputs */
1493 /* FIXME: verify on IGDNG */
1494 if (!IS_IGDNG(dev))
1495 intel_opregion_init(dev, 0);
1496
1497 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1498 (unsigned long) dev);
1499 return 0;
1500
1501 out_workqueue_free:
1502 destroy_workqueue(dev_priv->wq);
1503 out_iomapfree:
1504 io_mapping_free(dev_priv->mm.gtt_mapping);
1505 out_rmmap:
1506 iounmap(dev_priv->regs);
1507 put_bridge:
1508 pci_dev_put(dev_priv->bridge_dev);
1509 free_priv:
1510 kfree(dev_priv);
1511 return ret;
1512 }
1513
1514 int i915_driver_unload(struct drm_device *dev)
1515 {
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517
1518 destroy_workqueue(dev_priv->wq);
1519 del_timer_sync(&dev_priv->hangcheck_timer);
1520
1521 io_mapping_free(dev_priv->mm.gtt_mapping);
1522 if (dev_priv->mm.gtt_mtrr >= 0) {
1523 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
1524 dev->agp->agp_info.aper_size * 1024 * 1024);
1525 dev_priv->mm.gtt_mtrr = -1;
1526 }
1527
1528 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1529 drm_irq_uninstall(dev);
1530 vga_client_register(dev->pdev, NULL, NULL, NULL);
1531 }
1532
1533 if (dev->pdev->msi_enabled)
1534 pci_disable_msi(dev->pdev);
1535
1536 if (dev_priv->regs != NULL)
1537 iounmap(dev_priv->regs);
1538
1539 if (!IS_IGDNG(dev))
1540 intel_opregion_free(dev, 0);
1541
1542 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1543 intel_modeset_cleanup(dev);
1544
1545 i915_gem_free_all_phys_object(dev);
1546
1547 mutex_lock(&dev->struct_mutex);
1548 i915_gem_cleanup_ringbuffer(dev);
1549 mutex_unlock(&dev->struct_mutex);
1550 drm_mm_takedown(&dev_priv->vram);
1551 i915_gem_lastclose(dev);
1552 }
1553
1554 pci_dev_put(dev_priv->bridge_dev);
1555 kfree(dev->dev_private);
1556
1557 return 0;
1558 }
1559
1560 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1561 {
1562 struct drm_i915_file_private *i915_file_priv;
1563
1564 DRM_DEBUG_DRIVER("\n");
1565 i915_file_priv = (struct drm_i915_file_private *)
1566 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
1567
1568 if (!i915_file_priv)
1569 return -ENOMEM;
1570
1571 file_priv->driver_priv = i915_file_priv;
1572
1573 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1574
1575 return 0;
1576 }
1577
1578 /**
1579 * i915_driver_lastclose - clean up after all DRM clients have exited
1580 * @dev: DRM device
1581 *
1582 * Take care of cleaning up after all DRM clients have exited. In the
1583 * mode setting case, we want to restore the kernel's initial mode (just
1584 * in case the last client left us in a bad state).
1585 *
1586 * Additionally, in the non-mode setting case, we'll tear down the AGP
1587 * and DMA structures, since the kernel won't be using them, and clea
1588 * up any GEM state.
1589 */
1590 void i915_driver_lastclose(struct drm_device * dev)
1591 {
1592 drm_i915_private_t *dev_priv = dev->dev_private;
1593
1594 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1595 drm_fb_helper_restore();
1596 return;
1597 }
1598
1599 i915_gem_lastclose(dev);
1600
1601 if (dev_priv->agp_heap)
1602 i915_mem_takedown(&(dev_priv->agp_heap));
1603
1604 i915_dma_cleanup(dev);
1605 }
1606
1607 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1608 {
1609 drm_i915_private_t *dev_priv = dev->dev_private;
1610 i915_gem_release(dev, file_priv);
1611 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1612 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1613 }
1614
1615 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1616 {
1617 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1618
1619 kfree(i915_file_priv);
1620 }
1621
1622 struct drm_ioctl_desc i915_ioctls[] = {
1623 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1624 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1625 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1626 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1627 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1628 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1629 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1630 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1631 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1632 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1633 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1634 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1635 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1636 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1637 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1638 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1639 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1640 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1641 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1642 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1643 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1644 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1645 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1646 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1647 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1648 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1649 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1650 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1651 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1652 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, 0),
1653 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1654 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1655 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1656 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1657 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
1658 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1659 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, 0),
1660 };
1661
1662 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1663
1664 /**
1665 * Determine if the device really is AGP or not.
1666 *
1667 * All Intel graphics chipsets are treated as AGP, even if they are really
1668 * PCI-e.
1669 *
1670 * \param dev The device to be tested.
1671 *
1672 * \returns
1673 * A value of 1 is always retured to indictate every i9x5 is AGP.
1674 */
1675 int i915_driver_device_is_agp(struct drm_device * dev)
1676 {
1677 return 1;
1678 }
Verdex Pro support