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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / gpu / drm / i915 / i915_suspend.c
blobbd6d8d91ca9f7e7f8f2efb046cd0bb3b502af861
1 /*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "i915_drm.h"
30 #include "i915_drv.h"
31
32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33 {
34 struct drm_i915_private *dev_priv = dev->dev_private;
35
36 if (pipe == PIPE_A)
37 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
38 else
39 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
40 }
41
42 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
43 {
44 struct drm_i915_private *dev_priv = dev->dev_private;
45 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
46 u32 *array;
47 int i;
48
49 if (!i915_pipe_enabled(dev, pipe))
50 return;
51
52 if (pipe == PIPE_A)
53 array = dev_priv->save_palette_a;
54 else
55 array = dev_priv->save_palette_b;
56
57 for(i = 0; i < 256; i++)
58 array[i] = I915_READ(reg + (i << 2));
59 }
60
61 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
62 {
63 struct drm_i915_private *dev_priv = dev->dev_private;
64 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
65 u32 *array;
66 int i;
67
68 if (!i915_pipe_enabled(dev, pipe))
69 return;
70
71 if (pipe == PIPE_A)
72 array = dev_priv->save_palette_a;
73 else
74 array = dev_priv->save_palette_b;
75
76 for(i = 0; i < 256; i++)
77 I915_WRITE(reg + (i << 2), array[i]);
78 }
79
80 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
81 {
82 struct drm_i915_private *dev_priv = dev->dev_private;
83
84 I915_WRITE8(index_port, reg);
85 return I915_READ8(data_port);
86 }
87
88 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
89 {
90 struct drm_i915_private *dev_priv = dev->dev_private;
91
92 I915_READ8(st01);
93 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
94 return I915_READ8(VGA_AR_DATA_READ);
95 }
96
97 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
98 {
99 struct drm_i915_private *dev_priv = dev->dev_private;
100
101 I915_READ8(st01);
102 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
103 I915_WRITE8(VGA_AR_DATA_WRITE, val);
104 }
105
106 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
107 {
108 struct drm_i915_private *dev_priv = dev->dev_private;
109
110 I915_WRITE8(index_port, reg);
111 I915_WRITE8(data_port, val);
112 }
113
114 static void i915_save_vga(struct drm_device *dev)
115 {
116 struct drm_i915_private *dev_priv = dev->dev_private;
117 int i;
118 u16 cr_index, cr_data, st01;
119
120 /* VGA color palette registers */
121 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
122
123 /* MSR bits */
124 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
125 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
126 cr_index = VGA_CR_INDEX_CGA;
127 cr_data = VGA_CR_DATA_CGA;
128 st01 = VGA_ST01_CGA;
129 } else {
130 cr_index = VGA_CR_INDEX_MDA;
131 cr_data = VGA_CR_DATA_MDA;
132 st01 = VGA_ST01_MDA;
133 }
134
135 /* CRT controller regs */
136 i915_write_indexed(dev, cr_index, cr_data, 0x11,
137 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
138 (~0x80));
139 for (i = 0; i <= 0x24; i++)
140 dev_priv->saveCR[i] =
141 i915_read_indexed(dev, cr_index, cr_data, i);
142 /* Make sure we don't turn off CR group 0 writes */
143 dev_priv->saveCR[0x11] &= ~0x80;
144
145 /* Attribute controller registers */
146 I915_READ8(st01);
147 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
148 for (i = 0; i <= 0x14; i++)
149 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
150 I915_READ8(st01);
151 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
152 I915_READ8(st01);
153
154 /* Graphics controller registers */
155 for (i = 0; i < 9; i++)
156 dev_priv->saveGR[i] =
157 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
158
159 dev_priv->saveGR[0x10] =
160 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
161 dev_priv->saveGR[0x11] =
162 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
163 dev_priv->saveGR[0x18] =
164 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
165
166 /* Sequencer registers */
167 for (i = 0; i < 8; i++)
168 dev_priv->saveSR[i] =
169 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
170 }
171
172 static void i915_restore_vga(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 int i;
176 u16 cr_index, cr_data, st01;
177
178 /* MSR bits */
179 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
180 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
181 cr_index = VGA_CR_INDEX_CGA;
182 cr_data = VGA_CR_DATA_CGA;
183 st01 = VGA_ST01_CGA;
184 } else {
185 cr_index = VGA_CR_INDEX_MDA;
186 cr_data = VGA_CR_DATA_MDA;
187 st01 = VGA_ST01_MDA;
188 }
189
190 /* Sequencer registers, don't write SR07 */
191 for (i = 0; i < 7; i++)
192 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
193 dev_priv->saveSR[i]);
194
195 /* CRT controller regs */
196 /* Enable CR group 0 writes */
197 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
198 for (i = 0; i <= 0x24; i++)
199 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
200
201 /* Graphics controller regs */
202 for (i = 0; i < 9; i++)
203 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
204 dev_priv->saveGR[i]);
205
206 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
207 dev_priv->saveGR[0x10]);
208 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
209 dev_priv->saveGR[0x11]);
210 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
211 dev_priv->saveGR[0x18]);
212
213 /* Attribute controller registers */
214 I915_READ8(st01); /* switch back to index mode */
215 for (i = 0; i <= 0x14; i++)
216 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
217 I915_READ8(st01); /* switch back to index mode */
218 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
219 I915_READ8(st01);
220
221 /* VGA color palette registers */
222 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
223 }
224
225 static void i915_save_modeset_reg(struct drm_device *dev)
226 {
227 struct drm_i915_private *dev_priv = dev->dev_private;
228
229 if (drm_core_check_feature(dev, DRIVER_MODESET))
230 return;
231
232 /* Pipe & plane A info */
233 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
234 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
235 dev_priv->saveFPA0 = I915_READ(FPA0);
236 dev_priv->saveFPA1 = I915_READ(FPA1);
237 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
238 if (IS_I965G(dev))
239 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
240 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
241 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
242 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
243 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
244 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
245 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
246 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
247
248 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
249 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
250 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
251 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
252 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
253 if (IS_I965G(dev)) {
254 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
255 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
256 }
257 i915_save_palette(dev, PIPE_A);
258 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
259
260 /* Pipe & plane B info */
261 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
262 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
263 dev_priv->saveFPB0 = I915_READ(FPB0);
264 dev_priv->saveFPB1 = I915_READ(FPB1);
265 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
266 if (IS_I965G(dev))
267 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
268 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
269 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
270 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
271 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
272 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
273 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
274 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
275
276 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
277 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
278 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
279 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
280 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
281 if (IS_I965GM(dev) || IS_GM45(dev)) {
282 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
283 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
284 }
285 i915_save_palette(dev, PIPE_B);
286 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
287 return;
288 }
289
290 static void i915_restore_modeset_reg(struct drm_device *dev)
291 {
292 struct drm_i915_private *dev_priv = dev->dev_private;
293
294 if (drm_core_check_feature(dev, DRIVER_MODESET))
295 return;
296
297 /* Pipe & plane A info */
298 /* Prime the clock */
299 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
300 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
301 ~DPLL_VCO_ENABLE);
302 DRM_UDELAY(150);
303 }
304 I915_WRITE(FPA0, dev_priv->saveFPA0);
305 I915_WRITE(FPA1, dev_priv->saveFPA1);
306 /* Actually enable it */
307 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
308 DRM_UDELAY(150);
309 if (IS_I965G(dev))
310 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
311 DRM_UDELAY(150);
312
313 /* Restore mode */
314 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
315 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
316 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
317 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
318 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
319 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
320 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
321
322 /* Restore plane info */
323 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
324 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
325 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
326 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
327 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
328 if (IS_I965G(dev)) {
329 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
330 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
331 }
332
333 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
334
335 i915_restore_palette(dev, PIPE_A);
336 /* Enable the plane */
337 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
338 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
339
340 /* Pipe & plane B info */
341 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
342 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
343 ~DPLL_VCO_ENABLE);
344 DRM_UDELAY(150);
345 }
346 I915_WRITE(FPB0, dev_priv->saveFPB0);
347 I915_WRITE(FPB1, dev_priv->saveFPB1);
348 /* Actually enable it */
349 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
350 DRM_UDELAY(150);
351 if (IS_I965G(dev))
352 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
353 DRM_UDELAY(150);
354
355 /* Restore mode */
356 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
357 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
358 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
359 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
360 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
361 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
362 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
363
364 /* Restore plane info */
365 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
366 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
367 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
368 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
369 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
370 if (IS_I965G(dev)) {
371 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
372 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
373 }
374
375 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
376
377 i915_restore_palette(dev, PIPE_B);
378 /* Enable the plane */
379 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
380 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
381
382 return;
383 }
384
385 void i915_save_display(struct drm_device *dev)
386 {
387 struct drm_i915_private *dev_priv = dev->dev_private;
388
389 /* Display arbitration control */
390 dev_priv->saveDSPARB = I915_READ(DSPARB);
391
392 /* This is only meaningful in non-KMS mode */
393 /* Don't save them in KMS mode */
394 i915_save_modeset_reg(dev);
395
396 /* Cursor state */
397 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
398 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
399 dev_priv->saveCURABASE = I915_READ(CURABASE);
400 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
401 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
402 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
403 if (!IS_I9XX(dev))
404 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
405
406 /* CRT state */
407 dev_priv->saveADPA = I915_READ(ADPA);
408
409 /* LVDS state */
410 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
411 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
412 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
413 if (IS_I965G(dev))
414 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
415 if (IS_MOBILE(dev) && !IS_I830(dev))
416 dev_priv->saveLVDS = I915_READ(LVDS);
417 if (!IS_I830(dev) && !IS_845G(dev))
418 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
419 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
420 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
421 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
422
423 /* Display Port state */
424 if (SUPPORTS_INTEGRATED_DP(dev)) {
425 dev_priv->saveDP_B = I915_READ(DP_B);
426 dev_priv->saveDP_C = I915_READ(DP_C);
427 dev_priv->saveDP_D = I915_READ(DP_D);
428 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
429 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
430 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
431 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
432 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
433 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
434 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
435 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
436 }
437 /* FIXME: save TV & SDVO state */
438
439 /* FBC state */
440 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
441 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
442 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
443 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
444
445 /* VGA state */
446 dev_priv->saveVGA0 = I915_READ(VGA0);
447 dev_priv->saveVGA1 = I915_READ(VGA1);
448 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
449 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
450
451 i915_save_vga(dev);
452 }
453
454 void i915_restore_display(struct drm_device *dev)
455 {
456 struct drm_i915_private *dev_priv = dev->dev_private;
457
458 /* Display arbitration */
459 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
460
461 /* Display port ratios (must be done before clock is set) */
462 if (SUPPORTS_INTEGRATED_DP(dev)) {
463 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
464 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
465 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
466 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
467 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
468 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
469 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
470 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
471 }
472
473 /* This is only meaningful in non-KMS mode */
474 /* Don't restore them in KMS mode */
475 i915_restore_modeset_reg(dev);
476
477 /* Cursor state */
478 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
479 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
480 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
481 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
482 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
483 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
484 if (!IS_I9XX(dev))
485 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
486
487 /* CRT state */
488 I915_WRITE(ADPA, dev_priv->saveADPA);
489
490 /* LVDS state */
491 if (IS_I965G(dev))
492 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
493 if (IS_MOBILE(dev) && !IS_I830(dev))
494 I915_WRITE(LVDS, dev_priv->saveLVDS);
495 if (!IS_I830(dev) && !IS_845G(dev))
496 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
497
498 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
499 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
500 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
501 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
502 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
503 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
504
505 /* Display Port state */
506 if (SUPPORTS_INTEGRATED_DP(dev)) {
507 I915_WRITE(DP_B, dev_priv->saveDP_B);
508 I915_WRITE(DP_C, dev_priv->saveDP_C);
509 I915_WRITE(DP_D, dev_priv->saveDP_D);
510 }
511 /* FIXME: restore TV & SDVO state */
512
513 /* FBC info */
514 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
515 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
516 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
517 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
518
519 /* VGA state */
520 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
521 I915_WRITE(VGA0, dev_priv->saveVGA0);
522 I915_WRITE(VGA1, dev_priv->saveVGA1);
523 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
524 DRM_UDELAY(150);
525
526 i915_restore_vga(dev);
527 }
528
529 int i915_save_state(struct drm_device *dev)
530 {
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 int i;
533
534 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
535
536 /* Render Standby */
537 if (IS_I965G(dev) && IS_MOBILE(dev))
538 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
539
540 /* Hardware status page */
541 dev_priv->saveHWS = I915_READ(HWS_PGA);
542
543 i915_save_display(dev);
544
545 /* Interrupt state */
546 dev_priv->saveIER = I915_READ(IER);
547 dev_priv->saveIMR = I915_READ(IMR);
548
549 /* Clock gating state */
550 dev_priv->saveD_STATE = I915_READ(D_STATE);
551 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */
552
553 /* Cache mode state */
554 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
555
556 /* Memory Arbitration state */
557 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
558
559 /* Scratch space */
560 for (i = 0; i < 16; i++) {
561 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
562 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
563 }
564 for (i = 0; i < 3; i++)
565 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
566
567 /* Fences */
568 if (IS_I965G(dev)) {
569 for (i = 0; i < 16; i++)
570 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
571 } else {
572 for (i = 0; i < 8; i++)
573 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
574
575 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
576 for (i = 0; i < 8; i++)
577 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
578 }
579
580 return 0;
581 }
582
583 int i915_restore_state(struct drm_device *dev)
584 {
585 struct drm_i915_private *dev_priv = dev->dev_private;
586 int i;
587
588 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
589
590 /* Render Standby */
591 if (IS_I965G(dev) && IS_MOBILE(dev))
592 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
593
594 /* Hardware status page */
595 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
596
597 /* Fences */
598 if (IS_I965G(dev)) {
599 for (i = 0; i < 16; i++)
600 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
601 } else {
602 for (i = 0; i < 8; i++)
603 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
604 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
605 for (i = 0; i < 8; i++)
606 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
607 }
608
609 i915_restore_display(dev);
610
611 /* Interrupt state */
612 I915_WRITE (IER, dev_priv->saveIER);
613 I915_WRITE (IMR, dev_priv->saveIMR);
614
615 /* Clock gating state */
616 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
617 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
618
619 /* Cache mode state */
620 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
621
622 /* Memory arbitration state */
623 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
624
625 for (i = 0; i < 16; i++) {
626 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
627 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
628 }
629 for (i = 0; i < 3; i++)
630 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
631
632 return 0;
633 }
634
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