drivers/gpu/drm/radeon/r520.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include "r520d.h"
  32
  33 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */
  34
  35 static int r520_mc_wait_for_idle(struct radeon_device *rdev)
  36 {
  37         unsigned i;
  38         uint32_t tmp;
  39
  40         for (i = 0; i < rdev->usec_timeout; i++) {
  41                 /* read MC_STATUS */
  42                 tmp = RREG32_MC(R520_MC_STATUS);
  43                 if (tmp & R520_MC_STATUS_IDLE) {
  44                         return 0;
  45                 }
  46                 DRM_UDELAY(1);
  47         }
  48         return -1;
  49 }
  50
  51 static void r520_gpu_init(struct radeon_device *rdev)
  52 {
  53         unsigned pipe_select_current, gb_pipe_select, tmp;
  54
  55         r100_hdp_reset(rdev);
  56         rv515_vga_render_disable(rdev);
  57         /*
  58          * DST_PIPE_CONFIG              0x170C
  59          * GB_TILE_CONFIG               0x4018
  60          * GB_FIFO_SIZE                 0x4024
  61          * GB_PIPE_SELECT               0x402C
  62          * GB_PIPE_SELECT2              0x4124
  63          *      Z_PIPE_SHIFT                    0
  64          *      Z_PIPE_MASK                     0x000000003
  65          * GB_FIFO_SIZE2                0x4128
  66          *      SC_SFIFO_SIZE_SHIFT             0
  67          *      SC_SFIFO_SIZE_MASK              0x000000003
  68          *      SC_MFIFO_SIZE_SHIFT             2
  69          *      SC_MFIFO_SIZE_MASK              0x00000000C
  70          *      FG_SFIFO_SIZE_SHIFT             4
  71          *      FG_SFIFO_SIZE_MASK              0x000000030
  72          *      ZB_MFIFO_SIZE_SHIFT             6
  73          *      ZB_MFIFO_SIZE_MASK              0x0000000C0
  74          * GA_ENHANCE                   0x4274
  75          * SU_REG_DEST                  0x42C8
  76          */
  77         /* workaround for RV530 */
  78         if (rdev->family == CHIP_RV530) {
  79                 WREG32(0x4128, 0xFF);
  80         }
  81         r420_pipes_init(rdev);
  82         gb_pipe_select = RREG32(0x402C);
  83         tmp = RREG32(0x170C);
  84         pipe_select_current = (tmp >> 2) & 3;
  85         tmp = (1 << pipe_select_current) |
  86               (((gb_pipe_select >> 8) & 0xF) << 4);
  87         WREG32_PLL(0x000D, tmp);
  88         if (r520_mc_wait_for_idle(rdev)) {
  89                 printk(KERN_WARNING "Failed to wait MC idle while "
  90                        "programming pipes. Bad things might happen.\n");
  91         }
  92 }
  93
  94 static void r520_vram_get_type(struct radeon_device *rdev)
  95 {
  96         uint32_t tmp;
  97
  98         rdev->mc.vram_width = 128;
  99         rdev->mc.vram_is_ddr = true;
 100         tmp = RREG32_MC(R520_MC_CNTL0);
 101         switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
 102         case 0:
 103                 rdev->mc.vram_width = 32;
 104                 break;
 105         case 1:
 106                 rdev->mc.vram_width = 64;
 107                 break;
 108         case 2:
 109                 rdev->mc.vram_width = 128;
 110                 break;
 111         case 3:
 112                 rdev->mc.vram_width = 256;
 113                 break;
 114         default:
 115                 rdev->mc.vram_width = 128;
 116                 break;
 117         }
 118         if (tmp & R520_MC_CHANNEL_SIZE)
 119                 rdev->mc.vram_width *= 2;
 120 }
 121
 122 void r520_vram_info(struct radeon_device *rdev)
 123 {
 124         fixed20_12 a;
 125
 126         r520_vram_get_type(rdev);
 127
 128         r100_vram_init_sizes(rdev);
 129         /* FIXME: we should enforce default clock in case GPU is not in
 130          * default setup
 131          */
 132         a.full = rfixed_const(100);
 133         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 134         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 135 }
 136
 137 void r520_mc_program(struct radeon_device *rdev)
 138 {
 139         struct rv515_mc_save save;
 140
 141         /* Stops all mc clients */
 142         rv515_mc_stop(rdev, &save);
 143
 144         /* Wait for mc idle */
 145         if (r520_mc_wait_for_idle(rdev))
 146                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 147         /* Write VRAM size in case we are limiting it */
 148         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 149         /* Program MC, should be a 32bits limited address space */
 150         WREG32_MC(R_000004_MC_FB_LOCATION,
 151                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
 152                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
 153         WREG32(R_000134_HDP_FB_LOCATION,
 154                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 155         if (rdev->flags & RADEON_IS_AGP) {
 156                 WREG32_MC(R_000005_MC_AGP_LOCATION,
 157                         S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
 158                         S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
 159                 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
 160                 WREG32_MC(R_000007_AGP_BASE_2,
 161                         S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
 162         } else {
 163                 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF);
 164                 WREG32_MC(R_000006_AGP_BASE, 0);
 165                 WREG32_MC(R_000007_AGP_BASE_2, 0);
 166         }
 167
 168         rv515_mc_resume(rdev, &save);
 169 }
 170
 171 static int r520_startup(struct radeon_device *rdev)
 172 {
 173         int r;
 174
 175         r520_mc_program(rdev);
 176         /* Resume clock */
 177         rv515_clock_startup(rdev);
 178         /* Initialize GPU configuration (# pipes, ...) */
 179         r520_gpu_init(rdev);
 180         /* Initialize GART (initialize after TTM so we can allocate
 181          * memory through TTM but finalize after TTM) */
 182         if (rdev->flags & RADEON_IS_PCIE) {
 183                 r = rv370_pcie_gart_enable(rdev);
 184                 if (r)
 185                         return r;
 186         }
 187         /* Enable IRQ */
 188         rdev->irq.sw_int = true;
 189         rs600_irq_set(rdev);
 190         /* 1M ring buffer */
 191         r = r100_cp_init(rdev, 1024 * 1024);
 192         if (r) {
 193                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 194                 return r;
 195         }
 196         r = r100_wb_init(rdev);
 197         if (r)
 198                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 199         r = r100_ib_init(rdev);
 200         if (r) {
 201                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 202                 return r;
 203         }
 204         return 0;
 205 }
 206
 207 int r520_resume(struct radeon_device *rdev)
 208 {
 209         /* Make sur GART are not working */
 210         if (rdev->flags & RADEON_IS_PCIE)
 211                 rv370_pcie_gart_disable(rdev);
 212         /* Resume clock before doing reset */
 213         rv515_clock_startup(rdev);
 214         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 215         if (radeon_gpu_reset(rdev)) {
 216                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 217                         RREG32(R_000E40_RBBM_STATUS),
 218                         RREG32(R_0007C0_CP_STAT));
 219         }
 220         /* post */
 221         atom_asic_init(rdev->mode_info.atom_context);
 222         /* Resume clock after posting */
 223         rv515_clock_startup(rdev);
 224         return r520_startup(rdev);
 225 }
 226
 227 int r520_init(struct radeon_device *rdev)
 228 {
 229         int r;
 230
 231         /* Initialize scratch registers */
 232         radeon_scratch_init(rdev);
 233         /* Initialize surface registers */
 234         radeon_surface_init(rdev);
 235         /* TODO: disable VGA need to use VGA request */
 236         /* BIOS*/
 237         if (!radeon_get_bios(rdev)) {
 238                 if (ASIC_IS_AVIVO(rdev))
 239                         return -EINVAL;
 240         }
 241         if (rdev->is_atom_bios) {
 242                 r = radeon_atombios_init(rdev);
 243                 if (r)
 244                         return r;
 245         } else {
 246                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 247                 return -EINVAL;
 248         }
 249         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 250         if (radeon_gpu_reset(rdev)) {
 251                 dev_warn(rdev->dev,
 252                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 253                         RREG32(R_000E40_RBBM_STATUS),
 254                         RREG32(R_0007C0_CP_STAT));
 255         }
 256         /* check if cards are posted or not */
 257         if (!radeon_card_posted(rdev) && rdev->bios) {
 258                 DRM_INFO("GPU not posted. posting now...\n");
 259                 atom_asic_init(rdev->mode_info.atom_context);
 260         }
 261         /* Initialize clocks */
 262         radeon_get_clock_info(rdev->ddev);
 263         /* Get vram informations */
 264         r520_vram_info(rdev);
 265         /* Initialize memory controller (also test AGP) */
 266         r = r420_mc_init(rdev);
 267         if (r)
 268                 return r;
 269         rv515_debugfs(rdev);
 270         /* Fence driver */
 271         r = radeon_fence_driver_init(rdev);
 272         if (r)
 273                 return r;
 274         r = radeon_irq_kms_init(rdev);
 275         if (r)
 276                 return r;
 277         /* Memory manager */
 278         r = radeon_object_init(rdev);
 279         if (r)
 280                 return r;
 281         r = rv370_pcie_gart_init(rdev);
 282         if (r)
 283                 return r;
 284         rv515_set_safe_registers(rdev);
 285         rdev->accel_working = true;
 286         r = r520_startup(rdev);
 287         if (r) {
 288                 /* Somethings want wront with the accel init stop accel */
 289                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 290                 rv515_suspend(rdev);
 291                 r100_cp_fini(rdev);
 292                 r100_wb_fini(rdev);
 293                 r100_ib_fini(rdev);
 294                 rv370_pcie_gart_fini(rdev);
 295                 radeon_agp_fini(rdev);
 296                 radeon_irq_kms_fini(rdev);
 297                 rdev->accel_working = false;
 298         }
 299         return 0;
 300 }