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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / gpu / drm / radeon / radeon_display.c
blob3655d91993a6bd8d1d46034b6262e93553a8ef81
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
72 {
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77 uint32_t dac2_cntl;
78
79 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
80 if (radeon_crtc->crtc_id == 0)
81 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
82 else
83 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
84 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
85
86 WREG8(RADEON_PALETTE_INDEX, 0);
87 for (i = 0; i < 256; i++) {
88 WREG32(RADEON_PALETTE_30_DATA,
89 (radeon_crtc->lut_r[i] << 20) |
90 (radeon_crtc->lut_g[i] << 10) |
91 (radeon_crtc->lut_b[i] << 0));
92 }
93 }
94
95 void radeon_crtc_load_lut(struct drm_crtc *crtc)
96 {
97 struct drm_device *dev = crtc->dev;
98 struct radeon_device *rdev = dev->dev_private;
99
100 if (!crtc->enabled)
101 return;
102
103 if (ASIC_IS_AVIVO(rdev))
104 avivo_crtc_load_lut(crtc);
105 else
106 legacy_crtc_load_lut(crtc);
107 }
108
109 /** Sets the color ramps on behalf of fbcon */
110 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
111 u16 blue, int regno)
112 {
113 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
114
115 radeon_crtc->lut_r[regno] = red >> 6;
116 radeon_crtc->lut_g[regno] = green >> 6;
117 radeon_crtc->lut_b[regno] = blue >> 6;
118 }
119
120 /** Gets the color ramps on behalf of fbcon */
121 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
122 u16 *blue, int regno)
123 {
124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
125
126 *red = radeon_crtc->lut_r[regno] << 6;
127 *green = radeon_crtc->lut_g[regno] << 6;
128 *blue = radeon_crtc->lut_b[regno] << 6;
129 }
130
131 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
132 u16 *blue, uint32_t size)
133 {
134 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
135 int i;
136
137 if (size != 256) {
138 return;
139 }
140 if (crtc->fb == NULL) {
141 return;
142 }
143
144 /* userspace palettes are always correct as is */
145 for (i = 0; i < 256; i++) {
146 radeon_crtc->lut_r[i] = red[i] >> 6;
147 radeon_crtc->lut_g[i] = green[i] >> 6;
148 radeon_crtc->lut_b[i] = blue[i] >> 6;
149 }
150
151 radeon_crtc_load_lut(crtc);
152 }
153
154 static void radeon_crtc_destroy(struct drm_crtc *crtc)
155 {
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157
158 drm_crtc_cleanup(crtc);
159 kfree(radeon_crtc);
160 }
161
162 static const struct drm_crtc_funcs radeon_crtc_funcs = {
163 .cursor_set = radeon_crtc_cursor_set,
164 .cursor_move = radeon_crtc_cursor_move,
165 .gamma_set = radeon_crtc_gamma_set,
166 .set_config = drm_crtc_helper_set_config,
167 .destroy = radeon_crtc_destroy,
168 };
169
170 static void radeon_crtc_init(struct drm_device *dev, int index)
171 {
172 struct radeon_device *rdev = dev->dev_private;
173 struct radeon_crtc *radeon_crtc;
174 int i;
175
176 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
177 if (radeon_crtc == NULL)
178 return;
179
180 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
181
182 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
183 radeon_crtc->crtc_id = index;
184 rdev->mode_info.crtcs[index] = radeon_crtc;
185
186 #if 0
187 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
188 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
189 radeon_crtc->mode_set.num_connectors = 0;
190 #endif
191
192 for (i = 0; i < 256; i++) {
193 radeon_crtc->lut_r[i] = i << 2;
194 radeon_crtc->lut_g[i] = i << 2;
195 radeon_crtc->lut_b[i] = i << 2;
196 }
197
198 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
199 radeon_atombios_init_crtc(dev, radeon_crtc);
200 else
201 radeon_legacy_init_crtc(dev, radeon_crtc);
202 }
203
204 static const char *encoder_names[34] = {
205 "NONE",
206 "INTERNAL_LVDS",
207 "INTERNAL_TMDS1",
208 "INTERNAL_TMDS2",
209 "INTERNAL_DAC1",
210 "INTERNAL_DAC2",
211 "INTERNAL_SDVOA",
212 "INTERNAL_SDVOB",
213 "SI170B",
214 "CH7303",
215 "CH7301",
216 "INTERNAL_DVO1",
217 "EXTERNAL_SDVOA",
218 "EXTERNAL_SDVOB",
219 "TITFP513",
220 "INTERNAL_LVTM1",
221 "VT1623",
222 "HDMI_SI1930",
223 "HDMI_INTERNAL",
224 "INTERNAL_KLDSCP_TMDS1",
225 "INTERNAL_KLDSCP_DVO1",
226 "INTERNAL_KLDSCP_DAC1",
227 "INTERNAL_KLDSCP_DAC2",
228 "SI178",
229 "MVPU_FPGA",
230 "INTERNAL_DDI",
231 "VT1625",
232 "HDMI_SI1932",
233 "DP_AN9801",
234 "DP_DP501",
235 "INTERNAL_UNIPHY",
236 "INTERNAL_KLDSCP_LVTMA",
237 "INTERNAL_UNIPHY1",
238 "INTERNAL_UNIPHY2",
239 };
240
241 static const char *connector_names[13] = {
242 "Unknown",
243 "VGA",
244 "DVI-I",
245 "DVI-D",
246 "DVI-A",
247 "Composite",
248 "S-video",
249 "LVDS",
250 "Component",
251 "DIN",
252 "DisplayPort",
253 "HDMI-A",
254 "HDMI-B",
255 };
256
257 static void radeon_print_display_setup(struct drm_device *dev)
258 {
259 struct drm_connector *connector;
260 struct radeon_connector *radeon_connector;
261 struct drm_encoder *encoder;
262 struct radeon_encoder *radeon_encoder;
263 uint32_t devices;
264 int i = 0;
265
266 DRM_INFO("Radeon Display Connectors\n");
267 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
268 radeon_connector = to_radeon_connector(connector);
269 DRM_INFO("Connector %d:\n", i);
270 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
271 if (radeon_connector->ddc_bus)
272 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
273 radeon_connector->ddc_bus->rec.mask_clk_reg,
274 radeon_connector->ddc_bus->rec.mask_data_reg,
275 radeon_connector->ddc_bus->rec.a_clk_reg,
276 radeon_connector->ddc_bus->rec.a_data_reg,
277 radeon_connector->ddc_bus->rec.put_clk_reg,
278 radeon_connector->ddc_bus->rec.put_data_reg,
279 radeon_connector->ddc_bus->rec.get_clk_reg,
280 radeon_connector->ddc_bus->rec.get_data_reg);
281 DRM_INFO(" Encoders:\n");
282 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
283 radeon_encoder = to_radeon_encoder(encoder);
284 devices = radeon_encoder->devices & radeon_connector->devices;
285 if (devices) {
286 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
287 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
288 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
289 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
290 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
291 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
292 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
293 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
294 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
295 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
296 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
297 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
298 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
299 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
300 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
301 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
302 if (devices & ATOM_DEVICE_TV1_SUPPORT)
303 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
304 if (devices & ATOM_DEVICE_CV_SUPPORT)
305 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
306 }
307 }
308 i++;
309 }
310 }
311
312 static bool radeon_setup_enc_conn(struct drm_device *dev)
313 {
314 struct radeon_device *rdev = dev->dev_private;
315 struct drm_connector *drm_connector;
316 bool ret = false;
317
318 if (rdev->bios) {
319 if (rdev->is_atom_bios) {
320 if (rdev->family >= CHIP_R600)
321 ret = radeon_get_atom_connector_info_from_object_table(dev);
322 else
323 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
324 } else
325 ret = radeon_get_legacy_connector_info_from_bios(dev);
326 } else {
327 if (!ASIC_IS_AVIVO(rdev))
328 ret = radeon_get_legacy_connector_info_from_table(dev);
329 }
330 if (ret) {
331 radeon_print_display_setup(dev);
332 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
333 radeon_ddc_dump(drm_connector);
334 }
335
336 return ret;
337 }
338
339 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
340 {
341 struct edid *edid;
342 int ret = 0;
343
344 if (!radeon_connector->ddc_bus)
345 return -1;
346 if (!radeon_connector->edid) {
347 radeon_i2c_do_lock(radeon_connector, 1);
348 edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
349 radeon_i2c_do_lock(radeon_connector, 0);
350 } else
351 edid = radeon_connector->edid;
352
353 if (edid) {
354 /* update digital bits here */
355 if (edid->input & DRM_EDID_INPUT_DIGITAL)
356 radeon_connector->use_digital = 1;
357 else
358 radeon_connector->use_digital = 0;
359 drm_mode_connector_update_edid_property(&radeon_connector->base, edid);
360 ret = drm_add_edid_modes(&radeon_connector->base, edid);
361 kfree(edid);
362 return ret;
363 }
364 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
365 return 0;
366 }
367
368 static int radeon_ddc_dump(struct drm_connector *connector)
369 {
370 struct edid *edid;
371 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
372 int ret = 0;
373
374 if (!radeon_connector->ddc_bus)
375 return -1;
376 radeon_i2c_do_lock(radeon_connector, 1);
377 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
378 radeon_i2c_do_lock(radeon_connector, 0);
379 if (edid) {
380 kfree(edid);
381 }
382 return ret;
383 }
384
385 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
386 {
387 uint64_t mod;
388
389 n += d / 2;
390
391 mod = do_div(n, d);
392 return n;
393 }
394
395 void radeon_compute_pll(struct radeon_pll *pll,
396 uint64_t freq,
397 uint32_t *dot_clock_p,
398 uint32_t *fb_div_p,
399 uint32_t *frac_fb_div_p,
400 uint32_t *ref_div_p,
401 uint32_t *post_div_p,
402 int flags)
403 {
404 uint32_t min_ref_div = pll->min_ref_div;
405 uint32_t max_ref_div = pll->max_ref_div;
406 uint32_t min_fractional_feed_div = 0;
407 uint32_t max_fractional_feed_div = 0;
408 uint32_t best_vco = pll->best_vco;
409 uint32_t best_post_div = 1;
410 uint32_t best_ref_div = 1;
411 uint32_t best_feedback_div = 1;
412 uint32_t best_frac_feedback_div = 0;
413 uint32_t best_freq = -1;
414 uint32_t best_error = 0xffffffff;
415 uint32_t best_vco_diff = 1;
416 uint32_t post_div;
417
418 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
419 freq = freq * 1000;
420
421 if (flags & RADEON_PLL_USE_REF_DIV)
422 min_ref_div = max_ref_div = pll->reference_div;
423 else {
424 while (min_ref_div < max_ref_div-1) {
425 uint32_t mid = (min_ref_div + max_ref_div) / 2;
426 uint32_t pll_in = pll->reference_freq / mid;
427 if (pll_in < pll->pll_in_min)
428 max_ref_div = mid;
429 else if (pll_in > pll->pll_in_max)
430 min_ref_div = mid;
431 else
432 break;
433 }
434 }
435
436 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) {
437 min_fractional_feed_div = pll->min_frac_feedback_div;
438 max_fractional_feed_div = pll->max_frac_feedback_div;
439 }
440
441 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
442 uint32_t ref_div;
443
444 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
445 continue;
446
447 /* legacy radeons only have a few post_divs */
448 if (flags & RADEON_PLL_LEGACY) {
449 if ((post_div == 5) ||
450 (post_div == 7) ||
451 (post_div == 9) ||
452 (post_div == 10) ||
453 (post_div == 11) ||
454 (post_div == 13) ||
455 (post_div == 14) ||
456 (post_div == 15))
457 continue;
458 }
459
460 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
461 uint32_t feedback_div, current_freq = 0, error, vco_diff;
462 uint32_t pll_in = pll->reference_freq / ref_div;
463 uint32_t min_feed_div = pll->min_feedback_div;
464 uint32_t max_feed_div = pll->max_feedback_div + 1;
465
466 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
467 continue;
468
469 while (min_feed_div < max_feed_div) {
470 uint32_t vco;
471 uint32_t min_frac_feed_div = min_fractional_feed_div;
472 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
473 uint32_t frac_feedback_div;
474 uint64_t tmp;
475
476 feedback_div = (min_feed_div + max_feed_div) / 2;
477
478 tmp = (uint64_t)pll->reference_freq * feedback_div;
479 vco = radeon_div(tmp, ref_div);
480
481 if (vco < pll->pll_out_min) {
482 min_feed_div = feedback_div + 1;
483 continue;
484 } else if (vco > pll->pll_out_max) {
485 max_feed_div = feedback_div;
486 continue;
487 }
488
489 while (min_frac_feed_div < max_frac_feed_div) {
490 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
491 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
492 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
493 current_freq = radeon_div(tmp, ref_div * post_div);
494
495 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
496 error = freq - current_freq;
497 error = error < 0 ? 0xffffffff : error;
498 } else
499 error = abs(current_freq - freq);
500 vco_diff = abs(vco - best_vco);
501
502 if ((best_vco == 0 && error < best_error) ||
503 (best_vco != 0 &&
504 (error < best_error - 100 ||
505 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
506 best_post_div = post_div;
507 best_ref_div = ref_div;
508 best_feedback_div = feedback_div;
509 best_frac_feedback_div = frac_feedback_div;
510 best_freq = current_freq;
511 best_error = error;
512 best_vco_diff = vco_diff;
513 } else if (current_freq == freq) {
514 if (best_freq == -1) {
515 best_post_div = post_div;
516 best_ref_div = ref_div;
517 best_feedback_div = feedback_div;
518 best_frac_feedback_div = frac_feedback_div;
519 best_freq = current_freq;
520 best_error = error;
521 best_vco_diff = vco_diff;
522 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
523 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
524 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
525 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
526 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
527 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
528 best_post_div = post_div;
529 best_ref_div = ref_div;
530 best_feedback_div = feedback_div;
531 best_frac_feedback_div = frac_feedback_div;
532 best_freq = current_freq;
533 best_error = error;
534 best_vco_diff = vco_diff;
535 }
536 }
537 if (current_freq < freq)
538 min_frac_feed_div = frac_feedback_div + 1;
539 else
540 max_frac_feed_div = frac_feedback_div;
541 }
542 if (current_freq < freq)
543 min_feed_div = feedback_div + 1;
544 else
545 max_feed_div = feedback_div;
546 }
547 }
548 }
549
550 *dot_clock_p = best_freq / 10000;
551 *fb_div_p = best_feedback_div;
552 *frac_fb_div_p = best_frac_feedback_div;
553 *ref_div_p = best_ref_div;
554 *post_div_p = best_post_div;
555 }
556
557 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
558 {
559 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
560 struct drm_device *dev = fb->dev;
561
562 if (fb->fbdev)
563 radeonfb_remove(dev, fb);
564
565 if (radeon_fb->obj) {
566 radeon_gem_object_unpin(radeon_fb->obj);
567 mutex_lock(&dev->struct_mutex);
568 drm_gem_object_unreference(radeon_fb->obj);
569 mutex_unlock(&dev->struct_mutex);
570 }
571 drm_framebuffer_cleanup(fb);
572 kfree(radeon_fb);
573 }
574
575 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
576 struct drm_file *file_priv,
577 unsigned int *handle)
578 {
579 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
580
581 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
582 }
583
584 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
585 .destroy = radeon_user_framebuffer_destroy,
586 .create_handle = radeon_user_framebuffer_create_handle,
587 };
588
589 struct drm_framebuffer *
590 radeon_framebuffer_create(struct drm_device *dev,
591 struct drm_mode_fb_cmd *mode_cmd,
592 struct drm_gem_object *obj)
593 {
594 struct radeon_framebuffer *radeon_fb;
595
596 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
597 if (radeon_fb == NULL) {
598 return NULL;
599 }
600 drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
601 drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
602 radeon_fb->obj = obj;
603 return &radeon_fb->base;
604 }
605
606 static struct drm_framebuffer *
607 radeon_user_framebuffer_create(struct drm_device *dev,
608 struct drm_file *file_priv,
609 struct drm_mode_fb_cmd *mode_cmd)
610 {
611 struct drm_gem_object *obj;
612
613 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
614
615 return radeon_framebuffer_create(dev, mode_cmd, obj);
616 }
617
618 static const struct drm_mode_config_funcs radeon_mode_funcs = {
619 .fb_create = radeon_user_framebuffer_create,
620 .fb_changed = radeonfb_probe,
621 };
622
623 struct drm_prop_enum_list {
624 int type;
625 char *name;
626 };
627
628 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
629 { { 0, "driver" },
630 { 1, "bios" },
631 };
632
633 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
634 { { TV_STD_NTSC, "ntsc" },
635 { TV_STD_PAL, "pal" },
636 { TV_STD_PAL_M, "pal-m" },
637 { TV_STD_PAL_60, "pal-60" },
638 { TV_STD_NTSC_J, "ntsc-j" },
639 { TV_STD_SCART_PAL, "scart-pal" },
640 { TV_STD_PAL_CN, "pal-cn" },
641 { TV_STD_SECAM, "secam" },
642 };
643
644 int radeon_modeset_create_props(struct radeon_device *rdev)
645 {
646 int i, sz;
647
648 if (rdev->is_atom_bios) {
649 rdev->mode_info.coherent_mode_property =
650 drm_property_create(rdev->ddev,
651 DRM_MODE_PROP_RANGE,
652 "coherent", 2);
653 if (!rdev->mode_info.coherent_mode_property)
654 return -ENOMEM;
655
656 rdev->mode_info.coherent_mode_property->values[0] = 0;
657 rdev->mode_info.coherent_mode_property->values[0] = 1;
658 }
659
660 if (!ASIC_IS_AVIVO(rdev)) {
661 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
662 rdev->mode_info.tmds_pll_property =
663 drm_property_create(rdev->ddev,
664 DRM_MODE_PROP_ENUM,
665 "tmds_pll", sz);
666 for (i = 0; i < sz; i++) {
667 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
668 i,
669 radeon_tmds_pll_enum_list[i].type,
670 radeon_tmds_pll_enum_list[i].name);
671 }
672 }
673
674 rdev->mode_info.load_detect_property =
675 drm_property_create(rdev->ddev,
676 DRM_MODE_PROP_RANGE,
677 "load detection", 2);
678 if (!rdev->mode_info.load_detect_property)
679 return -ENOMEM;
680 rdev->mode_info.load_detect_property->values[0] = 0;
681 rdev->mode_info.load_detect_property->values[0] = 1;
682
683 drm_mode_create_scaling_mode_property(rdev->ddev);
684
685 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
686 rdev->mode_info.tv_std_property =
687 drm_property_create(rdev->ddev,
688 DRM_MODE_PROP_ENUM,
689 "tv standard", sz);
690 for (i = 0; i < sz; i++) {
691 drm_property_add_enum(rdev->mode_info.tv_std_property,
692 i,
693 radeon_tv_std_enum_list[i].type,
694 radeon_tv_std_enum_list[i].name);
695 }
696
697 return 0;
698 }
699
700 int radeon_modeset_init(struct radeon_device *rdev)
701 {
702 int num_crtc = 2, i;
703 int ret;
704
705 drm_mode_config_init(rdev->ddev);
706 rdev->mode_info.mode_config_initialized = true;
707
708 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
709
710 if (ASIC_IS_AVIVO(rdev)) {
711 rdev->ddev->mode_config.max_width = 8192;
712 rdev->ddev->mode_config.max_height = 8192;
713 } else {
714 rdev->ddev->mode_config.max_width = 4096;
715 rdev->ddev->mode_config.max_height = 4096;
716 }
717
718 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
719
720 ret = radeon_modeset_create_props(rdev);
721 if (ret) {
722 return ret;
723 }
724
725 if (rdev->flags & RADEON_SINGLE_CRTC)
726 num_crtc = 1;
727
728 /* allocate crtcs */
729 for (i = 0; i < num_crtc; i++) {
730 radeon_crtc_init(rdev->ddev, i);
731 }
732
733 /* okay we should have all the bios connectors */
734 ret = radeon_setup_enc_conn(rdev->ddev);
735 if (!ret) {
736 return ret;
737 }
738 drm_helper_initial_config(rdev->ddev);
739 return 0;
740 }
741
742 void radeon_modeset_fini(struct radeon_device *rdev)
743 {
744 if (rdev->mode_info.mode_config_initialized) {
745 drm_mode_config_cleanup(rdev->ddev);
746 rdev->mode_info.mode_config_initialized = false;
747 }
748 }
749
750 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
751 struct drm_display_mode *mode,
752 struct drm_display_mode *adjusted_mode)
753 {
754 struct drm_device *dev = crtc->dev;
755 struct drm_encoder *encoder;
756 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
757 struct radeon_encoder *radeon_encoder;
758 bool first = true;
759
760 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
761 radeon_encoder = to_radeon_encoder(encoder);
762 if (encoder->crtc != crtc)
763 continue;
764 if (first) {
765 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
766 memcpy(&radeon_crtc->native_mode,
767 &radeon_encoder->native_mode,
768 sizeof(struct radeon_native_mode));
769 first = false;
770 } else {
771 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
772 /* WARNING: Right now this can't happen but
773 * in the future we need to check that scaling
774 * are consistent accross different encoder
775 * (ie all encoder can work with the same
776 * scaling).
777 */
778 DRM_ERROR("Scaling not consistent accross encoder.\n");
779 return false;
780 }
781 }
782 }
783 if (radeon_crtc->rmx_type != RMX_OFF) {
784 fixed20_12 a, b;
785 a.full = rfixed_const(crtc->mode.vdisplay);
786 b.full = rfixed_const(radeon_crtc->native_mode.panel_xres);
787 radeon_crtc->vsc.full = rfixed_div(a, b);
788 a.full = rfixed_const(crtc->mode.hdisplay);
789 b.full = rfixed_const(radeon_crtc->native_mode.panel_yres);
790 radeon_crtc->hsc.full = rfixed_div(a, b);
791 } else {
792 radeon_crtc->vsc.full = rfixed_const(1);
793 radeon_crtc->hsc.full = rfixed_const(1);
794 }
795 return true;
796 }
Verdex Pro support