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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / media / video / pxa_camera.c
blob6952e9602d5d50407d6d98a3d4fe7058b7ab8a35
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29
30 #include <media/v4l2-common.h>
31 #include <media/v4l2-dev.h>
32 #include <media/videobuf-dma-sg.h>
33 #include <media/soc_camera.h>
34
35 #include <linux/videodev2.h>
36
37 #include <mach/dma.h>
38 #include <mach/camera.h>
39
40 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
41 #define PXA_CAM_DRV_NAME "pxa27x-camera"
42
43 /* Camera Interface */
44 #define CICR0 0x0000
45 #define CICR1 0x0004
46 #define CICR2 0x0008
47 #define CICR3 0x000C
48 #define CICR4 0x0010
49 #define CISR 0x0014
50 #define CIFR 0x0018
51 #define CITOR 0x001C
52 #define CIBR0 0x0028
53 #define CIBR1 0x0030
54 #define CIBR2 0x0038
55
56 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
57 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
58 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
59 #define CICR0_ENB (1 << 28) /* Camera interface enable */
60 #define CICR0_DIS (1 << 27) /* Camera interface disable */
61 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
62 #define CICR0_TOM (1 << 9) /* Time-out mask */
63 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
64 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
65 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
66 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
67 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
68 #define CICR0_CDM (1 << 3) /* Disable-done mask */
69 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
70 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
71 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
72
73 #define CICR1_TBIT (1 << 31) /* Transparency bit */
74 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
75 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
76 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
77 #define CICR1_RGB_F (1 << 11) /* RGB format */
78 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
79 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
80 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
81 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
82 #define CICR1_DW (0x7 << 0) /* Data width mask */
83
84 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
85 wait count mask */
86 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
87 wait count mask */
88 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
89 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
90 wait count mask */
91 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
92 wait count mask */
93
94 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
95 wait count mask */
96 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
97 wait count mask */
98 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
99 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
100 wait count mask */
101 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
102
103 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
104 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
105 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
106 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
107 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
108 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
109 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
110 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
111
112 #define CISR_FTO (1 << 15) /* FIFO time-out */
113 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
114 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
115 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
116 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
117 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
118 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
119 #define CISR_EOL (1 << 8) /* End of line */
120 #define CISR_PAR_ERR (1 << 7) /* Parity error */
121 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
122 #define CISR_CDD (1 << 5) /* Camera interface disable done */
123 #define CISR_SOF (1 << 4) /* Start of frame */
124 #define CISR_EOF (1 << 3) /* End of frame */
125 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
126 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
127 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
128
129 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
130 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
131 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
132 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
133 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
134 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
135 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
136 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
137
138 #define CICR0_SIM_MP (0 << 24)
139 #define CICR0_SIM_SP (1 << 24)
140 #define CICR0_SIM_MS (2 << 24)
141 #define CICR0_SIM_EP (3 << 24)
142 #define CICR0_SIM_ES (4 << 24)
143
144 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
145 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
146 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
147 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
148 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
149
150 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
151 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
152 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
153 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
154 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
155
156 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
157 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
158 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
159 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
160
161 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
162 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
163 CICR0_EOFM | CICR0_FOM)
164
165 /*
166 * Structures
167 */
168 enum pxa_camera_active_dma {
169 DMA_Y = 0x1,
170 DMA_U = 0x2,
171 DMA_V = 0x4,
172 };
173
174 /* descriptor needed for the PXA DMA engine */
175 struct pxa_cam_dma {
176 dma_addr_t sg_dma;
177 struct pxa_dma_desc *sg_cpu;
178 size_t sg_size;
179 int sglen;
180 };
181
182 /* buffer for one video frame */
183 struct pxa_buffer {
184 /* common v4l buffer stuff -- must be first */
185 struct videobuf_buffer vb;
186
187 const struct soc_camera_data_format *fmt;
188
189 /* our descriptor lists for Y, U and V channels */
190 struct pxa_cam_dma dmas[3];
191
192 int inwork;
193
194 enum pxa_camera_active_dma active_dma;
195 };
196
197 struct pxa_camera_dev {
198 struct soc_camera_host soc_host;
199 /* PXA27x is only supposed to handle one camera on its Quick Capture
200 * interface. If anyone ever builds hardware to enable more than
201 * one camera, they will have to modify this driver too */
202 struct soc_camera_device *icd;
203 struct clk *clk;
204
205 unsigned int irq;
206 void __iomem *base;
207
208 int channels;
209 unsigned int dma_chans[3];
210
211 struct pxacamera_platform_data *pdata;
212 struct resource *res;
213 unsigned long platform_flags;
214 unsigned long ciclk;
215 unsigned long mclk;
216 u32 mclk_divisor;
217
218 struct list_head capture;
219
220 spinlock_t lock;
221
222 struct pxa_buffer *active;
223 struct pxa_dma_desc *sg_tail[3];
224
225 u32 save_cicr[5];
226 };
227
228 struct pxa_cam {
229 unsigned long flags;
230 };
231
232 static const char *pxa_cam_driver_description = "PXA_Camera";
233
234 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
235
236 /*
237 * Videobuf operations
238 */
239 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
240 unsigned int *size)
241 {
242 struct soc_camera_device *icd = vq->priv_data;
243
244 dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size);
245
246 *size = roundup(icd->user_width * icd->user_height *
247 ((icd->current_fmt->depth + 7) >> 3), 8);
248
249 if (0 == *count)
250 *count = 32;
251 while (*size * *count > vid_limit * 1024 * 1024)
252 (*count)--;
253
254 return 0;
255 }
256
257 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
258 {
259 struct soc_camera_device *icd = vq->priv_data;
260 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
261 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
262 int i;
263
264 BUG_ON(in_interrupt());
265
266 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
267 &buf->vb, buf->vb.baddr, buf->vb.bsize);
268
269 /* This waits until this buffer is out of danger, i.e., until it is no
270 * longer in STATE_QUEUED or STATE_ACTIVE */
271 videobuf_waiton(&buf->vb, 0, 0);
272 videobuf_dma_unmap(vq, dma);
273 videobuf_dma_free(dma);
274
275 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
276 if (buf->dmas[i].sg_cpu)
277 dma_free_coherent(ici->v4l2_dev.dev,
278 buf->dmas[i].sg_size,
279 buf->dmas[i].sg_cpu,
280 buf->dmas[i].sg_dma);
281 buf->dmas[i].sg_cpu = NULL;
282 }
283
284 buf->vb.state = VIDEOBUF_NEEDS_INIT;
285 }
286
287 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
288 int sg_first_ofs, int size)
289 {
290 int i, offset, dma_len, xfer_len;
291 struct scatterlist *sg;
292
293 offset = sg_first_ofs;
294 for_each_sg(sglist, sg, sglen, i) {
295 dma_len = sg_dma_len(sg);
296
297 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
298 xfer_len = roundup(min(dma_len - offset, size), 8);
299
300 size = max(0, size - xfer_len);
301 offset = 0;
302 if (size == 0)
303 break;
304 }
305
306 BUG_ON(size != 0);
307 return i + 1;
308 }
309
310 /**
311 * pxa_init_dma_channel - init dma descriptors
312 * @pcdev: pxa camera device
313 * @buf: pxa buffer to find pxa dma channel
314 * @dma: dma video buffer
315 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
316 * @cibr: camera Receive Buffer Register
317 * @size: bytes to transfer
318 * @sg_first: first element of sg_list
319 * @sg_first_ofs: offset in first element of sg_list
320 *
321 * Prepares the pxa dma descriptors to transfer one camera channel.
322 * Beware sg_first and sg_first_ofs are both input and output parameters.
323 *
324 * Returns 0 or -ENOMEM if no coherent memory is available
325 */
326 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
327 struct pxa_buffer *buf,
328 struct videobuf_dmabuf *dma, int channel,
329 int cibr, int size,
330 struct scatterlist **sg_first, int *sg_first_ofs)
331 {
332 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
333 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
334 struct scatterlist *sg;
335 int i, offset, sglen;
336 int dma_len = 0, xfer_len = 0;
337
338 if (pxa_dma->sg_cpu)
339 dma_free_coherent(dev, pxa_dma->sg_size,
340 pxa_dma->sg_cpu, pxa_dma->sg_dma);
341
342 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
343 *sg_first_ofs, size);
344
345 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
346 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
347 &pxa_dma->sg_dma, GFP_KERNEL);
348 if (!pxa_dma->sg_cpu)
349 return -ENOMEM;
350
351 pxa_dma->sglen = sglen;
352 offset = *sg_first_ofs;
353
354 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
355 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
356
357
358 for_each_sg(*sg_first, sg, sglen, i) {
359 dma_len = sg_dma_len(sg);
360
361 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
362 xfer_len = roundup(min(dma_len - offset, size), 8);
363
364 size = max(0, size - xfer_len);
365
366 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
367 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
368 pxa_dma->sg_cpu[i].dcmd =
369 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
370 #ifdef DEBUG
371 if (!i)
372 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
373 #endif
374 pxa_dma->sg_cpu[i].ddadr =
375 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
376
377 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
378 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
379 sg_dma_address(sg) + offset, xfer_len);
380 offset = 0;
381
382 if (size == 0)
383 break;
384 }
385
386 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
387 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
388
389 /*
390 * Handle 1 special case :
391 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
392 * to dma_len (end on PAGE boundary). In this case, the sg element
393 * for next plane should be the next after the last used to store the
394 * last scatter gather RAM page
395 */
396 if (xfer_len >= dma_len) {
397 *sg_first_ofs = xfer_len - dma_len;
398 *sg_first = sg_next(sg);
399 } else {
400 *sg_first_ofs = xfer_len;
401 *sg_first = sg;
402 }
403
404 return 0;
405 }
406
407 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
408 struct pxa_buffer *buf)
409 {
410 buf->active_dma = DMA_Y;
411 if (pcdev->channels == 3)
412 buf->active_dma |= DMA_U | DMA_V;
413 }
414
415 /*
416 * Please check the DMA prepared buffer structure in :
417 * Documentation/video4linux/pxa_camera.txt
418 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
419 * modification while DMA chain is running will work anyway.
420 */
421 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
422 struct videobuf_buffer *vb, enum v4l2_field field)
423 {
424 struct soc_camera_device *icd = vq->priv_data;
425 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
426 struct pxa_camera_dev *pcdev = ici->priv;
427 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
428 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
429 int ret;
430 int size_y, size_u = 0, size_v = 0;
431
432 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
433 vb, vb->baddr, vb->bsize);
434
435 /* Added list head initialization on alloc */
436 WARN_ON(!list_empty(&vb->queue));
437
438 #ifdef DEBUG
439 /* This can be useful if you want to see if we actually fill
440 * the buffer with something */
441 memset((void *)vb->baddr, 0xaa, vb->bsize);
442 #endif
443
444 BUG_ON(NULL == icd->current_fmt);
445
446 /* I think, in buf_prepare you only have to protect global data,
447 * the actual buffer is yours */
448 buf->inwork = 1;
449
450 if (buf->fmt != icd->current_fmt ||
451 vb->width != icd->user_width ||
452 vb->height != icd->user_height ||
453 vb->field != field) {
454 buf->fmt = icd->current_fmt;
455 vb->width = icd->user_width;
456 vb->height = icd->user_height;
457 vb->field = field;
458 vb->state = VIDEOBUF_NEEDS_INIT;
459 }
460
461 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
462 if (0 != vb->baddr && vb->bsize < vb->size) {
463 ret = -EINVAL;
464 goto out;
465 }
466
467 if (vb->state == VIDEOBUF_NEEDS_INIT) {
468 int size = vb->size;
469 int next_ofs = 0;
470 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
471 struct scatterlist *sg;
472
473 ret = videobuf_iolock(vq, vb, NULL);
474 if (ret)
475 goto fail;
476
477 if (pcdev->channels == 3) {
478 size_y = size / 2;
479 size_u = size_v = size / 4;
480 } else {
481 size_y = size;
482 }
483
484 sg = dma->sglist;
485
486 /* init DMA for Y channel */
487 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
488 &sg, &next_ofs);
489 if (ret) {
490 dev_err(dev, "DMA initialization for Y/RGB failed\n");
491 goto fail;
492 }
493
494 /* init DMA for U channel */
495 if (size_u)
496 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
497 size_u, &sg, &next_ofs);
498 if (ret) {
499 dev_err(dev, "DMA initialization for U failed\n");
500 goto fail_u;
501 }
502
503 /* init DMA for V channel */
504 if (size_v)
505 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
506 size_v, &sg, &next_ofs);
507 if (ret) {
508 dev_err(dev, "DMA initialization for V failed\n");
509 goto fail_v;
510 }
511
512 vb->state = VIDEOBUF_PREPARED;
513 }
514
515 buf->inwork = 0;
516 pxa_videobuf_set_actdma(pcdev, buf);
517
518 return 0;
519
520 fail_v:
521 dma_free_coherent(dev, buf->dmas[1].sg_size,
522 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
523 fail_u:
524 dma_free_coherent(dev, buf->dmas[0].sg_size,
525 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
526 fail:
527 free_buffer(vq, buf);
528 out:
529 buf->inwork = 0;
530 return ret;
531 }
532
533 /**
534 * pxa_dma_start_channels - start DMA channel for active buffer
535 * @pcdev: pxa camera device
536 *
537 * Initialize DMA channels to the beginning of the active video buffer, and
538 * start these channels.
539 */
540 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
541 {
542 int i;
543 struct pxa_buffer *active;
544
545 active = pcdev->active;
546
547 for (i = 0; i < pcdev->channels; i++) {
548 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
549 "%s (channel=%d) ddadr=%08x\n", __func__,
550 i, active->dmas[i].sg_dma);
551 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
552 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
553 }
554 }
555
556 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
557 {
558 int i;
559
560 for (i = 0; i < pcdev->channels; i++) {
561 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
562 "%s (channel=%d)\n", __func__, i);
563 DCSR(pcdev->dma_chans[i]) = 0;
564 }
565 }
566
567 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
568 struct pxa_buffer *buf)
569 {
570 int i;
571 struct pxa_dma_desc *buf_last_desc;
572
573 for (i = 0; i < pcdev->channels; i++) {
574 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
575 buf_last_desc->ddadr = DDADR_STOP;
576
577 if (pcdev->sg_tail[i])
578 /* Link the new buffer to the old tail */
579 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
580
581 /* Update the channel tail */
582 pcdev->sg_tail[i] = buf_last_desc;
583 }
584 }
585
586 /**
587 * pxa_camera_start_capture - start video capturing
588 * @pcdev: camera device
589 *
590 * Launch capturing. DMA channels should not be active yet. They should get
591 * activated at the end of frame interrupt, to capture only whole frames, and
592 * never begin the capture of a partial frame.
593 */
594 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
595 {
596 unsigned long cicr0, cifr;
597
598 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
599 /* Reset the FIFOs */
600 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
601 __raw_writel(cifr, pcdev->base + CIFR);
602 /* Enable End-Of-Frame Interrupt */
603 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
604 cicr0 &= ~CICR0_EOFM;
605 __raw_writel(cicr0, pcdev->base + CICR0);
606 }
607
608 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
609 {
610 unsigned long cicr0;
611
612 pxa_dma_stop_channels(pcdev);
613
614 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
615 __raw_writel(cicr0, pcdev->base + CICR0);
616
617 pcdev->active = NULL;
618 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
619 }
620
621 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
622 static void pxa_videobuf_queue(struct videobuf_queue *vq,
623 struct videobuf_buffer *vb)
624 {
625 struct soc_camera_device *icd = vq->priv_data;
626 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
627 struct pxa_camera_dev *pcdev = ici->priv;
628 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
629
630 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
631 __func__, vb, vb->baddr, vb->bsize, pcdev->active);
632
633 list_add_tail(&vb->queue, &pcdev->capture);
634
635 vb->state = VIDEOBUF_ACTIVE;
636 pxa_dma_add_tail_buf(pcdev, buf);
637
638 if (!pcdev->active)
639 pxa_camera_start_capture(pcdev);
640 }
641
642 static void pxa_videobuf_release(struct videobuf_queue *vq,
643 struct videobuf_buffer *vb)
644 {
645 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
646 #ifdef DEBUG
647 struct soc_camera_device *icd = vq->priv_data;
648 struct device *dev = icd->dev.parent;
649
650 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
651 vb, vb->baddr, vb->bsize);
652
653 switch (vb->state) {
654 case VIDEOBUF_ACTIVE:
655 dev_dbg(dev, "%s (active)\n", __func__);
656 break;
657 case VIDEOBUF_QUEUED:
658 dev_dbg(dev, "%s (queued)\n", __func__);
659 break;
660 case VIDEOBUF_PREPARED:
661 dev_dbg(dev, "%s (prepared)\n", __func__);
662 break;
663 default:
664 dev_dbg(dev, "%s (unknown)\n", __func__);
665 break;
666 }
667 #endif
668
669 free_buffer(vq, buf);
670 }
671
672 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
673 struct videobuf_buffer *vb,
674 struct pxa_buffer *buf)
675 {
676 int i;
677
678 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
679 list_del_init(&vb->queue);
680 vb->state = VIDEOBUF_DONE;
681 do_gettimeofday(&vb->ts);
682 vb->field_count++;
683 wake_up(&vb->done);
684 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
685 __func__, vb);
686
687 if (list_empty(&pcdev->capture)) {
688 pxa_camera_stop_capture(pcdev);
689 for (i = 0; i < pcdev->channels; i++)
690 pcdev->sg_tail[i] = NULL;
691 return;
692 }
693
694 pcdev->active = list_entry(pcdev->capture.next,
695 struct pxa_buffer, vb.queue);
696 }
697
698 /**
699 * pxa_camera_check_link_miss - check missed DMA linking
700 * @pcdev: camera device
701 *
702 * The DMA chaining is done with DMA running. This means a tiny temporal window
703 * remains, where a buffer is queued on the chain, while the chain is already
704 * stopped. This means the tailed buffer would never be transfered by DMA.
705 * This function restarts the capture for this corner case, where :
706 * - DADR() == DADDR_STOP
707 * - a videobuffer is queued on the pcdev->capture list
708 *
709 * Please check the "DMA hot chaining timeslice issue" in
710 * Documentation/video4linux/pxa_camera.txt
711 *
712 * Context: should only be called within the dma irq handler
713 */
714 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
715 {
716 int i, is_dma_stopped = 1;
717
718 for (i = 0; i < pcdev->channels; i++)
719 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
720 is_dma_stopped = 0;
721 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
722 "%s : top queued buffer=%p, dma_stopped=%d\n",
723 __func__, pcdev->active, is_dma_stopped);
724 if (pcdev->active && is_dma_stopped)
725 pxa_camera_start_capture(pcdev);
726 }
727
728 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
729 enum pxa_camera_active_dma act_dma)
730 {
731 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
732 struct pxa_buffer *buf;
733 unsigned long flags;
734 u32 status, camera_status, overrun;
735 struct videobuf_buffer *vb;
736
737 spin_lock_irqsave(&pcdev->lock, flags);
738
739 status = DCSR(channel);
740 DCSR(channel) = status;
741
742 camera_status = __raw_readl(pcdev->base + CISR);
743 overrun = CISR_IFO_0;
744 if (pcdev->channels == 3)
745 overrun |= CISR_IFO_1 | CISR_IFO_2;
746
747 if (status & DCSR_BUSERR) {
748 dev_err(dev, "DMA Bus Error IRQ!\n");
749 goto out;
750 }
751
752 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
753 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
754 status);
755 goto out;
756 }
757
758 /*
759 * pcdev->active should not be NULL in DMA irq handler.
760 *
761 * But there is one corner case : if capture was stopped due to an
762 * overrun of channel 1, and at that same channel 2 was completed.
763 *
764 * When handling the overrun in DMA irq for channel 1, we'll stop the
765 * capture and restart it (and thus set pcdev->active to NULL). But the
766 * DMA irq handler will already be pending for channel 2. So on entering
767 * the DMA irq handler for channel 2 there will be no active buffer, yet
768 * that is normal.
769 */
770 if (!pcdev->active)
771 goto out;
772
773 vb = &pcdev->active->vb;
774 buf = container_of(vb, struct pxa_buffer, vb);
775 WARN_ON(buf->inwork || list_empty(&vb->queue));
776
777 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
778 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
779 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
780
781 if (status & DCSR_ENDINTR) {
782 /*
783 * It's normal if the last frame creates an overrun, as there
784 * are no more DMA descriptors to fetch from QCI fifos
785 */
786 if (camera_status & overrun &&
787 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
788 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
789 camera_status);
790 pxa_camera_stop_capture(pcdev);
791 pxa_camera_start_capture(pcdev);
792 goto out;
793 }
794 buf->active_dma &= ~act_dma;
795 if (!buf->active_dma) {
796 pxa_camera_wakeup(pcdev, vb, buf);
797 pxa_camera_check_link_miss(pcdev);
798 }
799 }
800
801 out:
802 spin_unlock_irqrestore(&pcdev->lock, flags);
803 }
804
805 static void pxa_camera_dma_irq_y(int channel, void *data)
806 {
807 struct pxa_camera_dev *pcdev = data;
808 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
809 }
810
811 static void pxa_camera_dma_irq_u(int channel, void *data)
812 {
813 struct pxa_camera_dev *pcdev = data;
814 pxa_camera_dma_irq(channel, pcdev, DMA_U);
815 }
816
817 static void pxa_camera_dma_irq_v(int channel, void *data)
818 {
819 struct pxa_camera_dev *pcdev = data;
820 pxa_camera_dma_irq(channel, pcdev, DMA_V);
821 }
822
823 static struct videobuf_queue_ops pxa_videobuf_ops = {
824 .buf_setup = pxa_videobuf_setup,
825 .buf_prepare = pxa_videobuf_prepare,
826 .buf_queue = pxa_videobuf_queue,
827 .buf_release = pxa_videobuf_release,
828 };
829
830 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
831 struct soc_camera_device *icd)
832 {
833 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
834 struct pxa_camera_dev *pcdev = ici->priv;
835
836 /* We must pass NULL as dev pointer, then all pci_* dma operations
837 * transform to normal dma_* ones. */
838 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
839 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
840 sizeof(struct pxa_buffer), icd);
841 }
842
843 static u32 mclk_get_divisor(struct platform_device *pdev,
844 struct pxa_camera_dev *pcdev)
845 {
846 unsigned long mclk = pcdev->mclk;
847 struct device *dev = &pdev->dev;
848 u32 div;
849 unsigned long lcdclk;
850
851 lcdclk = clk_get_rate(pcdev->clk);
852 pcdev->ciclk = lcdclk;
853
854 /* mclk <= ciclk / 4 (27.4.2) */
855 if (mclk > lcdclk / 4) {
856 mclk = lcdclk / 4;
857 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
858 }
859
860 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
861 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
862
863 /* If we're not supplying MCLK, leave it at 0 */
864 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
865 pcdev->mclk = lcdclk / (2 * (div + 1));
866
867 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
868 lcdclk, mclk, div);
869
870 return div;
871 }
872
873 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
874 unsigned long pclk)
875 {
876 /* We want a timeout > 1 pixel time, not ">=" */
877 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
878
879 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
880 }
881
882 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
883 {
884 struct pxacamera_platform_data *pdata = pcdev->pdata;
885 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
886 u32 cicr4 = 0;
887
888 dev_dbg(dev, "Registered platform device at %p data %p\n",
889 pcdev, pdata);
890
891 if (pdata && pdata->init) {
892 dev_dbg(dev, "%s: Init gpios\n", __func__);
893 pdata->init(dev);
894 }
895
896 /* disable all interrupts */
897 __raw_writel(0x3ff, pcdev->base + CICR0);
898
899 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
900 cicr4 |= CICR4_PCLK_EN;
901 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
902 cicr4 |= CICR4_MCLK_EN;
903 if (pcdev->platform_flags & PXA_CAMERA_PCP)
904 cicr4 |= CICR4_PCP;
905 if (pcdev->platform_flags & PXA_CAMERA_HSP)
906 cicr4 |= CICR4_HSP;
907 if (pcdev->platform_flags & PXA_CAMERA_VSP)
908 cicr4 |= CICR4_VSP;
909
910 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
911
912 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
913 /* Initialise the timeout under the assumption pclk = mclk */
914 recalculate_fifo_timeout(pcdev, pcdev->mclk);
915 else
916 /* "Safe default" - 13MHz */
917 recalculate_fifo_timeout(pcdev, 13000000);
918
919 clk_enable(pcdev->clk);
920 }
921
922 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
923 {
924 clk_disable(pcdev->clk);
925 }
926
927 static irqreturn_t pxa_camera_irq(int irq, void *data)
928 {
929 struct pxa_camera_dev *pcdev = data;
930 unsigned long status, cicr0;
931 struct pxa_buffer *buf;
932 struct videobuf_buffer *vb;
933
934 status = __raw_readl(pcdev->base + CISR);
935 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
936 "Camera interrupt status 0x%lx\n", status);
937
938 if (!status)
939 return IRQ_NONE;
940
941 __raw_writel(status, pcdev->base + CISR);
942
943 if (status & CISR_EOF) {
944 pcdev->active = list_first_entry(&pcdev->capture,
945 struct pxa_buffer, vb.queue);
946 vb = &pcdev->active->vb;
947 buf = container_of(vb, struct pxa_buffer, vb);
948 pxa_videobuf_set_actdma(pcdev, buf);
949
950 pxa_dma_start_channels(pcdev);
951
952 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
953 __raw_writel(cicr0, pcdev->base + CICR0);
954 }
955
956 return IRQ_HANDLED;
957 }
958
959 /*
960 * The following two functions absolutely depend on the fact, that
961 * there can be only one camera on PXA quick capture interface
962 * Called with .video_lock held
963 */
964 static int pxa_camera_add_device(struct soc_camera_device *icd)
965 {
966 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
967 struct pxa_camera_dev *pcdev = ici->priv;
968
969 if (pcdev->icd)
970 return -EBUSY;
971
972 pxa_camera_activate(pcdev);
973
974 pcdev->icd = icd;
975
976 dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n",
977 icd->devnum);
978
979 return 0;
980 }
981
982 /* Called with .video_lock held */
983 static void pxa_camera_remove_device(struct soc_camera_device *icd)
984 {
985 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
986 struct pxa_camera_dev *pcdev = ici->priv;
987
988 BUG_ON(icd != pcdev->icd);
989
990 dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n",
991 icd->devnum);
992
993 /* disable capture, disable interrupts */
994 __raw_writel(0x3ff, pcdev->base + CICR0);
995
996 /* Stop DMA engine */
997 DCSR(pcdev->dma_chans[0]) = 0;
998 DCSR(pcdev->dma_chans[1]) = 0;
999 DCSR(pcdev->dma_chans[2]) = 0;
1000
1001 pxa_camera_deactivate(pcdev);
1002
1003 pcdev->icd = NULL;
1004 }
1005
1006 static int test_platform_param(struct pxa_camera_dev *pcdev,
1007 unsigned char buswidth, unsigned long *flags)
1008 {
1009 /*
1010 * Platform specified synchronization and pixel clock polarities are
1011 * only a recommendation and are only used during probing. The PXA270
1012 * quick capture interface supports both.
1013 */
1014 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1015 SOCAM_MASTER : SOCAM_SLAVE) |
1016 SOCAM_HSYNC_ACTIVE_HIGH |
1017 SOCAM_HSYNC_ACTIVE_LOW |
1018 SOCAM_VSYNC_ACTIVE_HIGH |
1019 SOCAM_VSYNC_ACTIVE_LOW |
1020 SOCAM_DATA_ACTIVE_HIGH |
1021 SOCAM_PCLK_SAMPLE_RISING |
1022 SOCAM_PCLK_SAMPLE_FALLING;
1023
1024 /* If requested data width is supported by the platform, use it */
1025 switch (buswidth) {
1026 case 10:
1027 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1028 return -EINVAL;
1029 *flags |= SOCAM_DATAWIDTH_10;
1030 break;
1031 case 9:
1032 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1033 return -EINVAL;
1034 *flags |= SOCAM_DATAWIDTH_9;
1035 break;
1036 case 8:
1037 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1038 return -EINVAL;
1039 *flags |= SOCAM_DATAWIDTH_8;
1040 break;
1041 default:
1042 return -EINVAL;
1043 }
1044
1045 return 0;
1046 }
1047
1048 static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
1049 unsigned long flags, __u32 pixfmt)
1050 {
1051 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1052 struct pxa_camera_dev *pcdev = ici->priv;
1053 unsigned long dw, bpp;
1054 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1055
1056 /* Datawidth is now guaranteed to be equal to one of the three values.
1057 * We fix bit-per-pixel equal to data-width... */
1058 switch (flags & SOCAM_DATAWIDTH_MASK) {
1059 case SOCAM_DATAWIDTH_10:
1060 dw = 4;
1061 bpp = 0x40;
1062 break;
1063 case SOCAM_DATAWIDTH_9:
1064 dw = 3;
1065 bpp = 0x20;
1066 break;
1067 default:
1068 /* Actually it can only be 8 now,
1069 * default is just to silence compiler warnings */
1070 case SOCAM_DATAWIDTH_8:
1071 dw = 2;
1072 bpp = 0;
1073 }
1074
1075 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1076 cicr4 |= CICR4_PCLK_EN;
1077 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1078 cicr4 |= CICR4_MCLK_EN;
1079 if (flags & SOCAM_PCLK_SAMPLE_FALLING)
1080 cicr4 |= CICR4_PCP;
1081 if (flags & SOCAM_HSYNC_ACTIVE_LOW)
1082 cicr4 |= CICR4_HSP;
1083 if (flags & SOCAM_VSYNC_ACTIVE_LOW)
1084 cicr4 |= CICR4_VSP;
1085
1086 cicr0 = __raw_readl(pcdev->base + CICR0);
1087 if (cicr0 & CICR0_ENB)
1088 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1089
1090 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1091
1092 switch (pixfmt) {
1093 case V4L2_PIX_FMT_YUV422P:
1094 pcdev->channels = 3;
1095 cicr1 |= CICR1_YCBCR_F;
1096 /*
1097 * Normally, pxa bus wants as input UYVY format. We allow all
1098 * reorderings of the YUV422 format, as no processing is done,
1099 * and the YUV stream is just passed through without any
1100 * transformation. Note that UYVY is the only format that
1101 * should be used if pxa framebuffer Overlay2 is used.
1102 */
1103 case V4L2_PIX_FMT_UYVY:
1104 case V4L2_PIX_FMT_VYUY:
1105 case V4L2_PIX_FMT_YUYV:
1106 case V4L2_PIX_FMT_YVYU:
1107 cicr1 |= CICR1_COLOR_SP_VAL(2);
1108 break;
1109 case V4L2_PIX_FMT_RGB555:
1110 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1111 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1112 break;
1113 case V4L2_PIX_FMT_RGB565:
1114 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1115 break;
1116 }
1117
1118 cicr2 = 0;
1119 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1120 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1121 cicr4 |= pcdev->mclk_divisor;
1122
1123 __raw_writel(cicr1, pcdev->base + CICR1);
1124 __raw_writel(cicr2, pcdev->base + CICR2);
1125 __raw_writel(cicr3, pcdev->base + CICR3);
1126 __raw_writel(cicr4, pcdev->base + CICR4);
1127
1128 /* CIF interrupts are not used, only DMA */
1129 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1130 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1131 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1132 __raw_writel(cicr0, pcdev->base + CICR0);
1133 }
1134
1135 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1136 {
1137 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1138 struct pxa_camera_dev *pcdev = ici->priv;
1139 unsigned long bus_flags, camera_flags, common_flags;
1140 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1141 struct pxa_cam *cam = icd->host_priv;
1142
1143 if (ret < 0)
1144 return ret;
1145
1146 camera_flags = icd->ops->query_bus_param(icd);
1147
1148 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1149 if (!common_flags)
1150 return -EINVAL;
1151
1152 pcdev->channels = 1;
1153
1154 /* Make choises, based on platform preferences */
1155 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1156 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1157 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1158 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1159 else
1160 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1161 }
1162
1163 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1164 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1165 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1166 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1167 else
1168 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1169 }
1170
1171 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1172 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1173 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1174 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1175 else
1176 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1177 }
1178
1179 cam->flags = common_flags;
1180
1181 ret = icd->ops->set_bus_param(icd, common_flags);
1182 if (ret < 0)
1183 return ret;
1184
1185 pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1186
1187 return 0;
1188 }
1189
1190 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1191 unsigned char buswidth)
1192 {
1193 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1194 struct pxa_camera_dev *pcdev = ici->priv;
1195 unsigned long bus_flags, camera_flags;
1196 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1197
1198 if (ret < 0)
1199 return ret;
1200
1201 camera_flags = icd->ops->query_bus_param(icd);
1202
1203 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1204 }
1205
1206 static const struct soc_camera_data_format pxa_camera_formats[] = {
1207 {
1208 .name = "Planar YUV422 16 bit",
1209 .depth = 16,
1210 .fourcc = V4L2_PIX_FMT_YUV422P,
1211 .colorspace = V4L2_COLORSPACE_JPEG,
1212 },
1213 };
1214
1215 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1216 {
1217 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1218 struct pxa_camera_dev *pcdev = ici->priv;
1219
1220 switch (depth) {
1221 case 8:
1222 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1223 case 9:
1224 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1225 case 10:
1226 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1227 }
1228 return false;
1229 }
1230
1231 static int required_buswidth(const struct soc_camera_data_format *fmt)
1232 {
1233 switch (fmt->fourcc) {
1234 case V4L2_PIX_FMT_UYVY:
1235 case V4L2_PIX_FMT_VYUY:
1236 case V4L2_PIX_FMT_YUYV:
1237 case V4L2_PIX_FMT_YVYU:
1238 case V4L2_PIX_FMT_RGB565:
1239 case V4L2_PIX_FMT_RGB555:
1240 return 8;
1241 default:
1242 return fmt->depth;
1243 }
1244 }
1245
1246 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1247 struct soc_camera_format_xlate *xlate)
1248 {
1249 struct device *dev = icd->dev.parent;
1250 int formats = 0, buswidth, ret;
1251 struct pxa_cam *cam;
1252
1253 buswidth = required_buswidth(icd->formats + idx);
1254
1255 if (!buswidth_supported(icd, buswidth))
1256 return 0;
1257
1258 ret = pxa_camera_try_bus_param(icd, buswidth);
1259 if (ret < 0)
1260 return 0;
1261
1262 if (!icd->host_priv) {
1263 cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1264 if (!cam)
1265 return -ENOMEM;
1266
1267 icd->host_priv = cam;
1268 } else {
1269 cam = icd->host_priv;
1270 }
1271
1272 switch (icd->formats[idx].fourcc) {
1273 case V4L2_PIX_FMT_UYVY:
1274 formats++;
1275 if (xlate) {
1276 xlate->host_fmt = &pxa_camera_formats[0];
1277 xlate->cam_fmt = icd->formats + idx;
1278 xlate->buswidth = buswidth;
1279 xlate++;
1280 dev_dbg(dev, "Providing format %s using %s\n",
1281 pxa_camera_formats[0].name,
1282 icd->formats[idx].name);
1283 }
1284 case V4L2_PIX_FMT_VYUY:
1285 case V4L2_PIX_FMT_YUYV:
1286 case V4L2_PIX_FMT_YVYU:
1287 case V4L2_PIX_FMT_RGB565:
1288 case V4L2_PIX_FMT_RGB555:
1289 formats++;
1290 if (xlate) {
1291 xlate->host_fmt = icd->formats + idx;
1292 xlate->cam_fmt = icd->formats + idx;
1293 xlate->buswidth = buswidth;
1294 xlate++;
1295 dev_dbg(dev, "Providing format %s packed\n",
1296 icd->formats[idx].name);
1297 }
1298 break;
1299 default:
1300 /* Generic pass-through */
1301 formats++;
1302 if (xlate) {
1303 xlate->host_fmt = icd->formats + idx;
1304 xlate->cam_fmt = icd->formats + idx;
1305 xlate->buswidth = icd->formats[idx].depth;
1306 xlate++;
1307 dev_dbg(dev,
1308 "Providing format %s in pass-through mode\n",
1309 icd->formats[idx].name);
1310 }
1311 }
1312
1313 return formats;
1314 }
1315
1316 static void pxa_camera_put_formats(struct soc_camera_device *icd)
1317 {
1318 kfree(icd->host_priv);
1319 icd->host_priv = NULL;
1320 }
1321
1322 static int pxa_camera_check_frame(struct v4l2_pix_format *pix)
1323 {
1324 /* limit to pxa hardware capabilities */
1325 return pix->height < 32 || pix->height > 2048 || pix->width < 48 ||
1326 pix->width > 2048 || (pix->width & 0x01);
1327 }
1328
1329 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1330 struct v4l2_crop *a)
1331 {
1332 struct v4l2_rect *rect = &a->c;
1333 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1334 struct pxa_camera_dev *pcdev = ici->priv;
1335 struct device *dev = icd->dev.parent;
1336 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1337 struct soc_camera_sense sense = {
1338 .master_clock = pcdev->mclk,
1339 .pixel_clock_max = pcdev->ciclk / 4,
1340 };
1341 struct v4l2_format f;
1342 struct v4l2_pix_format *pix = &f.fmt.pix, pix_tmp;
1343 struct pxa_cam *cam = icd->host_priv;
1344 int ret;
1345
1346 /* If PCLK is used to latch data from the sensor, check sense */
1347 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1348 icd->sense = &sense;
1349
1350 ret = v4l2_subdev_call(sd, video, s_crop, a);
1351
1352 icd->sense = NULL;
1353
1354 if (ret < 0) {
1355 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1356 rect->width, rect->height, rect->left, rect->top);
1357 return ret;
1358 }
1359
1360 f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1361
1362 ret = v4l2_subdev_call(sd, video, g_fmt, &f);
1363 if (ret < 0)
1364 return ret;
1365
1366 pix_tmp = *pix;
1367 if (pxa_camera_check_frame(pix)) {
1368 /*
1369 * Camera cropping produced a frame beyond our capabilities.
1370 * FIXME: just extract a subframe, that we can process.
1371 */
1372 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1373 &pix->height, 32, 2048, 0,
1374 icd->current_fmt->fourcc == V4L2_PIX_FMT_YUV422P ?
1375 4 : 0);
1376 ret = v4l2_subdev_call(sd, video, s_fmt, &f);
1377 if (ret < 0)
1378 return ret;
1379
1380 if (pxa_camera_check_frame(pix)) {
1381 dev_warn(icd->dev.parent,
1382 "Inconsistent state. Use S_FMT to repair\n");
1383 return -EINVAL;
1384 }
1385 }
1386
1387 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1388 if (sense.pixel_clock > sense.pixel_clock_max) {
1389 dev_err(dev,
1390 "pixel clock %lu set by the camera too high!",
1391 sense.pixel_clock);
1392 return -EIO;
1393 }
1394 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1395 }
1396
1397 icd->user_width = pix->width;
1398 icd->user_height = pix->height;
1399
1400 pxa_camera_setup_cicr(icd, cam->flags, icd->current_fmt->fourcc);
1401
1402 return ret;
1403 }
1404
1405 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1406 struct v4l2_format *f)
1407 {
1408 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1409 struct pxa_camera_dev *pcdev = ici->priv;
1410 struct device *dev = icd->dev.parent;
1411 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1412 const struct soc_camera_data_format *cam_fmt = NULL;
1413 const struct soc_camera_format_xlate *xlate = NULL;
1414 struct soc_camera_sense sense = {
1415 .master_clock = pcdev->mclk,
1416 .pixel_clock_max = pcdev->ciclk / 4,
1417 };
1418 struct v4l2_pix_format *pix = &f->fmt.pix;
1419 struct v4l2_format cam_f = *f;
1420 int ret;
1421
1422 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1423 if (!xlate) {
1424 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1425 return -EINVAL;
1426 }
1427
1428 cam_fmt = xlate->cam_fmt;
1429
1430 /* If PCLK is used to latch data from the sensor, check sense */
1431 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1432 icd->sense = &sense;
1433
1434 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1435 ret = v4l2_subdev_call(sd, video, s_fmt, f);
1436
1437 icd->sense = NULL;
1438
1439 if (ret < 0) {
1440 dev_warn(dev, "Failed to configure for format %x\n",
1441 pix->pixelformat);
1442 } else if (pxa_camera_check_frame(pix)) {
1443 dev_warn(dev,
1444 "Camera driver produced an unsupported frame %dx%d\n",
1445 pix->width, pix->height);
1446 ret = -EINVAL;
1447 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1448 if (sense.pixel_clock > sense.pixel_clock_max) {
1449 dev_err(dev,
1450 "pixel clock %lu set by the camera too high!",
1451 sense.pixel_clock);
1452 return -EIO;
1453 }
1454 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1455 }
1456
1457 if (!ret) {
1458 icd->buswidth = xlate->buswidth;
1459 icd->current_fmt = xlate->host_fmt;
1460 }
1461
1462 return ret;
1463 }
1464
1465 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1466 struct v4l2_format *f)
1467 {
1468 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1469 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1470 const struct soc_camera_format_xlate *xlate;
1471 struct v4l2_pix_format *pix = &f->fmt.pix;
1472 __u32 pixfmt = pix->pixelformat;
1473 enum v4l2_field field;
1474 int ret;
1475
1476 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1477 if (!xlate) {
1478 dev_warn(ici->v4l2_dev.dev, "Format %x not found\n", pixfmt);
1479 return -EINVAL;
1480 }
1481
1482 /*
1483 * Limit to pxa hardware capabilities. YUV422P planar format requires
1484 * images size to be a multiple of 16 bytes. If not, zeros will be
1485 * inserted between Y and U planes, and U and V planes, which violates
1486 * the YUV422P standard.
1487 */
1488 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1489 &pix->height, 32, 2048, 0,
1490 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1491
1492 pix->bytesperline = pix->width *
1493 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1494 pix->sizeimage = pix->height * pix->bytesperline;
1495
1496 /* camera has to see its format, but the user the original one */
1497 pix->pixelformat = xlate->cam_fmt->fourcc;
1498 /* limit to sensor capabilities */
1499 ret = v4l2_subdev_call(sd, video, try_fmt, f);
1500 pix->pixelformat = pixfmt;
1501
1502 field = pix->field;
1503
1504 if (field == V4L2_FIELD_ANY) {
1505 pix->field = V4L2_FIELD_NONE;
1506 } else if (field != V4L2_FIELD_NONE) {
1507 dev_err(icd->dev.parent, "Field type %d unsupported.\n", field);
1508 return -EINVAL;
1509 }
1510
1511 return ret;
1512 }
1513
1514 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1515 struct v4l2_requestbuffers *p)
1516 {
1517 int i;
1518
1519 /* This is for locking debugging only. I removed spinlocks and now I
1520 * check whether .prepare is ever called on a linked buffer, or whether
1521 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1522 * it hadn't triggered */
1523 for (i = 0; i < p->count; i++) {
1524 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1525 struct pxa_buffer, vb);
1526 buf->inwork = 0;
1527 INIT_LIST_HEAD(&buf->vb.queue);
1528 }
1529
1530 return 0;
1531 }
1532
1533 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1534 {
1535 struct soc_camera_file *icf = file->private_data;
1536 struct pxa_buffer *buf;
1537
1538 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1539 vb.stream);
1540
1541 poll_wait(file, &buf->vb.done, pt);
1542
1543 if (buf->vb.state == VIDEOBUF_DONE ||
1544 buf->vb.state == VIDEOBUF_ERROR)
1545 return POLLIN|POLLRDNORM;
1546
1547 return 0;
1548 }
1549
1550 static int pxa_camera_querycap(struct soc_camera_host *ici,
1551 struct v4l2_capability *cap)
1552 {
1553 /* cap->name is set by the firendly caller:-> */
1554 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1555 cap->version = PXA_CAM_VERSION_CODE;
1556 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1557
1558 return 0;
1559 }
1560
1561 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1562 {
1563 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1564 struct pxa_camera_dev *pcdev = ici->priv;
1565 int i = 0, ret = 0;
1566
1567 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1568 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1569 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1570 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1571 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1572
1573 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1574 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1575
1576 return ret;
1577 }
1578
1579 static int pxa_camera_resume(struct soc_camera_device *icd)
1580 {
1581 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1582 struct pxa_camera_dev *pcdev = ici->priv;
1583 int i = 0, ret = 0;
1584
1585 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1586 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1587 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1588
1589 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1590 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1591 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1592 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1593 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1594
1595 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1596 ret = pcdev->icd->ops->resume(pcdev->icd);
1597
1598 /* Restart frame capture if active buffer exists */
1599 if (!ret && pcdev->active)
1600 pxa_camera_start_capture(pcdev);
1601
1602 return ret;
1603 }
1604
1605 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1606 .owner = THIS_MODULE,
1607 .add = pxa_camera_add_device,
1608 .remove = pxa_camera_remove_device,
1609 .suspend = pxa_camera_suspend,
1610 .resume = pxa_camera_resume,
1611 .set_crop = pxa_camera_set_crop,
1612 .get_formats = pxa_camera_get_formats,
1613 .put_formats = pxa_camera_put_formats,
1614 .set_fmt = pxa_camera_set_fmt,
1615 .try_fmt = pxa_camera_try_fmt,
1616 .init_videobuf = pxa_camera_init_videobuf,
1617 .reqbufs = pxa_camera_reqbufs,
1618 .poll = pxa_camera_poll,
1619 .querycap = pxa_camera_querycap,
1620 .set_bus_param = pxa_camera_set_bus_param,
1621 };
1622
1623 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1624 {
1625 struct pxa_camera_dev *pcdev;
1626 struct resource *res;
1627 void __iomem *base;
1628 int irq;
1629 int err = 0;
1630
1631 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1632 irq = platform_get_irq(pdev, 0);
1633 if (!res || irq < 0) {
1634 err = -ENODEV;
1635 goto exit;
1636 }
1637
1638 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1639 if (!pcdev) {
1640 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1641 err = -ENOMEM;
1642 goto exit;
1643 }
1644
1645 pcdev->clk = clk_get(&pdev->dev, NULL);
1646 if (IS_ERR(pcdev->clk)) {
1647 err = PTR_ERR(pcdev->clk);
1648 goto exit_kfree;
1649 }
1650
1651 pcdev->res = res;
1652
1653 pcdev->pdata = pdev->dev.platform_data;
1654 pcdev->platform_flags = pcdev->pdata->flags;
1655 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1656 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1657 /* Platform hasn't set available data widths. This is bad.
1658 * Warn and use a default. */
1659 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1660 "data widths, using default 10 bit\n");
1661 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1662 }
1663 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1664 if (!pcdev->mclk) {
1665 dev_warn(&pdev->dev,
1666 "mclk == 0! Please, fix your platform data. "
1667 "Using default 20MHz\n");
1668 pcdev->mclk = 20000000;
1669 }
1670
1671 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1672
1673 INIT_LIST_HEAD(&pcdev->capture);
1674 spin_lock_init(&pcdev->lock);
1675
1676 /*
1677 * Request the regions.
1678 */
1679 if (!request_mem_region(res->start, resource_size(res),
1680 PXA_CAM_DRV_NAME)) {
1681 err = -EBUSY;
1682 goto exit_clk;
1683 }
1684
1685 base = ioremap(res->start, resource_size(res));
1686 if (!base) {
1687 err = -ENOMEM;
1688 goto exit_release;
1689 }
1690 pcdev->irq = irq;
1691 pcdev->base = base;
1692
1693 /* request dma */
1694 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1695 pxa_camera_dma_irq_y, pcdev);
1696 if (err < 0) {
1697 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1698 goto exit_iounmap;
1699 }
1700 pcdev->dma_chans[0] = err;
1701 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1702
1703 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1704 pxa_camera_dma_irq_u, pcdev);
1705 if (err < 0) {
1706 dev_err(&pdev->dev, "Can't request DMA for U\n");
1707 goto exit_free_dma_y;
1708 }
1709 pcdev->dma_chans[1] = err;
1710 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1711
1712 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1713 pxa_camera_dma_irq_v, pcdev);
1714 if (err < 0) {
1715 dev_err(&pdev->dev, "Can't request DMA for V\n");
1716 goto exit_free_dma_u;
1717 }
1718 pcdev->dma_chans[2] = err;
1719 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1720
1721 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1722 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1723 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1724
1725 /* request irq */
1726 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1727 pcdev);
1728 if (err) {
1729 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1730 goto exit_free_dma;
1731 }
1732
1733 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1734 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1735 pcdev->soc_host.priv = pcdev;
1736 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1737 pcdev->soc_host.nr = pdev->id;
1738
1739 err = soc_camera_host_register(&pcdev->soc_host);
1740 if (err)
1741 goto exit_free_irq;
1742
1743 return 0;
1744
1745 exit_free_irq:
1746 free_irq(pcdev->irq, pcdev);
1747 exit_free_dma:
1748 pxa_free_dma(pcdev->dma_chans[2]);
1749 exit_free_dma_u:
1750 pxa_free_dma(pcdev->dma_chans[1]);
1751 exit_free_dma_y:
1752 pxa_free_dma(pcdev->dma_chans[0]);
1753 exit_iounmap:
1754 iounmap(base);
1755 exit_release:
1756 release_mem_region(res->start, resource_size(res));
1757 exit_clk:
1758 clk_put(pcdev->clk);
1759 exit_kfree:
1760 kfree(pcdev);
1761 exit:
1762 return err;
1763 }
1764
1765 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1766 {
1767 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1768 struct pxa_camera_dev *pcdev = container_of(soc_host,
1769 struct pxa_camera_dev, soc_host);
1770 struct resource *res;
1771
1772 clk_put(pcdev->clk);
1773
1774 pxa_free_dma(pcdev->dma_chans[0]);
1775 pxa_free_dma(pcdev->dma_chans[1]);
1776 pxa_free_dma(pcdev->dma_chans[2]);
1777 free_irq(pcdev->irq, pcdev);
1778
1779 soc_camera_host_unregister(soc_host);
1780
1781 iounmap(pcdev->base);
1782
1783 res = pcdev->res;
1784 release_mem_region(res->start, resource_size(res));
1785
1786 kfree(pcdev);
1787
1788 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1789
1790 return 0;
1791 }
1792
1793 static struct platform_driver pxa_camera_driver = {
1794 .driver = {
1795 .name = PXA_CAM_DRV_NAME,
1796 },
1797 .probe = pxa_camera_probe,
1798 .remove = __devexit_p(pxa_camera_remove),
1799 };
1800
1801
1802 static int __init pxa_camera_init(void)
1803 {
1804 return platform_driver_register(&pxa_camera_driver);
1805 }
1806
1807 static void __exit pxa_camera_exit(void)
1808 {
1809 platform_driver_unregister(&pxa_camera_driver);
1810 }
1811
1812 module_init(pxa_camera_init);
1813 module_exit(pxa_camera_exit);
1814
1815 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1816 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1817 MODULE_LICENSE("GPL");
1818 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Verdex Pro support