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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / message / fusion / lsi / mpi_cnfg.h
blob013c7d88194845e170077ea3cc4f2607f3363a4b
1 /*
2 * Copyright (c) 2000-2008 LSI Corporation.
3 *
4 *
5 * Name: mpi_cnfg.h
6 * Title: MPI Config message, structures, and Pages
7 * Creation Date: July 27, 2000
8 *
9 * mpi_cnfg.h Version: 01.05.18
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
17 * 06-06-00 01.00.01 Update version number for 1.0 release.
18 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
19 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
20 * fields to FC_DEVICE_0 page, updated the page version.
21 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
22 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
23 * and updated the page versions.
24 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
25 * page and updated the page version.
26 * Added Information field and _INFO_PARAMS_NEGOTIATED
27 * definitionto SCSI_DEVICE_0 page.
28 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
29 * page version.
30 * Added BucketsRemaining to LAN_1 page, redefined the
31 * state values, and updated the page version.
32 * Revised bus width definitions in SCSI_PORT_0,
33 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
34 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
35 * version.
36 * Moved FC_DEVICE_0 PageAddress description to spec.
37 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
38 * widths in IOC_0 page and updated the page version.
39 * 11-02-00 01.01.01 Original release for post 1.0 work
40 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI
41 * Port Page 2, FC Port Page 4, FC Port Page 5
42 * 11-15-00 01.01.02 Interim changes to match proposals
43 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
44 * 12-05-00 01.01.04 Modified config page actions.
45 * 01-09-01 01.01.05 Added defines for page address formats.
46 * Data size for Manufacturing pages 2 and 3 no longer
47 * defined here.
48 * Io Unit Page 2 size is fixed at 4 adapters and some
49 * flags were changed.
50 * SCSI Port Page 2 Device Settings modified.
51 * New fields added to FC Port Page 0 and some flags
52 * cleaned up.
53 * Removed impedance flash from FC Port Page 1.
54 * Added FC Port pages 6 and 7.
55 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
56 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
57 * Added some LinkType defines for FcPortPage0.
58 * 02-20-01 01.01.08 Started using MPI_POINTER.
59 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
60 * MPI_CONFIG_PAGETYPE_RAID_VOLUME.
61 * Added definitions and structures for IOC Page 2 and
62 * RAID Volume Page 2.
63 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
64 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
65 * Added VendorId and ProductRevLevel fields to
66 * RAIDVOL2_IM_PHYS_ID struct.
67 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
68 * defines to make them compatible to MPI version 1.0.
69 * Added structure offset comments.
70 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and
71 * removed some obsolete ones.
72 * Added IO Unit Page 3.
73 * Modified defines for Scsi Port Page 2.
74 * Modified RAID Volume Pages.
75 * 08-08-01 01.02.01 Original release for v1.2 work.
76 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
77 * Added defines for the SEP bits in RVP2 VolumeSettings.
78 * Modified the DeviceSettings field in RVP2 to use the
79 * proper structure.
80 * Added defines for SES, SAF-TE, and cross channel for
81 * IOCPage2 CapabilitiesFlags.
82 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
83 * Removed define for
84 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
85 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
86 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
87 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
88 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
89 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
90 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
91 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
92 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
93 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
94 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
95 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
96 * Added rejected bits to SCSI Device Page 0 Information.
97 * Increased size of ALPA array in FC Port Page 2 by one
98 * and removed a one byte reserved field.
99 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
100 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
101 * Added structures for Manufacturing Page 4, IO Unit
102 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
103 * RAID PhysDisk Page 0.
104 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
105 * Modified some of the new defines to make them 32
106 * character unique.
107 * Modified how variable length pages (arrays) are defined.
108 * Added generic defines for hot spare pools and RAID
109 * volume types.
110 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
111 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
112 * related define, and bumped the page version define.
113 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
114 * reserved byte and added a define.
115 * Added define for
116 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
117 * Added new config page: CONFIG_PAGE_IOC_5.
118 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
119 * fields to CONFIG_PAGE_FC_PORT_0.
120 * Added AltConnector and NumRequestedAliases fields to
121 * CONFIG_PAGE_FC_PORT_1.
122 * Added new config page: CONFIG_PAGE_FC_PORT_10.
123 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
124 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
125 * Added more MPI_SCSIDEVPAGE1_RP_ defines.
126 * Added define for
127 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
128 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
129 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
130 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
131 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
132 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
133 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
134 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
135 * CONFIG_PAGE_FC_PORT_1.
136 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
137 * an alias.
138 * Added more device id defines.
139 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
140 * Added TargetConfig and IDConfig fields to
141 * CONFIG_PAGE_SCSI_PORT_1.
142 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
143 * to control DV.
144 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
145 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
146 * with ADISCHardALPA.
147 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
148 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
149 * fields and related defines to CONFIG_PAGE_FC_PORT_1.
150 * Added define for
151 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
152 * Added new fields to the substructures of
153 * CONFIG_PAGE_FC_PORT_10.
154 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
155 * CONFIG_PAGE_SCSI_DEVICE_0, and
156 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
157 * these pages.
158 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.
159 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config
160 * pages.
161 * Added a new structure for extended config page header.
162 * Added new extended config pages types and structures for
163 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
164 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
165 * to add a Flags field.
166 * Two new Manufacturing config pages (5 and 6).
167 * Two new bits defined for IO Unit Page 1 Flags field.
168 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
169 * to specify the BIOS boot device.
170 * Four new Flags bits defined for IO Unit Page 2.
171 * Added IO Unit Page 4.
172 * Added EEDP Flags settings to IOC Page 1.
173 * Added new BIOS Page 1 config page.
174 * 10-05-04 01.05.02 Added define for
175 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
176 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
177 * associated defines.
178 * Added more defines for SAS IO Unit Page 0
179 * DiscoveryStatus field.
180 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
181 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
182 * Added defines for Physical Mapping Modes to SAS IO Unit
183 * Page 2.
184 * Added define for
185 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
186 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
187 * Added defines for MaxTargetSpinUp to BIOS Page 1.
188 * Added 5 new ControlFlags defines for SAS IO Unit
189 * Page 1.
190 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit
191 * Page 2.
192 * Added AccessStatus field to SAS Device Page 0 and added
193 * new Flags bits for supported SATA features.
194 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID
195 * Volume Page 1, and RAID Physical Disk Page 1.
196 * Replaced IO Unit Page 1 BootTargetID,BootBus, and
197 * BootAdapterNum with reserved field.
198 * Added DataScrubRate and ResyncRate to RAID Volume
199 * Page 0.
200 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
201 * define.
202 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1
203 * Flags field.
204 * Added Auto Port Config flag define for SAS IOUNIT
205 * Page 1 ControlFlags.
206 * Added Disabled bad Phy define to Expander Page 1
207 * Discovery Info field.
208 * Added SAS/SATA device support to SAS IOUnit Page 1
209 * ControlFlags.
210 * Added Unsupported device to SAS Dev Page 0 Flags field
211 * Added disable use SATA Hash Address for SAS IOUNIT
212 * page 1 in ControlFields.
213 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to
214 * Manufacturing Page 4.
215 * Added new defines for BIOS Page 1 IOCSettings field.
216 * Added ExtDiskIdentifier field to RAID Physical Disk
217 * Page 0.
218 * Added new defines for SAS IO Unit Page 1 ControlFlags
219 * and to SAS Device Page 0 Flags to control SATA devices.
220 * Added defines and structures for the new Log Page 0, a
221 * new type of configuration page.
222 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.
223 * Added WWID field to RAID Volume Page 1.
224 * Added PhysicalPort field to SAS Expander pages 0 and 1.
225 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.
226 * Added Enclosure/Slot boot device format to BIOS Page 2.
227 * New status value for RAID Volume Page 0 VolumeStatus
228 * (VolumeState subfield).
229 * New value for RAID Physical Page 0 InactiveStatus.
230 * Added Inactive Volume Member flag RAID Physical Disk
231 * Page 0 PhysDiskStatus field.
232 * New physical mapping mode in SAS IO Unit Page 2.
233 * Added CONFIG_PAGE_SAS_ENCLOSURE_0.
234 * Added Slot and Enclosure fields to SAS Device Page 0.
235 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.
236 * Added more RAID type defines to IOC Page 2.
237 * Added Port Enable Delay settings to BIOS Page 1.
238 * Added Bad Block Table Full define to RAID Volume Page 0.
239 * Added Previous State defines to RAID Physical Disk
240 * Page 0.
241 * Added Max Sata Targets define for DiscoveryStatus field
242 * of SAS IO Unit Page 0.
243 * Added Device Self Test to Control Flags of SAS IO Unit
244 * Page 1.
245 * Added Direct Attach Starting Slot Number define for SAS
246 * IO Unit Page 2.
247 * Added new fields in SAS Device Page 2 for enclosure
248 * mapping.
249 * Added OwnerDevHandle and Flags field to SAS PHY Page 0.
250 * Added IOC GPIO Flags define to SAS Enclosure Page 0.
251 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
252 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from
253 * Manufacturing Page 4.
254 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit.
255 * Added NumDevsPerEnclosure field to SAS IO Unit page 2.
256 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP
257 * define.
258 * Added EnclosureHandle field to SAS Expander page 0.
259 * Removed redundant NumTableEntriesProg field from SAS
260 * Expander Page 1.
261 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for
262 * SAS1078.
263 * Added more defines for Manufacturing Page 4 Flags field.
264 * Added more defines for IOCSettings and added
265 * ExpanderSpinup field to Bios Page 1.
266 * Added postpone SATA Init bit to SAS IO Unit Page 1
267 * ControlFlags.
268 * Changed LogEntry format for Log Page 0.
269 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4.
270 * Added Manufacturing Page 7.
271 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING.
272 * Added IOC Page 6.
273 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2.
274 * Added MaxLBAHigh field to RAID Volume Page 0.
275 * Added Nvdata version fields to SAS IO Unit Page 0.
276 * Added AdditionalControlFlags, MaxTargetPortConnectTime,
277 * ReportDeviceMissingDelay, and IODeviceMissingDelay
278 * fields to SAS IO Unit Page 1.
279 * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to
280 * Manufacturing Page 5.
281 * Added Manufacturing pages 8 through 10.
282 * Added defines for supported metadata size bits in
283 * CapabilitiesFlags field of IOC Page 6.
284 * Added defines for metadata size bits in VolumeSettings
285 * field of RAID Volume Page 0.
286 * Added SATA Link Reset settings, Enable SATA Asynchronous
287 * Notification bit, and HideNonZeroAttachedPhyIdentifiers
288 * bit to AdditionalControlFlags field of SAS IO Unit
289 * Page 1.
290 * Added defines for Enclosure Devices Unmapped and
291 * Device Limit Exceeded bits in Status field of SAS IO
292 * Unit Page 2.
293 * Added more AccessStatus values for SAS Device Page 0.
294 * Added bit for SATA Asynchronous Notification Support in
295 * Flags field of SAS Device Page 0.
296 * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4.
297 * Added Disable SMART Polling for CapabilitiesFlags of
298 * IOC Page 6.
299 * Added Disable SMART Polling to DeviceSettings of BIOS
300 * Page 1.
301 * Added Multi-Port Domain bit for DiscoveryStatus field
302 * of SAS IO Unit Page.
303 * Added Multi-Port Domain Illegal flag for SAS IO Unit
304 * Page 1 AdditionalControlFlags field.
305 * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID
306 * Metadata bit to Manufacturing Page 4 ExtFlags field.
307 * Added Internal Connector to End Device Present bit to
308 * Expander Page 0 Flags field.
309 * Fixed define for
310 * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED.
311 * 08-07-07 01.05.16 Added MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT
312 * define.
313 * Added BIOS Page 4 structure.
314 * Added MPI_RAID_PHYS_DISK1_PATH_MAX define for RAID
315 * Physcial Disk Page 1.
316 * 01-15-07 01.05.17 Added additional bit defines for ExtFlags field of
317 * Manufacturing Page 4.
318 * Added Solid State Drives Supported bit to IOC Page 6
319 * Capabilities Flags.
320 * Added new value for AccessStatus field of SAS Device
321 * Page 0 (_SATA_NEEDS_INITIALIZATION).
322 * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field
323 * to control coercion size and the mixing of SAS and SATA
324 * SSD drives.
325 * --------------------------------------------------------------------------
326 */
327
328 #ifndef MPI_CNFG_H
329 #define MPI_CNFG_H
330
331
332 /*****************************************************************************
333 *
334 * C o n f i g M e s s a g e a n d S t r u c t u r e s
335 *
336 *****************************************************************************/
337
338 typedef struct _CONFIG_PAGE_HEADER
339 {
340 U8 PageVersion; /* 00h */
341 U8 PageLength; /* 01h */
342 U8 PageNumber; /* 02h */
343 U8 PageType; /* 03h */
344 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
345 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
346
347 typedef union _CONFIG_PAGE_HEADER_UNION
348 {
349 ConfigPageHeader_t Struct;
350 U8 Bytes[4];
351 U16 Word16[2];
352 U32 Word32;
353 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
354 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
355
356 typedef struct _CONFIG_EXTENDED_PAGE_HEADER
357 {
358 U8 PageVersion; /* 00h */
359 U8 Reserved1; /* 01h */
360 U8 PageNumber; /* 02h */
361 U8 PageType; /* 03h */
362 U16 ExtPageLength; /* 04h */
363 U8 ExtPageType; /* 06h */
364 U8 Reserved2; /* 07h */
365 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
366 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
367
368
369
370 /****************************************************************************
371 * PageType field values
372 ****************************************************************************/
373 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
374 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
375 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
376 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
377 #define MPI_CONFIG_PAGEATTR_MASK (0xF0)
378
379 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
380 #define MPI_CONFIG_PAGETYPE_IOC (0x01)
381 #define MPI_CONFIG_PAGETYPE_BIOS (0x02)
382 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
383 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
384 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
385 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
386 #define MPI_CONFIG_PAGETYPE_LAN (0x07)
387 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
388 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
389 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
390 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
391 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
392 #define MPI_CONFIG_PAGETYPE_MASK (0x0F)
393
394 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
395
396
397 /****************************************************************************
398 * ExtPageType field values
399 ****************************************************************************/
400 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
401 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
402 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
403 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
404 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)
405 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
406
407
408 /****************************************************************************
409 * PageAddress field values
410 ****************************************************************************/
411 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
412
413 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)
414 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)
415 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
416 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
417 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
418 #define MPI_SCSI_DEVICE_BUS_SHIFT (8)
419 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)
420 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)
421 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)
422 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)
423 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)
424 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)
425 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)
426
427 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
428 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
429 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
430 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
431 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
432 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
433
434 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
435 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
436 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
437 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
438 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
439 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
440 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
441 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
442 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
443 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
444 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
445 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
446 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
447
448 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
449 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
450
451 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
452 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)
453 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
454 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)
455 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)
456 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)
457 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)
458 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)
459 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)
460 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)
461 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)
462 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)
463 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)
464
465 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
466 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
467 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
468 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
469 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
470 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
471 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
472 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
473 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
474 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
475 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
476 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
477 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
478
479 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
480 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)
481 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)
482 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)
483 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
484 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)
485 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
486 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)
487
488 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
489 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)
490 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
491 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)
492 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
493 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)
494 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)
495 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)
496
497
498
499 /****************************************************************************
500 * Config Request Message
501 ****************************************************************************/
502 typedef struct _MSG_CONFIG
503 {
504 U8 Action; /* 00h */
505 U8 Reserved; /* 01h */
506 U8 ChainOffset; /* 02h */
507 U8 Function; /* 03h */
508 U16 ExtPageLength; /* 04h */
509 U8 ExtPageType; /* 06h */
510 U8 MsgFlags; /* 07h */
511 U32 MsgContext; /* 08h */
512 U8 Reserved2[8]; /* 0Ch */
513 CONFIG_PAGE_HEADER Header; /* 14h */
514 U32 PageAddress; /* 18h */
515 SGE_IO_UNION PageBufferSGE; /* 1Ch */
516 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
517 Config_t, MPI_POINTER pConfig_t;
518
519
520 /****************************************************************************
521 * Action field values
522 ****************************************************************************/
523 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
524 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
525 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
526 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
527 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
528 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
529 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
530
531
532 /* Config Reply Message */
533 typedef struct _MSG_CONFIG_REPLY
534 {
535 U8 Action; /* 00h */
536 U8 Reserved; /* 01h */
537 U8 MsgLength; /* 02h */
538 U8 Function; /* 03h */
539 U16 ExtPageLength; /* 04h */
540 U8 ExtPageType; /* 06h */
541 U8 MsgFlags; /* 07h */
542 U32 MsgContext; /* 08h */
543 U8 Reserved2[2]; /* 0Ch */
544 U16 IOCStatus; /* 0Eh */
545 U32 IOCLogInfo; /* 10h */
546 CONFIG_PAGE_HEADER Header; /* 14h */
547 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
548 ConfigReply_t, MPI_POINTER pConfigReply_t;
549
550
551
552 /*****************************************************************************
553 *
554 * C o n f i g u r a t i o n P a g e s
555 *
556 *****************************************************************************/
557
558 /****************************************************************************
559 * Manufacturing Config pages
560 ****************************************************************************/
561 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
562 /* Fibre Channel */
563 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
564 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
565 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
566 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
567 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
568 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)
569 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)
570 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646)
571 /* SCSI */
572 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
573 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
574 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
575 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
576 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
577 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
578 /* SAS */
579 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
580 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)
581 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)
582 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)
583 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)
584 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)
585 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)
586 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062)
587
588
589 typedef struct _CONFIG_PAGE_MANUFACTURING_0
590 {
591 CONFIG_PAGE_HEADER Header; /* 00h */
592 U8 ChipName[16]; /* 04h */
593 U8 ChipRevision[8]; /* 14h */
594 U8 BoardName[16]; /* 1Ch */
595 U8 BoardAssembly[16]; /* 2Ch */
596 U8 BoardTracerNumber[16]; /* 3Ch */
597
598 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
599 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
600
601 #define MPI_MANUFACTURING0_PAGEVERSION (0x00)
602
603
604 typedef struct _CONFIG_PAGE_MANUFACTURING_1
605 {
606 CONFIG_PAGE_HEADER Header; /* 00h */
607 U8 VPD[256]; /* 04h */
608 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
609 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
610
611 #define MPI_MANUFACTURING1_PAGEVERSION (0x00)
612
613
614 typedef struct _MPI_CHIP_REVISION_ID
615 {
616 U16 DeviceID; /* 00h */
617 U8 PCIRevisionID; /* 02h */
618 U8 Reserved; /* 03h */
619 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
620 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
621
622
623 /*
624 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
625 * one and check Header.PageLength at runtime.
626 */
627 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
628 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
629 #endif
630
631 typedef struct _CONFIG_PAGE_MANUFACTURING_2
632 {
633 CONFIG_PAGE_HEADER Header; /* 00h */
634 MPI_CHIP_REVISION_ID ChipId; /* 04h */
635 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
636 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
637 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
638
639 #define MPI_MANUFACTURING2_PAGEVERSION (0x00)
640
641
642 /*
643 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
644 * one and check Header.PageLength at runtime.
645 */
646 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
647 #define MPI_MAN_PAGE_3_INFO_WORDS (1)
648 #endif
649
650 typedef struct _CONFIG_PAGE_MANUFACTURING_3
651 {
652 CONFIG_PAGE_HEADER Header; /* 00h */
653 MPI_CHIP_REVISION_ID ChipId; /* 04h */
654 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
655 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
656 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
657
658 #define MPI_MANUFACTURING3_PAGEVERSION (0x00)
659
660
661 typedef struct _CONFIG_PAGE_MANUFACTURING_4
662 {
663 CONFIG_PAGE_HEADER Header; /* 00h */
664 U32 Reserved1; /* 04h */
665 U8 InfoOffset0; /* 08h */
666 U8 InfoSize0; /* 09h */
667 U8 InfoOffset1; /* 0Ah */
668 U8 InfoSize1; /* 0Bh */
669 U8 InquirySize; /* 0Ch */
670 U8 Flags; /* 0Dh */
671 U16 ExtFlags; /* 0Eh */
672 U8 InquiryData[56]; /* 10h */
673 U32 ISVolumeSettings; /* 48h */
674 U32 IMEVolumeSettings; /* 4Ch */
675 U32 IMVolumeSettings; /* 50h */
676 U32 Reserved3; /* 54h */
677 U32 Reserved4; /* 58h */
678 U32 Reserved5; /* 5Ch */
679 U8 IMEDataScrubRate; /* 60h */
680 U8 IMEResyncRate; /* 61h */
681 U16 Reserved6; /* 62h */
682 U8 IMDataScrubRate; /* 64h */
683 U8 IMResyncRate; /* 65h */
684 U16 Reserved7; /* 66h */
685 U32 Reserved8; /* 68h */
686 U32 Reserved9; /* 6Ch */
687 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
688 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
689
690 #define MPI_MANUFACTURING4_PAGEVERSION (0x05)
691
692 /* defines for the Flags field */
693 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80)
694 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40)
695 #define MPI_MANPAGE4_IME_DISABLE (0x20)
696 #define MPI_MANPAGE4_IM_DISABLE (0x10)
697 #define MPI_MANPAGE4_IS_DISABLE (0x08)
698 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04)
699 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02)
700 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
701
702 /* defines for the ExtFlags field */
703 #define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180)
704 #define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7)
705 #define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0)
706 #define MPI_MANPAGE4_EXTFLAGS_128MB_COERCION_SIZE (1)
707
708 #define MPI_MANPAGE4_EXTFLAGS_NO_MIX_SSD_SAS_SATA (0x0040)
709 #define MPI_MANPAGE4_EXTFLAGS_MIX_SSD_AND_NON_SSD (0x0020)
710 #define MPI_MANPAGE4_EXTFLAGS_DUAL_PORT_SUPPORT (0x0010)
711 #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008)
712 #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004)
713 #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002)
714 #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001)
715
716
717 #ifndef MPI_MANPAGE5_NUM_FORCEWWID
718 #define MPI_MANPAGE5_NUM_FORCEWWID (1)
719 #endif
720
721 typedef struct _CONFIG_PAGE_MANUFACTURING_5
722 {
723 CONFIG_PAGE_HEADER Header; /* 00h */
724 U64 BaseWWID; /* 04h */
725 U8 Flags; /* 0Ch */
726 U8 NumForceWWID; /* 0Dh */
727 U16 Reserved2; /* 0Eh */
728 U32 Reserved3; /* 10h */
729 U32 Reserved4; /* 14h */
730 U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */
731 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
732 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
733
734 #define MPI_MANUFACTURING5_PAGEVERSION (0x02)
735
736 /* defines for the Flags field */
737 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)
738
739
740 typedef struct _CONFIG_PAGE_MANUFACTURING_6
741 {
742 CONFIG_PAGE_HEADER Header; /* 00h */
743 U32 ProductSpecificInfo;/* 04h */
744 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
745 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
746
747 #define MPI_MANUFACTURING6_PAGEVERSION (0x00)
748
749
750 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO
751 {
752 U32 Pinout; /* 00h */
753 U8 Connector[16]; /* 04h */
754 U8 Location; /* 14h */
755 U8 Reserved1; /* 15h */
756 U16 Slot; /* 16h */
757 U32 Reserved2; /* 18h */
758 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO,
759 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t;
760
761 /* defines for the Pinout field */
762 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)
763 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)
764 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)
765 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)
766 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)
767 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)
768 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)
769 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)
770 #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002)
771 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)
772
773 /* defines for the Location field */
774 #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01)
775 #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02)
776 #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04)
777 #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08)
778 #define MPI_MANPAGE7_LOCATION_AUTO (0x10)
779 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
780 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
781
782 /*
783 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
784 * one and check NumPhys at runtime.
785 */
786 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX
787 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1)
788 #endif
789
790 typedef struct _CONFIG_PAGE_MANUFACTURING_7
791 {
792 CONFIG_PAGE_HEADER Header; /* 00h */
793 U32 Reserved1; /* 04h */
794 U32 Reserved2; /* 08h */
795 U32 Flags; /* 0Ch */
796 U8 EnclosureName[16]; /* 10h */
797 U8 NumPhys; /* 20h */
798 U8 Reserved3; /* 21h */
799 U16 Reserved4; /* 22h */
800 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */
801 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7,
802 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t;
803
804 #define MPI_MANUFACTURING7_PAGEVERSION (0x00)
805
806 /* defines for the Flags field */
807 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
808
809
810 typedef struct _CONFIG_PAGE_MANUFACTURING_8
811 {
812 CONFIG_PAGE_HEADER Header; /* 00h */
813 U32 ProductSpecificInfo;/* 04h */
814 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8,
815 ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t;
816
817 #define MPI_MANUFACTURING8_PAGEVERSION (0x00)
818
819
820 typedef struct _CONFIG_PAGE_MANUFACTURING_9
821 {
822 CONFIG_PAGE_HEADER Header; /* 00h */
823 U32 ProductSpecificInfo;/* 04h */
824 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9,
825 ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t;
826
827 #define MPI_MANUFACTURING9_PAGEVERSION (0x00)
828
829
830 typedef struct _CONFIG_PAGE_MANUFACTURING_10
831 {
832 CONFIG_PAGE_HEADER Header; /* 00h */
833 U32 ProductSpecificInfo;/* 04h */
834 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10,
835 ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t;
836
837 #define MPI_MANUFACTURING10_PAGEVERSION (0x00)
838
839
840 /****************************************************************************
841 * IO Unit Config Pages
842 ****************************************************************************/
843
844 typedef struct _CONFIG_PAGE_IO_UNIT_0
845 {
846 CONFIG_PAGE_HEADER Header; /* 00h */
847 U64 UniqueValue; /* 04h */
848 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
849 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
850
851 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
852
853
854 typedef struct _CONFIG_PAGE_IO_UNIT_1
855 {
856 CONFIG_PAGE_HEADER Header; /* 00h */
857 U32 Flags; /* 04h */
858 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
859 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
860
861 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02)
862
863 /* IO Unit Page 1 Flags defines */
864 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
865 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
866 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
867 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
868 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
869 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
870 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
871 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
872 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
873 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200)
874
875 typedef struct _MPI_ADAPTER_INFO
876 {
877 U8 PciBusNumber; /* 00h */
878 U8 PciDeviceAndFunctionNumber; /* 01h */
879 U16 AdapterFlags; /* 02h */
880 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
881 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
882
883 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
884 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
885
886 typedef struct _CONFIG_PAGE_IO_UNIT_2
887 {
888 CONFIG_PAGE_HEADER Header; /* 00h */
889 U32 Flags; /* 04h */
890 U32 BiosVersion; /* 08h */
891 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
892 U32 Reserved1; /* 1Ch */
893 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
894 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
895
896 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02)
897
898 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
899 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
900 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
901 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
902
903 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
904 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
905 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
906 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
907
908
909 /*
910 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
911 * one and check Header.PageLength at runtime.
912 */
913 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
914 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
915 #endif
916
917 typedef struct _CONFIG_PAGE_IO_UNIT_3
918 {
919 CONFIG_PAGE_HEADER Header; /* 00h */
920 U8 GPIOCount; /* 04h */
921 U8 Reserved1; /* 05h */
922 U16 Reserved2; /* 06h */
923 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
924 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
925 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
926
927 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
928
929 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
930 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
931 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
932 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
933
934
935 typedef struct _CONFIG_PAGE_IO_UNIT_4
936 {
937 CONFIG_PAGE_HEADER Header; /* 00h */
938 U32 Reserved1; /* 04h */
939 SGE_SIMPLE_UNION FWImageSGE; /* 08h */
940 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
941 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
942
943 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00)
944
945
946 /****************************************************************************
947 * IOC Config Pages
948 ****************************************************************************/
949
950 typedef struct _CONFIG_PAGE_IOC_0
951 {
952 CONFIG_PAGE_HEADER Header; /* 00h */
953 U32 TotalNVStore; /* 04h */
954 U32 FreeNVStore; /* 08h */
955 U16 VendorID; /* 0Ch */
956 U16 DeviceID; /* 0Eh */
957 U8 RevisionID; /* 10h */
958 U8 Reserved[3]; /* 11h */
959 U32 ClassCode; /* 14h */
960 U16 SubsystemVendorID; /* 18h */
961 U16 SubsystemID; /* 1Ah */
962 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
963 IOCPage0_t, MPI_POINTER pIOCPage0_t;
964
965 #define MPI_IOCPAGE0_PAGEVERSION (0x01)
966
967
968 typedef struct _CONFIG_PAGE_IOC_1
969 {
970 CONFIG_PAGE_HEADER Header; /* 00h */
971 U32 Flags; /* 04h */
972 U32 CoalescingTimeout; /* 08h */
973 U8 CoalescingDepth; /* 0Ch */
974 U8 PCISlotNum; /* 0Dh */
975 U8 Reserved[2]; /* 0Eh */
976 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
977 IOCPage1_t, MPI_POINTER pIOCPage1_t;
978
979 #define MPI_IOCPAGE1_PAGEVERSION (0x03)
980
981 /* defines for the Flags field */
982 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
983 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
984 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
985 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
986 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)
987 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
988
989 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
990
991
992 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
993 {
994 U8 VolumeID; /* 00h */
995 U8 VolumeBus; /* 01h */
996 U8 VolumeIOC; /* 02h */
997 U8 VolumePageNumber; /* 03h */
998 U8 VolumeType; /* 04h */
999 U8 Flags; /* 05h */
1000 U16 Reserved3; /* 06h */
1001 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
1002 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
1003
1004 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
1005
1006 #define MPI_RAID_VOL_TYPE_IS (0x00)
1007 #define MPI_RAID_VOL_TYPE_IME (0x01)
1008 #define MPI_RAID_VOL_TYPE_IM (0x02)
1009 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03)
1010 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04)
1011 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05)
1012 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06)
1013 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)
1014
1015 /* IOC Page 2 Volume Flags values */
1016
1017 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
1018
1019 /*
1020 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1021 * one and check Header.PageLength at runtime.
1022 */
1023 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
1024 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
1025 #endif
1026
1027 typedef struct _CONFIG_PAGE_IOC_2
1028 {
1029 CONFIG_PAGE_HEADER Header; /* 00h */
1030 U32 CapabilitiesFlags; /* 04h */
1031 U8 NumActiveVolumes; /* 08h */
1032 U8 MaxVolumes; /* 09h */
1033 U8 NumActivePhysDisks; /* 0Ah */
1034 U8 MaxPhysDisks; /* 0Bh */
1035 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
1036 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
1037 IOCPage2_t, MPI_POINTER pIOCPage2_t;
1038
1039 #define MPI_IOCPAGE2_PAGEVERSION (0x04)
1040
1041 /* IOC Page 2 Capabilities flags */
1042
1043 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
1044 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
1045 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
1046 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)
1047 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010)
1048 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020)
1049 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040)
1050 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000)
1051 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
1052 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
1053 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
1054
1055
1056 typedef struct _IOC_3_PHYS_DISK
1057 {
1058 U8 PhysDiskID; /* 00h */
1059 U8 PhysDiskBus; /* 01h */
1060 U8 PhysDiskIOC; /* 02h */
1061 U8 PhysDiskNum; /* 03h */
1062 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
1063 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
1064
1065 /*
1066 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1067 * one and check Header.PageLength at runtime.
1068 */
1069 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
1070 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
1071 #endif
1072
1073 typedef struct _CONFIG_PAGE_IOC_3
1074 {
1075 CONFIG_PAGE_HEADER Header; /* 00h */
1076 U8 NumPhysDisks; /* 04h */
1077 U8 Reserved1; /* 05h */
1078 U16 Reserved2; /* 06h */
1079 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
1080 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
1081 IOCPage3_t, MPI_POINTER pIOCPage3_t;
1082
1083 #define MPI_IOCPAGE3_PAGEVERSION (0x00)
1084
1085
1086 typedef struct _IOC_4_SEP
1087 {
1088 U8 SEPTargetID; /* 00h */
1089 U8 SEPBus; /* 01h */
1090 U16 Reserved; /* 02h */
1091 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
1092 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
1093
1094 /*
1095 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1096 * one and check Header.PageLength at runtime.
1097 */
1098 #ifndef MPI_IOC_PAGE_4_SEP_MAX
1099 #define MPI_IOC_PAGE_4_SEP_MAX (1)
1100 #endif
1101
1102 typedef struct _CONFIG_PAGE_IOC_4
1103 {
1104 CONFIG_PAGE_HEADER Header; /* 00h */
1105 U8 ActiveSEP; /* 04h */
1106 U8 MaxSEP; /* 05h */
1107 U16 Reserved1; /* 06h */
1108 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
1109 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
1110 IOCPage4_t, MPI_POINTER pIOCPage4_t;
1111
1112 #define MPI_IOCPAGE4_PAGEVERSION (0x00)
1113
1114
1115 typedef struct _IOC_5_HOT_SPARE
1116 {
1117 U8 PhysDiskNum; /* 00h */
1118 U8 Reserved; /* 01h */
1119 U8 HotSparePool; /* 02h */
1120 U8 Flags; /* 03h */
1121 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
1122 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
1123
1124 /* IOC Page 5 HotSpare Flags */
1125 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
1126
1127 /*
1128 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1129 * one and check Header.PageLength at runtime.
1130 */
1131 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
1132 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
1133 #endif
1134
1135 typedef struct _CONFIG_PAGE_IOC_5
1136 {
1137 CONFIG_PAGE_HEADER Header; /* 00h */
1138 U32 Reserved1; /* 04h */
1139 U8 NumHotSpares; /* 08h */
1140 U8 Reserved2; /* 09h */
1141 U16 Reserved3; /* 0Ah */
1142 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
1143 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
1144 IOCPage5_t, MPI_POINTER pIOCPage5_t;
1145
1146 #define MPI_IOCPAGE5_PAGEVERSION (0x00)
1147
1148 typedef struct _CONFIG_PAGE_IOC_6
1149 {
1150 CONFIG_PAGE_HEADER Header; /* 00h */
1151 U32 CapabilitiesFlags; /* 04h */
1152 U8 MaxDrivesIS; /* 08h */
1153 U8 MaxDrivesIM; /* 09h */
1154 U8 MaxDrivesIME; /* 0Ah */
1155 U8 Reserved1; /* 0Bh */
1156 U8 MinDrivesIS; /* 0Ch */
1157 U8 MinDrivesIM; /* 0Dh */
1158 U8 MinDrivesIME; /* 0Eh */
1159 U8 Reserved2; /* 0Fh */
1160 U8 MaxGlobalHotSpares; /* 10h */
1161 U8 Reserved3; /* 11h */
1162 U16 Reserved4; /* 12h */
1163 U32 Reserved5; /* 14h */
1164 U32 SupportedStripeSizeMapIS; /* 18h */
1165 U32 SupportedStripeSizeMapIME; /* 1Ch */
1166 U32 Reserved6; /* 20h */
1167 U8 MetadataSize; /* 24h */
1168 U8 Reserved7; /* 25h */
1169 U16 Reserved8; /* 26h */
1170 U16 MaxBadBlockTableEntries; /* 28h */
1171 U16 Reserved9; /* 2Ah */
1172 U16 IRNvsramUsage; /* 2Ch */
1173 U16 Reserved10; /* 2Eh */
1174 U32 IRNvsramVersion; /* 30h */
1175 U32 Reserved11; /* 34h */
1176 U32 Reserved12; /* 38h */
1177 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6,
1178 IOCPage6_t, MPI_POINTER pIOCPage6_t;
1179
1180 #define MPI_IOCPAGE6_PAGEVERSION (0x01)
1181
1182 /* IOC Page 6 Capabilities Flags */
1183
1184 #define MPI_IOCPAGE6_CAP_FLAGS_SSD_SUPPORT (0x00000020)
1185 #define MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT (0x00000010)
1186 #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008)
1187
1188 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006)
1189 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000)
1190 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002)
1191
1192 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1193
1194
1195 /****************************************************************************
1196 * BIOS Config Pages
1197 ****************************************************************************/
1198
1199 typedef struct _CONFIG_PAGE_BIOS_1
1200 {
1201 CONFIG_PAGE_HEADER Header; /* 00h */
1202 U32 BiosOptions; /* 04h */
1203 U32 IOCSettings; /* 08h */
1204 U32 Reserved1; /* 0Ch */
1205 U32 DeviceSettings; /* 10h */
1206 U16 NumberOfDevices; /* 14h */
1207 U8 ExpanderSpinup; /* 16h */
1208 U8 Reserved2; /* 17h */
1209 U16 IOTimeoutBlockDevicesNonRM; /* 18h */
1210 U16 IOTimeoutSequential; /* 1Ah */
1211 U16 IOTimeoutOther; /* 1Ch */
1212 U16 IOTimeoutBlockDevicesRM; /* 1Eh */
1213 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
1214 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
1215
1216 #define MPI_BIOSPAGE1_PAGEVERSION (0x03)
1217
1218 /* values for the BiosOptions field */
1219 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
1220 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
1221 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
1222 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1223
1224 /* values for the IOCSettings field */
1225 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000)
1226 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24)
1227
1228 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000)
1229 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20)
1230
1231 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000)
1232 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000)
1233
1234 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1235 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1236 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1237
1238 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)
1239 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)
1240
1241 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
1242 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
1243
1244 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1245 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1246 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1247 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1248
1249 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1250 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1251 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1252 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1253 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1254
1255 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1256
1257 /* values for the DeviceSettings field */
1258 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1259 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1260 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1261 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1262 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1263
1264 /* defines for the ExpanderSpinup field */
1265 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0)
1266 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4)
1267 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F)
1268
1269 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1270 {
1271 U32 Reserved1; /* 00h */
1272 U32 Reserved2; /* 04h */
1273 U32 Reserved3; /* 08h */
1274 U32 Reserved4; /* 0Ch */
1275 U32 Reserved5; /* 10h */
1276 U32 Reserved6; /* 14h */
1277 U32 Reserved7; /* 18h */
1278 U32 Reserved8; /* 1Ch */
1279 U32 Reserved9; /* 20h */
1280 U32 Reserved10; /* 24h */
1281 U32 Reserved11; /* 28h */
1282 U32 Reserved12; /* 2Ch */
1283 U32 Reserved13; /* 30h */
1284 U32 Reserved14; /* 34h */
1285 U32 Reserved15; /* 38h */
1286 U32 Reserved16; /* 3Ch */
1287 U32 Reserved17; /* 40h */
1288 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1289
1290 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1291 {
1292 U8 TargetID; /* 00h */
1293 U8 Bus; /* 01h */
1294 U8 AdapterNumber; /* 02h */
1295 U8 Reserved1; /* 03h */
1296 U32 Reserved2; /* 04h */
1297 U32 Reserved3; /* 08h */
1298 U32 Reserved4; /* 0Ch */
1299 U8 LUN[8]; /* 10h */
1300 U32 Reserved5; /* 18h */
1301 U32 Reserved6; /* 1Ch */
1302 U32 Reserved7; /* 20h */
1303 U32 Reserved8; /* 24h */
1304 U32 Reserved9; /* 28h */
1305 U32 Reserved10; /* 2Ch */
1306 U32 Reserved11; /* 30h */
1307 U32 Reserved12; /* 34h */
1308 U32 Reserved13; /* 38h */
1309 U32 Reserved14; /* 3Ch */
1310 U32 Reserved15; /* 40h */
1311 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1312
1313 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1314 {
1315 U8 TargetID; /* 00h */
1316 U8 Bus; /* 01h */
1317 U16 PCIAddress; /* 02h */
1318 U32 Reserved1; /* 04h */
1319 U32 Reserved2; /* 08h */
1320 U32 Reserved3; /* 0Ch */
1321 U8 LUN[8]; /* 10h */
1322 U32 Reserved4; /* 18h */
1323 U32 Reserved5; /* 1Ch */
1324 U32 Reserved6; /* 20h */
1325 U32 Reserved7; /* 24h */
1326 U32 Reserved8; /* 28h */
1327 U32 Reserved9; /* 2Ch */
1328 U32 Reserved10; /* 30h */
1329 U32 Reserved11; /* 34h */
1330 U32 Reserved12; /* 38h */
1331 U32 Reserved13; /* 3Ch */
1332 U32 Reserved14; /* 40h */
1333 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1334
1335 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1336 {
1337 U8 TargetID; /* 00h */
1338 U8 Bus; /* 01h */
1339 U8 PCISlotNumber; /* 02h */
1340 U8 Reserved1; /* 03h */
1341 U32 Reserved2; /* 04h */
1342 U32 Reserved3; /* 08h */
1343 U32 Reserved4; /* 0Ch */
1344 U8 LUN[8]; /* 10h */
1345 U32 Reserved5; /* 18h */
1346 U32 Reserved6; /* 1Ch */
1347 U32 Reserved7; /* 20h */
1348 U32 Reserved8; /* 24h */
1349 U32 Reserved9; /* 28h */
1350 U32 Reserved10; /* 2Ch */
1351 U32 Reserved11; /* 30h */
1352 U32 Reserved12; /* 34h */
1353 U32 Reserved13; /* 38h */
1354 U32 Reserved14; /* 3Ch */
1355 U32 Reserved15; /* 40h */
1356 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1357
1358 typedef struct _MPI_BOOT_DEVICE_FC_WWN
1359 {
1360 U64 WWPN; /* 00h */
1361 U32 Reserved1; /* 08h */
1362 U32 Reserved2; /* 0Ch */
1363 U8 LUN[8]; /* 10h */
1364 U32 Reserved3; /* 18h */
1365 U32 Reserved4; /* 1Ch */
1366 U32 Reserved5; /* 20h */
1367 U32 Reserved6; /* 24h */
1368 U32 Reserved7; /* 28h */
1369 U32 Reserved8; /* 2Ch */
1370 U32 Reserved9; /* 30h */
1371 U32 Reserved10; /* 34h */
1372 U32 Reserved11; /* 38h */
1373 U32 Reserved12; /* 3Ch */
1374 U32 Reserved13; /* 40h */
1375 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1376
1377 typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1378 {
1379 U64 SASAddress; /* 00h */
1380 U32 Reserved1; /* 08h */
1381 U32 Reserved2; /* 0Ch */
1382 U8 LUN[8]; /* 10h */
1383 U32 Reserved3; /* 18h */
1384 U32 Reserved4; /* 1Ch */
1385 U32 Reserved5; /* 20h */
1386 U32 Reserved6; /* 24h */
1387 U32 Reserved7; /* 28h */
1388 U32 Reserved8; /* 2Ch */
1389 U32 Reserved9; /* 30h */
1390 U32 Reserved10; /* 34h */
1391 U32 Reserved11; /* 38h */
1392 U32 Reserved12; /* 3Ch */
1393 U32 Reserved13; /* 40h */
1394 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1395
1396 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1397 {
1398 U64 EnclosureLogicalID; /* 00h */
1399 U32 Reserved1; /* 08h */
1400 U32 Reserved2; /* 0Ch */
1401 U8 LUN[8]; /* 10h */
1402 U16 SlotNumber; /* 18h */
1403 U16 Reserved3; /* 1Ah */
1404 U32 Reserved4; /* 1Ch */
1405 U32 Reserved5; /* 20h */
1406 U32 Reserved6; /* 24h */
1407 U32 Reserved7; /* 28h */
1408 U32 Reserved8; /* 2Ch */
1409 U32 Reserved9; /* 30h */
1410 U32 Reserved10; /* 34h */
1411 U32 Reserved11; /* 38h */
1412 U32 Reserved12; /* 3Ch */
1413 U32 Reserved13; /* 40h */
1414 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1415 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1416
1417 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1418 {
1419 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1420 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;
1421 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;
1422 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1423 MPI_BOOT_DEVICE_FC_WWN FcWwn;
1424 MPI_BOOT_DEVICE_SAS_WWN SasWwn;
1425 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1426 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1427
1428 typedef struct _CONFIG_PAGE_BIOS_2
1429 {
1430 CONFIG_PAGE_HEADER Header; /* 00h */
1431 U32 Reserved1; /* 04h */
1432 U32 Reserved2; /* 08h */
1433 U32 Reserved3; /* 0Ch */
1434 U32 Reserved4; /* 10h */
1435 U32 Reserved5; /* 14h */
1436 U32 Reserved6; /* 18h */
1437 U8 BootDeviceForm; /* 1Ch */
1438 U8 PrevBootDeviceForm; /* 1Ch */
1439 U16 Reserved8; /* 1Eh */
1440 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */
1441 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1442 BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1443
1444 #define MPI_BIOSPAGE2_PAGEVERSION (0x02)
1445
1446 #define MPI_BIOSPAGE2_FORM_MASK (0x0F)
1447 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)
1448 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)
1449 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)
1450 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)
1451 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)
1452 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)
1453 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1454
1455 typedef struct _CONFIG_PAGE_BIOS_4
1456 {
1457 CONFIG_PAGE_HEADER Header; /* 00h */
1458 U64 ReassignmentBaseWWID; /* 04h */
1459 } CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4,
1460 BIOSPage4_t, MPI_POINTER pBIOSPage4_t;
1461
1462 #define MPI_BIOSPAGE4_PAGEVERSION (0x00)
1463
1464
1465 /****************************************************************************
1466 * SCSI Port Config Pages
1467 ****************************************************************************/
1468
1469 typedef struct _CONFIG_PAGE_SCSI_PORT_0
1470 {
1471 CONFIG_PAGE_HEADER Header; /* 00h */
1472 U32 Capabilities; /* 04h */
1473 U32 PhysicalInterface; /* 08h */
1474 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1475 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1476
1477 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)
1478
1479 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
1480 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
1481 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
1482 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1483 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
1484 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
1485 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
1486 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
1487 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
1488 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
1489 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
1490 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
1491 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
1492
1493 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
1494 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
1495 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \
1496 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
1497 )
1498 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1499 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
1500 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
1501 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \
1502 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
1503 )
1504 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)
1505 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
1506 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
1507
1508 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
1509 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
1510 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
1511 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
1512 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
1513 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
1514 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
1515 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
1516
1517
1518 typedef struct _CONFIG_PAGE_SCSI_PORT_1
1519 {
1520 CONFIG_PAGE_HEADER Header; /* 00h */
1521 U32 Configuration; /* 04h */
1522 U32 OnBusTimerValue; /* 08h */
1523 U8 TargetConfig; /* 0Ch */
1524 U8 Reserved1; /* 0Dh */
1525 U16 IDConfig; /* 0Eh */
1526 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1527 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1528
1529 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
1530
1531 /* Configuration values */
1532 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
1533 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1534 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
1535
1536 /* TargetConfig values */
1537 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
1538 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
1539
1540
1541 typedef struct _MPI_DEVICE_INFO
1542 {
1543 U8 Timeout; /* 00h */
1544 U8 SyncFactor; /* 01h */
1545 U16 DeviceFlags; /* 02h */
1546 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1547 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1548
1549 typedef struct _CONFIG_PAGE_SCSI_PORT_2
1550 {
1551 CONFIG_PAGE_HEADER Header; /* 00h */
1552 U32 PortFlags; /* 04h */
1553 U32 PortSettings; /* 08h */
1554 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
1555 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
1556 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1557
1558 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)
1559
1560 /* PortFlags values */
1561 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
1562 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
1563 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1564 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
1565
1566 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
1567 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
1568 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
1569 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
1570
1571
1572 /* PortSettings values */
1573 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
1574 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
1575 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
1576 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
1577 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
1578 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
1579 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1580 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
1581 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
1582 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
1583 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1584 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
1585 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
1586 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
1587 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
1588 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
1589
1590 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
1591 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
1592 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
1593 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
1594 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
1595 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
1596
1597
1598 /****************************************************************************
1599 * SCSI Target Device Config Pages
1600 ****************************************************************************/
1601
1602 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1603 {
1604 CONFIG_PAGE_HEADER Header; /* 00h */
1605 U32 NegotiatedParameters; /* 04h */
1606 U32 Information; /* 08h */
1607 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1608 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1609
1610 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)
1611
1612 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
1613 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
1614 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
1615 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
1616 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
1617 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
1618 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
1619 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
1620 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1621 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
1622 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1623 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
1624 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)
1625 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
1626 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
1627
1628 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
1629 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
1630 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
1631 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
1632
1633
1634 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1635 {
1636 CONFIG_PAGE_HEADER Header; /* 00h */
1637 U32 RequestedParameters; /* 04h */
1638 U32 Reserved; /* 08h */
1639 U32 Configuration; /* 0Ch */
1640 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1641 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1642
1643 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)
1644
1645 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
1646 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
1647 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
1648 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1649 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1650 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1651 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1652 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1653 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1654 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
1655 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1656 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
1657 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)
1658 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1659 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1660
1661 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1662 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1663 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1664 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1665
1666
1667 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1668 {
1669 CONFIG_PAGE_HEADER Header; /* 00h */
1670 U32 DomainValidation; /* 04h */
1671 U32 ParityPipeSelect; /* 08h */
1672 U32 DataPipeSelect; /* 0Ch */
1673 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1674 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1675
1676 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
1677
1678 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
1679 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
1680 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
1681 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
1682 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
1683 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
1684 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
1685 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
1686 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
1687
1688 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
1689
1690 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
1691 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
1692 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
1693 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
1694 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
1695 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
1696 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
1697 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
1698 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
1699 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
1700 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
1701 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
1702 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
1703 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
1704 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
1705 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
1706
1707
1708 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1709 {
1710 CONFIG_PAGE_HEADER Header; /* 00h */
1711 U16 MsgRejectCount; /* 04h */
1712 U16 PhaseErrorCount; /* 06h */
1713 U16 ParityErrorCount; /* 08h */
1714 U16 Reserved; /* 0Ah */
1715 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1716 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1717
1718 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
1719
1720 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
1721 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
1722
1723
1724 /****************************************************************************
1725 * FC Port Config Pages
1726 ****************************************************************************/
1727
1728 typedef struct _CONFIG_PAGE_FC_PORT_0
1729 {
1730 CONFIG_PAGE_HEADER Header; /* 00h */
1731 U32 Flags; /* 04h */
1732 U8 MPIPortNumber; /* 08h */
1733 U8 LinkType; /* 09h */
1734 U8 PortState; /* 0Ah */
1735 U8 Reserved; /* 0Bh */
1736 U32 PortIdentifier; /* 0Ch */
1737 U64 WWNN; /* 10h */
1738 U64 WWPN; /* 18h */
1739 U32 SupportedServiceClass; /* 20h */
1740 U32 SupportedSpeeds; /* 24h */
1741 U32 CurrentSpeed; /* 28h */
1742 U32 MaxFrameSize; /* 2Ch */
1743 U64 FabricWWNN; /* 30h */
1744 U64 FabricWWPN; /* 38h */
1745 U32 DiscoveredPortsCount; /* 40h */
1746 U32 MaxInitiators; /* 44h */
1747 U8 MaxAliasesSupported; /* 48h */
1748 U8 MaxHardAliasesSupported; /* 49h */
1749 U8 NumCurrentAliases; /* 4Ah */
1750 U8 Reserved1; /* 4Bh */
1751 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1752 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1753
1754 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
1755
1756 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
1757 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1758 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
1759 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
1760 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1761
1762 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
1763 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
1764 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
1765
1766 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
1767 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
1768 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
1769 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
1770 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
1771 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
1772
1773 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
1774 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
1775 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
1776 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
1777 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
1778 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
1779 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
1780 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
1781 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
1782 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
1783 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
1784 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
1785 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
1786 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
1787 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
1788 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
1789
1790 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
1791 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
1792 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
1793 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
1794 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
1795 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1796 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1797 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1798
1799 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1800 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1801 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1802
1803 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1804 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1805 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1806 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1807 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1808
1809 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1810 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1811 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1812 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1813 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1814 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1815
1816
1817 typedef struct _CONFIG_PAGE_FC_PORT_1
1818 {
1819 CONFIG_PAGE_HEADER Header; /* 00h */
1820 U32 Flags; /* 04h */
1821 U64 NoSEEPROMWWNN; /* 08h */
1822 U64 NoSEEPROMWWPN; /* 10h */
1823 U8 HardALPA; /* 18h */
1824 U8 LinkConfig; /* 19h */
1825 U8 TopologyConfig; /* 1Ah */
1826 U8 AltConnector; /* 1Bh */
1827 U8 NumRequestedAliases; /* 1Ch */
1828 U8 RR_TOV; /* 1Dh */
1829 U8 InitiatorDeviceTimeout; /* 1Eh */
1830 U8 InitiatorIoPendTimeout; /* 1Fh */
1831 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1832 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1833
1834 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
1835
1836 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1837 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1838 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1839 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1840 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1841 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1842 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1843 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)
1844 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1845 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1846 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1847 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1848 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1849 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1850
1851 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1852 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1853 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1854 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1855 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1856 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1857
1858 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1859 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1860 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1861 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1862
1863 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1864
1865 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1866 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1867 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1868 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1869 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1870 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1871
1872 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1873 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1874 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1875 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1876
1877 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
1878
1879 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
1880 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80)
1881
1882
1883 typedef struct _CONFIG_PAGE_FC_PORT_2
1884 {
1885 CONFIG_PAGE_HEADER Header; /* 00h */
1886 U8 NumberActive; /* 04h */
1887 U8 ALPA[127]; /* 05h */
1888 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1889 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1890
1891 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1892
1893
1894 typedef struct _WWN_FORMAT
1895 {
1896 U64 WWNN; /* 00h */
1897 U64 WWPN; /* 08h */
1898 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1899 WWNFormat, MPI_POINTER pWWNFormat;
1900
1901 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1902 {
1903 WWN_FORMAT WWN;
1904 U32 Did;
1905 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1906 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1907
1908 typedef struct _FC_PORT_PERSISTENT
1909 {
1910 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
1911 U8 TargetID; /* 10h */
1912 U8 Bus; /* 11h */
1913 U16 Flags; /* 12h */
1914 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1915 PersistentData_t, MPI_POINTER pPersistentData_t;
1916
1917 #define MPI_PERSISTENT_FLAGS_SHIFT (16)
1918 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
1919 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
1920 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
1921 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
1922 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
1923
1924 /*
1925 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1926 * one and check Header.PageLength at runtime.
1927 */
1928 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1929 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1930 #endif
1931
1932 typedef struct _CONFIG_PAGE_FC_PORT_3
1933 {
1934 CONFIG_PAGE_HEADER Header; /* 00h */
1935 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
1936 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1937 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1938
1939 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1940
1941
1942 typedef struct _CONFIG_PAGE_FC_PORT_4
1943 {
1944 CONFIG_PAGE_HEADER Header; /* 00h */
1945 U32 PortFlags; /* 04h */
1946 U32 PortSettings; /* 08h */
1947 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1948 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1949
1950 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1951
1952 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1953
1954 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1955 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
1956 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
1957 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
1958 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
1959 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
1960 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
1961
1962
1963 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1964 {
1965 U8 Flags; /* 00h */
1966 U8 AliasAlpa; /* 01h */
1967 U16 Reserved; /* 02h */
1968 U64 AliasWWNN; /* 04h */
1969 U64 AliasWWPN; /* 0Ch */
1970 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1971 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1972 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1973
1974 typedef struct _CONFIG_PAGE_FC_PORT_5
1975 {
1976 CONFIG_PAGE_HEADER Header; /* 00h */
1977 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1978 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1979 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1980
1981 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1982
1983 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1984 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1985 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1986 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1987 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1988
1989 typedef struct _CONFIG_PAGE_FC_PORT_6
1990 {
1991 CONFIG_PAGE_HEADER Header; /* 00h */
1992 U32 Reserved; /* 04h */
1993 U64 TimeSinceReset; /* 08h */
1994 U64 TxFrames; /* 10h */
1995 U64 RxFrames; /* 18h */
1996 U64 TxWords; /* 20h */
1997 U64 RxWords; /* 28h */
1998 U64 LipCount; /* 30h */
1999 U64 NosCount; /* 38h */
2000 U64 ErrorFrames; /* 40h */
2001 U64 DumpedFrames; /* 48h */
2002 U64 LinkFailureCount; /* 50h */
2003 U64 LossOfSyncCount; /* 58h */
2004 U64 LossOfSignalCount; /* 60h */
2005 U64 PrimativeSeqErrCount; /* 68h */
2006 U64 InvalidTxWordCount; /* 70h */
2007 U64 InvalidCrcCount; /* 78h */
2008 U64 FcpInitiatorIoCount; /* 80h */
2009 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
2010 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
2011
2012 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
2013
2014
2015 typedef struct _CONFIG_PAGE_FC_PORT_7
2016 {
2017 CONFIG_PAGE_HEADER Header; /* 00h */
2018 U32 Reserved; /* 04h */
2019 U8 PortSymbolicName[256]; /* 08h */
2020 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
2021 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
2022
2023 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
2024
2025
2026 typedef struct _CONFIG_PAGE_FC_PORT_8
2027 {
2028 CONFIG_PAGE_HEADER Header; /* 00h */
2029 U32 BitVector[8]; /* 04h */
2030 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
2031 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
2032
2033 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
2034
2035
2036 typedef struct _CONFIG_PAGE_FC_PORT_9
2037 {
2038 CONFIG_PAGE_HEADER Header; /* 00h */
2039 U32 Reserved; /* 04h */
2040 U64 GlobalWWPN; /* 08h */
2041 U64 GlobalWWNN; /* 10h */
2042 U32 UnitType; /* 18h */
2043 U32 PhysicalPortNumber; /* 1Ch */
2044 U32 NumAttachedNodes; /* 20h */
2045 U16 IPVersion; /* 24h */
2046 U16 UDPPortNumber; /* 26h */
2047 U8 IPAddress[16]; /* 28h */
2048 U16 Reserved1; /* 38h */
2049 U16 TopologyDiscoveryFlags; /* 3Ah */
2050 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
2051 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
2052
2053 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
2054
2055
2056 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
2057 {
2058 U8 Id; /* 10h */
2059 U8 ExtId; /* 11h */
2060 U8 Connector; /* 12h */
2061 U8 Transceiver[8]; /* 13h */
2062 U8 Encoding; /* 1Bh */
2063 U8 BitRate_100mbs; /* 1Ch */
2064 U8 Reserved1; /* 1Dh */
2065 U8 Length9u_km; /* 1Eh */
2066 U8 Length9u_100m; /* 1Fh */
2067 U8 Length50u_10m; /* 20h */
2068 U8 Length62p5u_10m; /* 21h */
2069 U8 LengthCopper_m; /* 22h */
2070 U8 Reseverved2; /* 22h */
2071 U8 VendorName[16]; /* 24h */
2072 U8 Reserved3; /* 34h */
2073 U8 VendorOUI[3]; /* 35h */
2074 U8 VendorPN[16]; /* 38h */
2075 U8 VendorRev[4]; /* 48h */
2076 U16 Wavelength; /* 4Ch */
2077 U8 Reserved4; /* 4Eh */
2078 U8 CC_BASE; /* 4Fh */
2079 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
2080 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
2081 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
2082
2083 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
2084 #define MPI_FCPORT10_BASE_ID_GBIC (0x01)
2085 #define MPI_FCPORT10_BASE_ID_FIXED (0x02)
2086 #define MPI_FCPORT10_BASE_ID_SFP (0x03)
2087 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
2088 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
2089 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
2090
2091 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
2092 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
2093 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
2094 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
2095 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
2096 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
2097 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
2098 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
2099 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
2100
2101 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
2102 #define MPI_FCPORT10_BASE_CONN_SC (0x01)
2103 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
2104 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
2105 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
2106 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
2107 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
2108 #define MPI_FCPORT10_BASE_CONN_LC (0x07)
2109 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
2110 #define MPI_FCPORT10_BASE_CONN_MU (0x09)
2111 #define MPI_FCPORT10_BASE_CONN_SG (0x0A)
2112 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
2113 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
2114 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
2115 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
2116 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
2117 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
2118 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
2119 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
2120
2121 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
2122 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
2123 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
2124 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
2125 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
2126
2127
2128 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
2129 {
2130 U8 Options[2]; /* 50h */
2131 U8 BitRateMax; /* 52h */
2132 U8 BitRateMin; /* 53h */
2133 U8 VendorSN[16]; /* 54h */
2134 U8 DateCode[8]; /* 64h */
2135 U8 DiagMonitoringType; /* 6Ch */
2136 U8 EnhancedOptions; /* 6Dh */
2137 U8 SFF8472Compliance; /* 6Eh */
2138 U8 CC_EXT; /* 6Fh */
2139 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2140 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
2141 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
2142
2143 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
2144 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
2145 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
2146 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
2147 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
2148
2149
2150 typedef struct _CONFIG_PAGE_FC_PORT_10
2151 {
2152 CONFIG_PAGE_HEADER Header; /* 00h */
2153 U8 Flags; /* 04h */
2154 U8 Reserved1; /* 05h */
2155 U16 Reserved2; /* 06h */
2156 U32 HwConfig1; /* 08h */
2157 U32 HwConfig2; /* 0Ch */
2158 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
2159 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
2160 U8 VendorSpecific[32]; /* 70h */
2161 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
2162 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
2163
2164 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01)
2165
2166 /* standard MODDEF pin definitions (from GBIC spec.) */
2167 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
2168 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
2169 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
2170 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
2171 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
2172 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
2173 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
2174 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
2175 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
2176 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
2177 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
2178 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
2179
2180 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
2181 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
2182
2183
2184 /****************************************************************************
2185 * FC Device Config Pages
2186 ****************************************************************************/
2187
2188 typedef struct _CONFIG_PAGE_FC_DEVICE_0
2189 {
2190 CONFIG_PAGE_HEADER Header; /* 00h */
2191 U64 WWNN; /* 04h */
2192 U64 WWPN; /* 0Ch */
2193 U32 PortIdentifier; /* 14h */
2194 U8 Protocol; /* 18h */
2195 U8 Flags; /* 19h */
2196 U16 BBCredit; /* 1Ah */
2197 U16 MaxRxFrameSize; /* 1Ch */
2198 U8 ADISCHardALPA; /* 1Eh */
2199 U8 PortNumber; /* 1Fh */
2200 U8 FcPhLowestVersion; /* 20h */
2201 U8 FcPhHighestVersion; /* 21h */
2202 U8 CurrentTargetID; /* 22h */
2203 U8 CurrentBus; /* 23h */
2204 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
2205 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
2206
2207 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)
2208
2209 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
2210 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
2211 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
2212
2213 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
2214 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
2215 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
2216 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)
2217
2218 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
2219 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
2220 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
2221 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
2222 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
2223 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
2224 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
2225 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
2226
2227 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)
2228
2229 /****************************************************************************
2230 * RAID Volume Config Pages
2231 ****************************************************************************/
2232
2233 typedef struct _RAID_VOL0_PHYS_DISK
2234 {
2235 U16 Reserved; /* 00h */
2236 U8 PhysDiskMap; /* 02h */
2237 U8 PhysDiskNum; /* 03h */
2238 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
2239 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
2240
2241 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
2242 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
2243
2244 typedef struct _RAID_VOL0_STATUS
2245 {
2246 U8 Flags; /* 00h */
2247 U8 State; /* 01h */
2248 U16 Reserved; /* 02h */
2249 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
2250 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
2251
2252 /* RAID Volume Page 0 VolumeStatus defines */
2253 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
2254 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
2255 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
2256 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
2257 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10)
2258
2259 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
2260 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
2261 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
2262 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)
2263
2264 typedef struct _RAID_VOL0_SETTINGS
2265 {
2266 U16 Settings; /* 00h */
2267 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2268 U8 Reserved; /* 02h */
2269 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2270 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2271
2272 /* RAID Volume Page 0 VolumeSettings defines */
2273 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
2274 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
2275 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
2276 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
2277 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */
2278
2279 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0)
2280 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000)
2281 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040)
2282
2283 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
2284 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
2285
2286 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2287 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
2288 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
2289 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
2290 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
2291 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
2292 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
2293 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
2294 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
2295
2296 /*
2297 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2298 * one and check Header.PageLength at runtime.
2299 */
2300 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2301 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
2302 #endif
2303
2304 typedef struct _CONFIG_PAGE_RAID_VOL_0
2305 {
2306 CONFIG_PAGE_HEADER Header; /* 00h */
2307 U8 VolumeID; /* 04h */
2308 U8 VolumeBus; /* 05h */
2309 U8 VolumeIOC; /* 06h */
2310 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2311 RAID_VOL0_STATUS VolumeStatus; /* 08h */
2312 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
2313 U32 MaxLBA; /* 10h */
2314 U32 MaxLBAHigh; /* 14h */
2315 U32 StripeSize; /* 18h */
2316 U32 Reserved2; /* 1Ch */
2317 U32 Reserved3; /* 20h */
2318 U8 NumPhysDisks; /* 24h */
2319 U8 DataScrubRate; /* 25h */
2320 U8 ResyncRate; /* 26h */
2321 U8 InactiveStatus; /* 27h */
2322 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2323 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2324 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2325
2326 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07)
2327
2328 /* values for RAID Volume Page 0 InactiveStatus field */
2329 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
2330 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
2331 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
2332 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2333 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
2334 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2335 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
2336
2337
2338 typedef struct _CONFIG_PAGE_RAID_VOL_1
2339 {
2340 CONFIG_PAGE_HEADER Header; /* 00h */
2341 U8 VolumeID; /* 04h */
2342 U8 VolumeBus; /* 05h */
2343 U8 VolumeIOC; /* 06h */
2344 U8 Reserved0; /* 07h */
2345 U8 GUID[24]; /* 08h */
2346 U8 Name[32]; /* 20h */
2347 U64 WWID; /* 40h */
2348 U32 Reserved1; /* 48h */
2349 U32 Reserved2; /* 4Ch */
2350 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2351 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2352
2353 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)
2354
2355
2356 /****************************************************************************
2357 * RAID Physical Disk Config Pages
2358 ****************************************************************************/
2359
2360 typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2361 {
2362 U8 ErrorCdbByte; /* 00h */
2363 U8 ErrorSenseKey; /* 01h */
2364 U16 Reserved; /* 02h */
2365 U16 ErrorCount; /* 04h */
2366 U8 ErrorASC; /* 06h */
2367 U8 ErrorASCQ; /* 07h */
2368 U16 SmartCount; /* 08h */
2369 U8 SmartASC; /* 0Ah */
2370 U8 SmartASCQ; /* 0Bh */
2371 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2372 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2373
2374 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2375 {
2376 U8 VendorID[8]; /* 00h */
2377 U8 ProductID[16]; /* 08h */
2378 U8 ProductRevLevel[4]; /* 18h */
2379 U8 Info[32]; /* 1Ch */
2380 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2381 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2382
2383 typedef struct _RAID_PHYS_DISK0_SETTINGS
2384 {
2385 U8 SepID; /* 00h */
2386 U8 SepBus; /* 01h */
2387 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2388 U8 PhysDiskSettings; /* 03h */
2389 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2390 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2391
2392 typedef struct _RAID_PHYS_DISK0_STATUS
2393 {
2394 U8 Flags; /* 00h */
2395 U8 State; /* 01h */
2396 U16 Reserved; /* 02h */
2397 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2398 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2399
2400 /* RAID Physical Disk PhysDiskStatus flags */
2401
2402 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
2403 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
2404 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)
2405 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00)
2406 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08)
2407
2408 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
2409 #define MPI_PHYSDISK0_STATUS_MISSING (0x01)
2410 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
2411 #define MPI_PHYSDISK0_STATUS_FAILED (0x03)
2412 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
2413 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
2414 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
2415 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
2416
2417 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2418 {
2419 CONFIG_PAGE_HEADER Header; /* 00h */
2420 U8 PhysDiskID; /* 04h */
2421 U8 PhysDiskBus; /* 05h */
2422 U8 PhysDiskIOC; /* 06h */
2423 U8 PhysDiskNum; /* 07h */
2424 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
2425 U32 Reserved1; /* 0Ch */
2426 U8 ExtDiskIdentifier[8]; /* 10h */
2427 U8 DiskIdentifier[16]; /* 18h */
2428 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
2429 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
2430 U32 MaxLBA; /* 68h */
2431 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
2432 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2433 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2434
2435 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02)
2436
2437
2438 typedef struct _RAID_PHYS_DISK1_PATH
2439 {
2440 U8 PhysDiskID; /* 00h */
2441 U8 PhysDiskBus; /* 01h */
2442 U16 Reserved1; /* 02h */
2443 U64 WWID; /* 04h */
2444 U64 OwnerWWID; /* 0Ch */
2445 U8 OwnerIdentifier; /* 14h */
2446 U8 Reserved2; /* 15h */
2447 U16 Flags; /* 16h */
2448 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2449 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2450
2451 /* RAID Physical Disk Page 1 Flags field defines */
2452 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2453 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2454
2455
2456 /*
2457 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2458 * one and check Header.PageLength or NumPhysDiskPaths at runtime.
2459 */
2460 #ifndef MPI_RAID_PHYS_DISK1_PATH_MAX
2461 #define MPI_RAID_PHYS_DISK1_PATH_MAX (1)
2462 #endif
2463
2464 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2465 {
2466 CONFIG_PAGE_HEADER Header; /* 00h */
2467 U8 NumPhysDiskPaths; /* 04h */
2468 U8 PhysDiskNum; /* 05h */
2469 U16 Reserved2; /* 06h */
2470 U32 Reserved1; /* 08h */
2471 RAID_PHYS_DISK1_PATH Path[MPI_RAID_PHYS_DISK1_PATH_MAX];/* 0Ch */
2472 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2473 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2474
2475 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)
2476
2477
2478 /****************************************************************************
2479 * LAN Config Pages
2480 ****************************************************************************/
2481
2482 typedef struct _CONFIG_PAGE_LAN_0
2483 {
2484 ConfigPageHeader_t Header; /* 00h */
2485 U16 TxRxModes; /* 04h */
2486 U16 Reserved; /* 06h */
2487 U32 PacketPrePad; /* 08h */
2488 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
2489 LANPage0_t, MPI_POINTER pLANPage0_t;
2490
2491 #define MPI_LAN_PAGE0_PAGEVERSION (0x01)
2492
2493 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
2494 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
2495 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
2496
2497 typedef struct _CONFIG_PAGE_LAN_1
2498 {
2499 ConfigPageHeader_t Header; /* 00h */
2500 U16 Reserved; /* 04h */
2501 U8 CurrentDeviceState; /* 06h */
2502 U8 Reserved1; /* 07h */
2503 U32 MinPacketSize; /* 08h */
2504 U32 MaxPacketSize; /* 0Ch */
2505 U32 HardwareAddressLow; /* 10h */
2506 U32 HardwareAddressHigh; /* 14h */
2507 U32 MaxWireSpeedLow; /* 18h */
2508 U32 MaxWireSpeedHigh; /* 1Ch */
2509 U32 BucketsRemaining; /* 20h */
2510 U32 MaxReplySize; /* 24h */
2511 U32 NegWireSpeedLow; /* 28h */
2512 U32 NegWireSpeedHigh; /* 2Ch */
2513 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2514 LANPage1_t, MPI_POINTER pLANPage1_t;
2515
2516 #define MPI_LAN_PAGE1_PAGEVERSION (0x03)
2517
2518 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
2519 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
2520
2521
2522 /****************************************************************************
2523 * Inband Config Pages
2524 ****************************************************************************/
2525
2526 typedef struct _CONFIG_PAGE_INBAND_0
2527 {
2528 CONFIG_PAGE_HEADER Header; /* 00h */
2529 MPI_VERSION_FORMAT InbandVersion; /* 04h */
2530 U16 MaximumBuffers; /* 08h */
2531 U16 Reserved1; /* 0Ah */
2532 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2533 InbandPage0_t, MPI_POINTER pInbandPage0_t;
2534
2535 #define MPI_INBAND_PAGEVERSION (0x00)
2536
2537
2538
2539 /****************************************************************************
2540 * SAS IO Unit Config Pages
2541 ****************************************************************************/
2542
2543 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2544 {
2545 U8 Port; /* 00h */
2546 U8 PortFlags; /* 01h */
2547 U8 PhyFlags; /* 02h */
2548 U8 NegotiatedLinkRate; /* 03h */
2549 U32 ControllerPhyDeviceInfo;/* 04h */
2550 U16 AttachedDeviceHandle; /* 08h */
2551 U16 ControllerDevHandle; /* 0Ah */
2552 U32 DiscoveryStatus; /* 0Ch */
2553 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2554 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2555
2556 /*
2557 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2558 * one and check Header.PageLength at runtime.
2559 */
2560 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
2561 #define MPI_SAS_IOUNIT0_PHY_MAX (1)
2562 #endif
2563
2564 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2565 {
2566 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2567 U16 NvdataVersionDefault; /* 08h */
2568 U16 NvdataVersionPersistent; /* 0Ah */
2569 U8 NumPhys; /* 0Ch */
2570 U8 Reserved2; /* 0Dh */
2571 U16 Reserved3; /* 0Eh */
2572 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
2573 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2574 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2575
2576 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04)
2577
2578 /* values for SAS IO Unit Page 0 PortFlags */
2579 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
2580 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2581 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2582 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2583
2584 /* values for SAS IO Unit Page 0 PhyFlags */
2585 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
2586 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
2587 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
2588
2589 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2590 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
2591 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
2592 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
2593 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
2594 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
2595 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
2596
2597 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2598
2599 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2600 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)
2601 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2602 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2603 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)
2604 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2605 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2606 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2607 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2608 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2609 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2610 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)
2611 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2612 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000)
2613 #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
2614
2615
2616 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2617 {
2618 U8 Port; /* 00h */
2619 U8 PortFlags; /* 01h */
2620 U8 PhyFlags; /* 02h */
2621 U8 MaxMinLinkRate; /* 03h */
2622 U32 ControllerPhyDeviceInfo; /* 04h */
2623 U16 MaxTargetPortConnectTime; /* 08h */
2624 U16 Reserved1; /* 0Ah */
2625 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2626 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2627
2628 /*
2629 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2630 * one and check Header.PageLength at runtime.
2631 */
2632 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
2633 #define MPI_SAS_IOUNIT1_PHY_MAX (1)
2634 #endif
2635
2636 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2637 {
2638 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2639 U16 ControlFlags; /* 08h */
2640 U16 MaxNumSATATargets; /* 0Ah */
2641 U16 AdditionalControlFlags; /* 0Ch */
2642 U16 Reserved1; /* 0Eh */
2643 U8 NumPhys; /* 10h */
2644 U8 SATAMaxQDepth; /* 11h */
2645 U8 ReportDeviceMissingDelay; /* 12h */
2646 U8 IODeviceMissingDelay; /* 13h */
2647 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */
2648 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2649 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2650
2651 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07)
2652
2653 /* values for SAS IO Unit Page 1 ControlFlags */
2654 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2655 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2656 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2657 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2658 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)
2659
2660 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2661 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2662 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)
2663 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)
2664 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02)
2665
2666 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100)
2667 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2668 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2669 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2670 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2671 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)
2672 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2673 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2674 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2675
2676 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2677 #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2678 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2679 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020)
2680 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2681 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2682 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2683 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2684 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2685
2686 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2687 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2688 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2689
2690 /* values for SAS IO Unit Page 1 PortFlags */
2691 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2692 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2693 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2694
2695 /* values for SAS IO Unit Page 0 PhyFlags */
2696 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
2697 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
2698 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
2699
2700 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
2701 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
2702 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
2703 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
2704 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
2705 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
2706 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
2707
2708 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2709
2710
2711 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2712 {
2713 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2714 U8 NumDevsPerEnclosure; /* 08h */
2715 U8 Reserved1; /* 09h */
2716 U16 Reserved2; /* 0Ah */
2717 U16 MaxPersistentIDs; /* 0Ch */
2718 U16 NumPersistentIDsUsed; /* 0Eh */
2719 U8 Status; /* 10h */
2720 U8 Flags; /* 11h */
2721 U16 MaxNumPhysicalMappedIDs;/* 12h */
2722 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2723 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2724
2725 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x06)
2726
2727 /* values for SAS IO Unit Page 2 Status field */
2728 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08)
2729 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04)
2730 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2731 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
2732
2733 /* values for SAS IO Unit Page 2 Flags field */
2734 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
2735 /* Physical Mapping Modes */
2736 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)
2737 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)
2738 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)
2739 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)
2740 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)
2741 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07)
2742
2743 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)
2744 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20)
2745
2746
2747 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2748 {
2749 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2750 U32 Reserved1; /* 08h */
2751 U32 MaxInvalidDwordCount; /* 0Ch */
2752 U32 InvalidDwordCountTime; /* 10h */
2753 U32 MaxRunningDisparityErrorCount; /* 14h */
2754 U32 RunningDisparityErrorTime; /* 18h */
2755 U32 MaxLossDwordSynchCount; /* 1Ch */
2756 U32 LossDwordSynchCountTime; /* 20h */
2757 U32 MaxPhyResetProblemCount; /* 24h */
2758 U32 PhyResetProblemTime; /* 28h */
2759 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2760 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2761
2762 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
2763
2764
2765 /****************************************************************************
2766 * SAS Expander Config Pages
2767 ****************************************************************************/
2768
2769 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2770 {
2771 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2772 U8 PhysicalPort; /* 08h */
2773 U8 Reserved1; /* 09h */
2774 U16 EnclosureHandle; /* 0Ah */
2775 U64 SASAddress; /* 0Ch */
2776 U32 DiscoveryStatus; /* 14h */
2777 U16 DevHandle; /* 18h */
2778 U16 ParentDevHandle; /* 1Ah */
2779 U16 ExpanderChangeCount; /* 1Ch */
2780 U16 ExpanderRouteIndexes; /* 1Eh */
2781 U8 NumPhys; /* 20h */
2782 U8 SASLevel; /* 21h */
2783 U8 Flags; /* 22h */
2784 U8 Reserved3; /* 23h */
2785 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2786 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2787
2788 #define MPI_SASEXPANDER0_PAGEVERSION (0x03)
2789
2790 /* values for SAS Expander Page 0 DiscoveryStatus field */
2791 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2792 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2793 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2794 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)
2795 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2796 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2797 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2798 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2799 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2800 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2801 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2802 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2803
2804 /* values for SAS Expander Page 0 Flags field */
2805 #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04)
2806 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
2807 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
2808
2809
2810 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2811 {
2812 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2813 U8 PhysicalPort; /* 08h */
2814 U8 Reserved1; /* 09h */
2815 U16 Reserved2; /* 0Ah */
2816 U8 NumPhys; /* 0Ch */
2817 U8 Phy; /* 0Dh */
2818 U16 NumTableEntriesProgrammed; /* 0Eh */
2819 U8 ProgrammedLinkRate; /* 10h */
2820 U8 HwLinkRate; /* 11h */
2821 U16 AttachedDevHandle; /* 12h */
2822 U32 PhyInfo; /* 14h */
2823 U32 AttachedDeviceInfo; /* 18h */
2824 U16 OwnerDevHandle; /* 1Ch */
2825 U8 ChangeCount; /* 1Eh */
2826 U8 NegotiatedLinkRate; /* 1Fh */
2827 U8 PhyIdentifier; /* 20h */
2828 U8 AttachedPhyIdentifier; /* 21h */
2829 U8 Reserved3; /* 22h */
2830 U8 DiscoveryInfo; /* 23h */
2831 U32 Reserved4; /* 24h */
2832 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2833 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2834
2835 #define MPI_SASEXPANDER1_PAGEVERSION (0x01)
2836
2837 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2838
2839 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2840
2841 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2842
2843 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2844
2845 /* values for SAS Expander Page 1 DiscoveryInfo field */
2846 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2847 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2848 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2849
2850 /* values for SAS Expander Page 1 NegotiatedLinkRate field */
2851 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)
2852 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)
2853 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)
2854 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)
2855 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)
2856 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)
2857
2858
2859 /****************************************************************************
2860 * SAS Device Config Pages
2861 ****************************************************************************/
2862
2863 typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2864 {
2865 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2866 U16 Slot; /* 08h */
2867 U16 EnclosureHandle; /* 0Ah */
2868 U64 SASAddress; /* 0Ch */
2869 U16 ParentDevHandle; /* 14h */
2870 U8 PhyNum; /* 16h */
2871 U8 AccessStatus; /* 17h */
2872 U16 DevHandle; /* 18h */
2873 U8 TargetID; /* 1Ah */
2874 U8 Bus; /* 1Bh */
2875 U32 DeviceInfo; /* 1Ch */
2876 U16 Flags; /* 20h */
2877 U8 PhysicalPort; /* 22h */
2878 U8 Reserved2; /* 23h */
2879 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2880 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2881
2882 #define MPI_SASDEVICE0_PAGEVERSION (0x05)
2883
2884 /* values for SAS Device Page 0 AccessStatus field */
2885 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2886 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2887 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2888 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2889 #define MPI_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2890 /* specific values for SATA Init failures */
2891 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2892 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2893 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2894 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2895 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2896 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2897 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2898 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2899 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2900 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2901 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2902
2903 /* values for SAS Device Page 0 Flags field */
2904 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2905 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2906 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2907 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2908 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2909 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2910 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2911 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2912 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)
2913 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)
2914 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2915
2916 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2917
2918
2919 typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2920 {
2921 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2922 U32 Reserved1; /* 08h */
2923 U64 SASAddress; /* 0Ch */
2924 U32 Reserved2; /* 14h */
2925 U16 DevHandle; /* 18h */
2926 U8 TargetID; /* 1Ah */
2927 U8 Bus; /* 1Bh */
2928 U8 InitialRegDeviceFIS[20];/* 1Ch */
2929 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2930 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2931
2932 #define MPI_SASDEVICE1_PAGEVERSION (0x00)
2933
2934
2935 typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2936 {
2937 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2938 U64 PhysicalIdentifier; /* 08h */
2939 U32 EnclosureMapping; /* 10h */
2940 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2941 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2942
2943 #define MPI_SASDEVICE2_PAGEVERSION (0x01)
2944
2945 /* defines for SAS Device Page 2 EnclosureMapping field */
2946 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F)
2947 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0)
2948 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0)
2949 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4)
2950 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800)
2951 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11)
2952
2953
2954 /****************************************************************************
2955 * SAS PHY Config Pages
2956 ****************************************************************************/
2957
2958 typedef struct _CONFIG_PAGE_SAS_PHY_0
2959 {
2960 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2961 U16 OwnerDevHandle; /* 08h */
2962 U16 Reserved1; /* 0Ah */
2963 U64 SASAddress; /* 0Ch */
2964 U16 AttachedDevHandle; /* 14h */
2965 U8 AttachedPhyIdentifier; /* 16h */
2966 U8 Reserved2; /* 17h */
2967 U32 AttachedDeviceInfo; /* 18h */
2968 U8 ProgrammedLinkRate; /* 1Ch */
2969 U8 HwLinkRate; /* 1Dh */
2970 U8 ChangeCount; /* 1Eh */
2971 U8 Flags; /* 1Fh */
2972 U32 PhyInfo; /* 20h */
2973 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2974 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2975
2976 #define MPI_SASPHY0_PAGEVERSION (0x01)
2977
2978 /* values for SAS PHY Page 0 ProgrammedLinkRate field */
2979 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2980 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2981 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2982 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2983 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2984 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2985 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2986 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2987
2988 /* values for SAS PHY Page 0 HwLinkRate field */
2989 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2990 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2991 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2992 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2993 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2994 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2995
2996 /* values for SAS PHY Page 0 Flags field */
2997 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2998
2999 /* values for SAS PHY Page 0 PhyInfo field */
3000 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
3001 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
3002 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
3003
3004 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
3005 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
3006
3007 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
3008 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
3009 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
3010 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
3011
3012 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
3013 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
3014 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
3015 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
3016 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
3017 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
3018 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
3019
3020
3021 typedef struct _CONFIG_PAGE_SAS_PHY_1
3022 {
3023 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3024 U32 Reserved1; /* 08h */
3025 U32 InvalidDwordCount; /* 0Ch */
3026 U32 RunningDisparityErrorCount; /* 10h */
3027 U32 LossDwordSynchCount; /* 14h */
3028 U32 PhyResetProblemCount; /* 18h */
3029 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
3030 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
3031
3032 #define MPI_SASPHY1_PAGEVERSION (0x00)
3033
3034
3035 /****************************************************************************
3036 * SAS Enclosure Config Pages
3037 ****************************************************************************/
3038
3039 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
3040 {
3041 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3042 U32 Reserved1; /* 08h */
3043 U64 EnclosureLogicalID; /* 0Ch */
3044 U16 Flags; /* 14h */
3045 U16 EnclosureHandle; /* 16h */
3046 U16 NumSlots; /* 18h */
3047 U16 StartSlot; /* 1Ah */
3048 U8 StartTargetID; /* 1Ch */
3049 U8 StartBus; /* 1Dh */
3050 U8 SEPTargetID; /* 1Eh */
3051 U8 SEPBus; /* 1Fh */
3052 U32 Reserved2; /* 20h */
3053 U32 Reserved3; /* 24h */
3054 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
3055 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
3056
3057 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01)
3058
3059 /* values for SAS Enclosure Page 0 Flags field */
3060 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)
3061 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)
3062
3063 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3064 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3065 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3066 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3067 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3068 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3069 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3070
3071
3072 /****************************************************************************
3073 * Log Config Pages
3074 ****************************************************************************/
3075 /*
3076 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3077 * one and check NumLogEntries at runtime.
3078 */
3079 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES
3080 #define MPI_LOG_0_NUM_LOG_ENTRIES (1)
3081 #endif
3082
3083 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C)
3084
3085 typedef struct _MPI_LOG_0_ENTRY
3086 {
3087 U32 TimeStamp; /* 00h */
3088 U32 Reserved1; /* 04h */
3089 U16 LogSequence; /* 08h */
3090 U16 LogEntryQualifier; /* 0Ah */
3091 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */
3092 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
3093 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
3094
3095 /* values for Log Page 0 LogEntry LogEntryQualifier field */
3096 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3097 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3098
3099 typedef struct _CONFIG_PAGE_LOG_0
3100 {
3101 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
3102 U32 Reserved1; /* 08h */
3103 U32 Reserved2; /* 0Ch */
3104 U16 NumLogEntries; /* 10h */
3105 U16 Reserved3; /* 12h */
3106 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
3107 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
3108 LogPage0_t, MPI_POINTER pLogPage0_t;
3109
3110 #define MPI_LOG_0_PAGEVERSION (0x01)
3111
3112
3113 #endif
3114
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