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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / mmc / host / mxcmmc.c
blob88671529c45d7690061f289d8fe005abd4701a09
1 /*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the seperate driver.
8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
32 #include <linux/io.h>
33 #include <linux/gpio.h>
34
35 #include <asm/dma.h>
36 #include <asm/irq.h>
37 #include <asm/sizes.h>
38 #include <mach/mmc.h>
39
40 #ifdef CONFIG_ARCH_MX2
41 #include <mach/dma-mx1-mx2.h>
42 #define HAS_DMA
43 #endif
44
45 #define DRIVER_NAME "mxc-mmc"
46
47 #define MMC_REG_STR_STP_CLK 0x00
48 #define MMC_REG_STATUS 0x04
49 #define MMC_REG_CLK_RATE 0x08
50 #define MMC_REG_CMD_DAT_CONT 0x0C
51 #define MMC_REG_RES_TO 0x10
52 #define MMC_REG_READ_TO 0x14
53 #define MMC_REG_BLK_LEN 0x18
54 #define MMC_REG_NOB 0x1C
55 #define MMC_REG_REV_NO 0x20
56 #define MMC_REG_INT_CNTR 0x24
57 #define MMC_REG_CMD 0x28
58 #define MMC_REG_ARG 0x2C
59 #define MMC_REG_RES_FIFO 0x34
60 #define MMC_REG_BUFFER_ACCESS 0x38
61
62 #define STR_STP_CLK_RESET (1 << 3)
63 #define STR_STP_CLK_START_CLK (1 << 1)
64 #define STR_STP_CLK_STOP_CLK (1 << 0)
65
66 #define STATUS_CARD_INSERTION (1 << 31)
67 #define STATUS_CARD_REMOVAL (1 << 30)
68 #define STATUS_YBUF_EMPTY (1 << 29)
69 #define STATUS_XBUF_EMPTY (1 << 28)
70 #define STATUS_YBUF_FULL (1 << 27)
71 #define STATUS_XBUF_FULL (1 << 26)
72 #define STATUS_BUF_UND_RUN (1 << 25)
73 #define STATUS_BUF_OVFL (1 << 24)
74 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
75 #define STATUS_END_CMD_RESP (1 << 13)
76 #define STATUS_WRITE_OP_DONE (1 << 12)
77 #define STATUS_DATA_TRANS_DONE (1 << 11)
78 #define STATUS_READ_OP_DONE (1 << 11)
79 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81 #define STATUS_BUF_READ_RDY (1 << 7)
82 #define STATUS_BUF_WRITE_RDY (1 << 6)
83 #define STATUS_RESP_CRC_ERR (1 << 5)
84 #define STATUS_CRC_READ_ERR (1 << 3)
85 #define STATUS_CRC_WRITE_ERR (1 << 2)
86 #define STATUS_TIME_OUT_RESP (1 << 1)
87 #define STATUS_TIME_OUT_READ (1 << 0)
88 #define STATUS_ERR_MASK 0x2f
89
90 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
93 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94 #define CMD_DAT_CONT_INIT (1 << 7)
95 #define CMD_DAT_CONT_WRITE (1 << 4)
96 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100
101 #define INT_SDIO_INT_WKP_EN (1 << 18)
102 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
103 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104 #define INT_CARD_INSERTION_EN (1 << 15)
105 #define INT_CARD_REMOVAL_EN (1 << 14)
106 #define INT_SDIO_IRQ_EN (1 << 13)
107 #define INT_DAT0_EN (1 << 12)
108 #define INT_BUF_READ_EN (1 << 4)
109 #define INT_BUF_WRITE_EN (1 << 3)
110 #define INT_END_CMD_RES_EN (1 << 2)
111 #define INT_WRITE_OP_DONE_EN (1 << 1)
112 #define INT_READ_OP_EN (1 << 0)
113
114 struct mxcmci_host {
115 struct mmc_host *mmc;
116 struct resource *res;
117 void __iomem *base;
118 int irq;
119 int detect_irq;
120 int dma;
121 int do_dma;
122 unsigned int power_mode;
123 struct imxmmc_platform_data *pdata;
124
125 struct mmc_request *req;
126 struct mmc_command *cmd;
127 struct mmc_data *data;
128
129 unsigned int dma_nents;
130 unsigned int datasize;
131 unsigned int dma_dir;
132
133 u16 rev_no;
134 unsigned int cmdat;
135
136 struct clk *clk;
137
138 int clock;
139
140 struct work_struct datawork;
141 };
142
143 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
144
145 static inline int mxcmci_use_dma(struct mxcmci_host *host)
146 {
147 return host->do_dma;
148 }
149
150 static void mxcmci_softreset(struct mxcmci_host *host)
151 {
152 int i;
153
154 /* reset sequence */
155 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
156 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
157 host->base + MMC_REG_STR_STP_CLK);
158
159 for (i = 0; i < 8; i++)
160 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
161
162 writew(0xff, host->base + MMC_REG_RES_TO);
163 }
164
165 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
166 {
167 unsigned int nob = data->blocks;
168 unsigned int blksz = data->blksz;
169 unsigned int datasize = nob * blksz;
170 #ifdef HAS_DMA
171 struct scatterlist *sg;
172 int i;
173 int ret;
174 #endif
175 if (data->flags & MMC_DATA_STREAM)
176 nob = 0xffff;
177
178 host->data = data;
179 data->bytes_xfered = 0;
180
181 writew(nob, host->base + MMC_REG_NOB);
182 writew(blksz, host->base + MMC_REG_BLK_LEN);
183 host->datasize = datasize;
184
185 #ifdef HAS_DMA
186 for_each_sg(data->sg, sg, data->sg_len, i) {
187 if (sg->offset & 3 || sg->length & 3) {
188 host->do_dma = 0;
189 return 0;
190 }
191 }
192
193 if (data->flags & MMC_DATA_READ) {
194 host->dma_dir = DMA_FROM_DEVICE;
195 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
196 data->sg_len, host->dma_dir);
197
198 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
199 datasize,
200 host->res->start + MMC_REG_BUFFER_ACCESS,
201 DMA_MODE_READ);
202 } else {
203 host->dma_dir = DMA_TO_DEVICE;
204 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
205 data->sg_len, host->dma_dir);
206
207 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
208 datasize,
209 host->res->start + MMC_REG_BUFFER_ACCESS,
210 DMA_MODE_WRITE);
211 }
212
213 if (ret) {
214 dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret);
215 return ret;
216 }
217 wmb();
218
219 imx_dma_enable(host->dma);
220 #endif /* HAS_DMA */
221 return 0;
222 }
223
224 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
225 unsigned int cmdat)
226 {
227 WARN_ON(host->cmd != NULL);
228 host->cmd = cmd;
229
230 switch (mmc_resp_type(cmd)) {
231 case MMC_RSP_R1: /* short CRC, OPCODE */
232 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
233 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
234 break;
235 case MMC_RSP_R2: /* long 136 bit + CRC */
236 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
237 break;
238 case MMC_RSP_R3: /* short */
239 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
240 break;
241 case MMC_RSP_NONE:
242 break;
243 default:
244 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
245 mmc_resp_type(cmd));
246 cmd->error = -EINVAL;
247 return -EINVAL;
248 }
249
250 if (mxcmci_use_dma(host))
251 writel(INT_READ_OP_EN | INT_WRITE_OP_DONE_EN |
252 INT_END_CMD_RES_EN,
253 host->base + MMC_REG_INT_CNTR);
254 else
255 writel(INT_END_CMD_RES_EN, host->base + MMC_REG_INT_CNTR);
256
257 writew(cmd->opcode, host->base + MMC_REG_CMD);
258 writel(cmd->arg, host->base + MMC_REG_ARG);
259 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
260
261 return 0;
262 }
263
264 static void mxcmci_finish_request(struct mxcmci_host *host,
265 struct mmc_request *req)
266 {
267 writel(0, host->base + MMC_REG_INT_CNTR);
268
269 host->req = NULL;
270 host->cmd = NULL;
271 host->data = NULL;
272
273 mmc_request_done(host->mmc, req);
274 }
275
276 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
277 {
278 struct mmc_data *data = host->data;
279 int data_error;
280
281 #ifdef HAS_DMA
282 if (mxcmci_use_dma(host)) {
283 imx_dma_disable(host->dma);
284 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
285 host->dma_dir);
286 }
287 #endif
288
289 if (stat & STATUS_ERR_MASK) {
290 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
291 stat);
292 if (stat & STATUS_CRC_READ_ERR) {
293 data->error = -EILSEQ;
294 } else if (stat & STATUS_CRC_WRITE_ERR) {
295 u32 err_code = (stat >> 9) & 0x3;
296 if (err_code == 2) /* No CRC response */
297 data->error = -ETIMEDOUT;
298 else
299 data->error = -EILSEQ;
300 } else if (stat & STATUS_TIME_OUT_READ) {
301 data->error = -ETIMEDOUT;
302 } else {
303 data->error = -EIO;
304 }
305 } else {
306 data->bytes_xfered = host->datasize;
307 }
308
309 data_error = data->error;
310
311 host->data = NULL;
312
313 return data_error;
314 }
315
316 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
317 {
318 struct mmc_command *cmd = host->cmd;
319 int i;
320 u32 a, b, c;
321
322 if (!cmd)
323 return;
324
325 if (stat & STATUS_TIME_OUT_RESP) {
326 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
327 cmd->error = -ETIMEDOUT;
328 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
329 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
330 cmd->error = -EILSEQ;
331 }
332
333 if (cmd->flags & MMC_RSP_PRESENT) {
334 if (cmd->flags & MMC_RSP_136) {
335 for (i = 0; i < 4; i++) {
336 a = readw(host->base + MMC_REG_RES_FIFO);
337 b = readw(host->base + MMC_REG_RES_FIFO);
338 cmd->resp[i] = a << 16 | b;
339 }
340 } else {
341 a = readw(host->base + MMC_REG_RES_FIFO);
342 b = readw(host->base + MMC_REG_RES_FIFO);
343 c = readw(host->base + MMC_REG_RES_FIFO);
344 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
345 }
346 }
347 }
348
349 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
350 {
351 u32 stat;
352 unsigned long timeout = jiffies + HZ;
353
354 do {
355 stat = readl(host->base + MMC_REG_STATUS);
356 if (stat & STATUS_ERR_MASK)
357 return stat;
358 if (time_after(jiffies, timeout)) {
359 mxcmci_softreset(host);
360 mxcmci_set_clk_rate(host, host->clock);
361 return STATUS_TIME_OUT_READ;
362 }
363 if (stat & mask)
364 return 0;
365 cpu_relax();
366 } while (1);
367 }
368
369 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
370 {
371 unsigned int stat;
372 u32 *buf = _buf;
373
374 while (bytes > 3) {
375 stat = mxcmci_poll_status(host,
376 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
377 if (stat)
378 return stat;
379 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
380 bytes -= 4;
381 }
382
383 if (bytes) {
384 u8 *b = (u8 *)buf;
385 u32 tmp;
386
387 stat = mxcmci_poll_status(host,
388 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
389 if (stat)
390 return stat;
391 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
392 memcpy(b, &tmp, bytes);
393 }
394
395 return 0;
396 }
397
398 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
399 {
400 unsigned int stat;
401 u32 *buf = _buf;
402
403 while (bytes > 3) {
404 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
405 if (stat)
406 return stat;
407 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
408 bytes -= 4;
409 }
410
411 if (bytes) {
412 u8 *b = (u8 *)buf;
413 u32 tmp;
414
415 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
416 if (stat)
417 return stat;
418
419 memcpy(&tmp, b, bytes);
420 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
421 }
422
423 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
424 if (stat)
425 return stat;
426
427 return 0;
428 }
429
430 static int mxcmci_transfer_data(struct mxcmci_host *host)
431 {
432 struct mmc_data *data = host->req->data;
433 struct scatterlist *sg;
434 int stat, i;
435
436 host->datasize = 0;
437
438 host->data = data;
439 host->datasize = 0;
440
441 if (data->flags & MMC_DATA_READ) {
442 for_each_sg(data->sg, sg, data->sg_len, i) {
443 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
444 if (stat)
445 return stat;
446 host->datasize += sg->length;
447 }
448 } else {
449 for_each_sg(data->sg, sg, data->sg_len, i) {
450 stat = mxcmci_push(host, sg_virt(sg), sg->length);
451 if (stat)
452 return stat;
453 host->datasize += sg->length;
454 }
455 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
456 if (stat)
457 return stat;
458 }
459 return 0;
460 }
461
462 static void mxcmci_datawork(struct work_struct *work)
463 {
464 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
465 datawork);
466 int datastat = mxcmci_transfer_data(host);
467 mxcmci_finish_data(host, datastat);
468
469 if (host->req->stop) {
470 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
471 mxcmci_finish_request(host, host->req);
472 return;
473 }
474 } else {
475 mxcmci_finish_request(host, host->req);
476 }
477 }
478
479 #ifdef HAS_DMA
480 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
481 {
482 struct mmc_data *data = host->data;
483 int data_error;
484
485 if (!data)
486 return;
487
488 data_error = mxcmci_finish_data(host, stat);
489
490 mxcmci_read_response(host, stat);
491 host->cmd = NULL;
492
493 if (host->req->stop) {
494 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
495 mxcmci_finish_request(host, host->req);
496 return;
497 }
498 } else {
499 mxcmci_finish_request(host, host->req);
500 }
501 }
502 #endif /* HAS_DMA */
503
504 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
505 {
506 mxcmci_read_response(host, stat);
507 host->cmd = NULL;
508
509 if (!host->data && host->req) {
510 mxcmci_finish_request(host, host->req);
511 return;
512 }
513
514 /* For the DMA case the DMA engine handles the data transfer
515 * automatically. For non DMA we have to do it ourselves.
516 * Don't do it in interrupt context though.
517 */
518 if (!mxcmci_use_dma(host) && host->data)
519 schedule_work(&host->datawork);
520
521 }
522
523 static irqreturn_t mxcmci_irq(int irq, void *devid)
524 {
525 struct mxcmci_host *host = devid;
526 u32 stat;
527
528 stat = readl(host->base + MMC_REG_STATUS);
529 writel(stat, host->base + MMC_REG_STATUS);
530
531 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
532
533 if (stat & STATUS_END_CMD_RESP)
534 mxcmci_cmd_done(host, stat);
535 #ifdef HAS_DMA
536 if (mxcmci_use_dma(host) &&
537 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
538 mxcmci_data_done(host, stat);
539 #endif
540 return IRQ_HANDLED;
541 }
542
543 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
544 {
545 struct mxcmci_host *host = mmc_priv(mmc);
546 unsigned int cmdat = host->cmdat;
547 int error;
548
549 WARN_ON(host->req != NULL);
550
551 host->req = req;
552 host->cmdat &= ~CMD_DAT_CONT_INIT;
553 #ifdef HAS_DMA
554 host->do_dma = 1;
555 #endif
556 if (req->data) {
557 error = mxcmci_setup_data(host, req->data);
558 if (error) {
559 req->cmd->error = error;
560 goto out;
561 }
562
563
564 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
565
566 if (req->data->flags & MMC_DATA_WRITE)
567 cmdat |= CMD_DAT_CONT_WRITE;
568 }
569
570 error = mxcmci_start_cmd(host, req->cmd, cmdat);
571 out:
572 if (error)
573 mxcmci_finish_request(host, req);
574 }
575
576 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
577 {
578 unsigned int divider;
579 int prescaler = 0;
580 unsigned int clk_in = clk_get_rate(host->clk);
581
582 while (prescaler <= 0x800) {
583 for (divider = 1; divider <= 0xF; divider++) {
584 int x;
585
586 x = (clk_in / (divider + 1));
587
588 if (prescaler)
589 x /= (prescaler * 2);
590
591 if (x <= clk_ios)
592 break;
593 }
594 if (divider < 0x10)
595 break;
596
597 if (prescaler == 0)
598 prescaler = 1;
599 else
600 prescaler <<= 1;
601 }
602
603 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
604
605 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
606 prescaler, divider, clk_in, clk_ios);
607 }
608
609 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
610 {
611 struct mxcmci_host *host = mmc_priv(mmc);
612 #ifdef HAS_DMA
613 unsigned int blen;
614 /*
615 * use burstlen of 64 in 4 bit mode (--> reg value 0)
616 * use burstlen of 16 in 1 bit mode (--> reg value 16)
617 */
618 if (ios->bus_width == MMC_BUS_WIDTH_4)
619 blen = 0;
620 else
621 blen = 16;
622
623 imx_dma_config_burstlen(host->dma, blen);
624 #endif
625 if (ios->bus_width == MMC_BUS_WIDTH_4)
626 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
627 else
628 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
629
630 if (host->power_mode != ios->power_mode) {
631 if (host->pdata && host->pdata->setpower)
632 host->pdata->setpower(mmc_dev(mmc), ios->vdd);
633 host->power_mode = ios->power_mode;
634 if (ios->power_mode == MMC_POWER_ON)
635 host->cmdat |= CMD_DAT_CONT_INIT;
636 }
637
638 if (ios->clock) {
639 mxcmci_set_clk_rate(host, ios->clock);
640 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
641 } else {
642 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
643 }
644
645 host->clock = ios->clock;
646 }
647
648 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
649 {
650 struct mmc_host *mmc = data;
651
652 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
653
654 mmc_detect_change(mmc, msecs_to_jiffies(250));
655 return IRQ_HANDLED;
656 }
657
658 static int mxcmci_get_ro(struct mmc_host *mmc)
659 {
660 struct mxcmci_host *host = mmc_priv(mmc);
661
662 if (host->pdata && host->pdata->get_ro)
663 return !!host->pdata->get_ro(mmc_dev(mmc));
664 /*
665 * Board doesn't support read only detection; let the mmc core
666 * decide what to do.
667 */
668 return -ENOSYS;
669 }
670
671
672 static const struct mmc_host_ops mxcmci_ops = {
673 .request = mxcmci_request,
674 .set_ios = mxcmci_set_ios,
675 .get_ro = mxcmci_get_ro,
676 };
677
678 static int mxcmci_probe(struct platform_device *pdev)
679 {
680 struct mmc_host *mmc;
681 struct mxcmci_host *host = NULL;
682 struct resource *r;
683 int ret = 0, irq;
684
685 printk(KERN_INFO "i.MX SDHC driver\n");
686
687 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
688 irq = platform_get_irq(pdev, 0);
689 if (!r || irq < 0)
690 return -EINVAL;
691
692 r = request_mem_region(r->start, resource_size(r), pdev->name);
693 if (!r)
694 return -EBUSY;
695
696 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
697 if (!mmc) {
698 ret = -ENOMEM;
699 goto out_release_mem;
700 }
701
702 mmc->ops = &mxcmci_ops;
703 mmc->caps = MMC_CAP_4_BIT_DATA;
704
705 /* MMC core transfer sizes tunable parameters */
706 mmc->max_hw_segs = 64;
707 mmc->max_phys_segs = 64;
708 mmc->max_blk_size = 2048;
709 mmc->max_blk_count = 65535;
710 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
711 mmc->max_seg_size = mmc->max_seg_size;
712
713 host = mmc_priv(mmc);
714 host->base = ioremap(r->start, resource_size(r));
715 if (!host->base) {
716 ret = -ENOMEM;
717 goto out_free;
718 }
719
720 host->mmc = mmc;
721 host->pdata = pdev->dev.platform_data;
722
723 if (host->pdata && host->pdata->ocr_avail)
724 mmc->ocr_avail = host->pdata->ocr_avail;
725 else
726 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
727
728 host->res = r;
729 host->irq = irq;
730
731 host->clk = clk_get(&pdev->dev, NULL);
732 if (IS_ERR(host->clk)) {
733 ret = PTR_ERR(host->clk);
734 goto out_iounmap;
735 }
736 clk_enable(host->clk);
737
738 mxcmci_softreset(host);
739
740 host->rev_no = readw(host->base + MMC_REG_REV_NO);
741 if (host->rev_no != 0x400) {
742 ret = -ENODEV;
743 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
744 host->rev_no);
745 goto out_clk_put;
746 }
747
748 mmc->f_min = clk_get_rate(host->clk) >> 16;
749 mmc->f_max = clk_get_rate(host->clk) >> 1;
750
751 /* recommended in data sheet */
752 writew(0x2db4, host->base + MMC_REG_READ_TO);
753
754 writel(0, host->base + MMC_REG_INT_CNTR);
755
756 #ifdef HAS_DMA
757 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
758 if (host->dma < 0) {
759 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
760 ret = -EBUSY;
761 goto out_clk_put;
762 }
763
764 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
765 if (!r) {
766 ret = -EINVAL;
767 goto out_free_dma;
768 }
769
770 ret = imx_dma_config_channel(host->dma,
771 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
772 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
773 r->start, 0);
774 if (ret) {
775 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n");
776 goto out_free_dma;
777 }
778 #endif
779 INIT_WORK(&host->datawork, mxcmci_datawork);
780
781 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
782 if (ret)
783 goto out_free_dma;
784
785 platform_set_drvdata(pdev, mmc);
786
787 if (host->pdata && host->pdata->init) {
788 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
789 host->mmc);
790 if (ret)
791 goto out_free_irq;
792 }
793
794 mmc_add_host(mmc);
795
796 return 0;
797
798 out_free_irq:
799 free_irq(host->irq, host);
800 out_free_dma:
801 #ifdef HAS_DMA
802 imx_dma_free(host->dma);
803 #endif
804 out_clk_put:
805 clk_disable(host->clk);
806 clk_put(host->clk);
807 out_iounmap:
808 iounmap(host->base);
809 out_free:
810 mmc_free_host(mmc);
811 out_release_mem:
812 release_mem_region(host->res->start, resource_size(host->res));
813 return ret;
814 }
815
816 static int mxcmci_remove(struct platform_device *pdev)
817 {
818 struct mmc_host *mmc = platform_get_drvdata(pdev);
819 struct mxcmci_host *host = mmc_priv(mmc);
820
821 platform_set_drvdata(pdev, NULL);
822
823 mmc_remove_host(mmc);
824
825 if (host->pdata && host->pdata->exit)
826 host->pdata->exit(&pdev->dev, mmc);
827
828 free_irq(host->irq, host);
829 iounmap(host->base);
830 #ifdef HAS_DMA
831 imx_dma_free(host->dma);
832 #endif
833 clk_disable(host->clk);
834 clk_put(host->clk);
835
836 release_mem_region(host->res->start, resource_size(host->res));
837 release_resource(host->res);
838
839 mmc_free_host(mmc);
840
841 return 0;
842 }
843
844 #ifdef CONFIG_PM
845 static int mxcmci_suspend(struct platform_device *dev, pm_message_t state)
846 {
847 struct mmc_host *mmc = platform_get_drvdata(dev);
848 int ret = 0;
849
850 if (mmc)
851 ret = mmc_suspend_host(mmc, state);
852
853 return ret;
854 }
855
856 static int mxcmci_resume(struct platform_device *dev)
857 {
858 struct mmc_host *mmc = platform_get_drvdata(dev);
859 struct mxcmci_host *host;
860 int ret = 0;
861
862 if (mmc) {
863 host = mmc_priv(mmc);
864 ret = mmc_resume_host(mmc);
865 }
866
867 return ret;
868 }
869 #else
870 #define mxcmci_suspend NULL
871 #define mxcmci_resume NULL
872 #endif /* CONFIG_PM */
873
874 static struct platform_driver mxcmci_driver = {
875 .probe = mxcmci_probe,
876 .remove = mxcmci_remove,
877 .suspend = mxcmci_suspend,
878 .resume = mxcmci_resume,
879 .driver = {
880 .name = DRIVER_NAME,
881 .owner = THIS_MODULE,
882 }
883 };
884
885 static int __init mxcmci_init(void)
886 {
887 return platform_driver_register(&mxcmci_driver);
888 }
889
890 static void __exit mxcmci_exit(void)
891 {
892 platform_driver_unregister(&mxcmci_driver);
893 }
894
895 module_init(mxcmci_init);
896 module_exit(mxcmci_exit);
897
898 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
899 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
900 MODULE_LICENSE("GPL");
901 MODULE_ALIAS("platform:imx-mmc");
Verdex Pro support