?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / b44.c
blobe046943ef29dc6c9243bb84ad0c5ab5fcdde19bf
1 /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
2 *
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
5 * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
6 * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
7 * Copyright (C) 2006 Broadcom Corporation.
8 * Copyright (C) 2007 Michael Buesch <mb@bu3sch.de>
9 *
10 * Distribute under GPL.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/types.h>
17 #include <linux/netdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/mii.h>
20 #include <linux/if_ether.h>
21 #include <linux/if_vlan.h>
22 #include <linux/etherdevice.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ssb/ssb.h>
28
29 #include <asm/uaccess.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32
33
34 #include "b44.h"
35
36 #define DRV_MODULE_NAME "b44"
37 #define PFX DRV_MODULE_NAME ": "
38 #define DRV_MODULE_VERSION "2.0"
39
40 #define B44_DEF_MSG_ENABLE \
41 (NETIF_MSG_DRV | \
42 NETIF_MSG_PROBE | \
43 NETIF_MSG_LINK | \
44 NETIF_MSG_TIMER | \
45 NETIF_MSG_IFDOWN | \
46 NETIF_MSG_IFUP | \
47 NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR)
49
50 /* length of time before we decide the hardware is borked,
51 * and dev->tx_timeout() should be called to fix the problem
52 */
53 #define B44_TX_TIMEOUT (5 * HZ)
54
55 /* hardware minimum and maximum for a single frame's data payload */
56 #define B44_MIN_MTU 60
57 #define B44_MAX_MTU 1500
58
59 #define B44_RX_RING_SIZE 512
60 #define B44_DEF_RX_RING_PENDING 200
61 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
62 B44_RX_RING_SIZE)
63 #define B44_TX_RING_SIZE 512
64 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
65 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
66 B44_TX_RING_SIZE)
67
68 #define TX_RING_GAP(BP) \
69 (B44_TX_RING_SIZE - (BP)->tx_pending)
70 #define TX_BUFFS_AVAIL(BP) \
71 (((BP)->tx_cons <= (BP)->tx_prod) ? \
72 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
73 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
74 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
75
76 #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
77 #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
78
79 /* minimum number of free TX descriptors required to wake up TX process */
80 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
81
82 /* b44 internal pattern match filter info */
83 #define B44_PATTERN_BASE 0x400
84 #define B44_PATTERN_SIZE 0x80
85 #define B44_PMASK_BASE 0x600
86 #define B44_PMASK_SIZE 0x10
87 #define B44_MAX_PATTERNS 16
88 #define B44_ETHIPV6UDP_HLEN 62
89 #define B44_ETHIPV4UDP_HLEN 42
90
91 static char version[] __devinitdata =
92 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION "\n";
93
94 MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
95 MODULE_DESCRIPTION("Broadcom 44xx/47xx 10/100 PCI ethernet driver");
96 MODULE_LICENSE("GPL");
97 MODULE_VERSION(DRV_MODULE_VERSION);
98
99 static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
100 module_param(b44_debug, int, 0);
101 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
102
103
104 #ifdef CONFIG_B44_PCI
105 static const struct pci_device_id b44_pci_tbl[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
107 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
108 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
109 { 0 } /* terminate list with empty entry */
110 };
111 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
112
113 static struct pci_driver b44_pci_driver = {
114 .name = DRV_MODULE_NAME,
115 .id_table = b44_pci_tbl,
116 };
117 #endif /* CONFIG_B44_PCI */
118
119 static const struct ssb_device_id b44_ssb_tbl[] = {
120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
121 SSB_DEVTABLE_END
122 };
123 MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
124
125 static void b44_halt(struct b44 *);
126 static void b44_init_rings(struct b44 *);
127
128 #define B44_FULL_RESET 1
129 #define B44_FULL_RESET_SKIP_PHY 2
130 #define B44_PARTIAL_RESET 3
131 #define B44_CHIP_RESET_FULL 4
132 #define B44_CHIP_RESET_PARTIAL 5
133
134 static void b44_init_hw(struct b44 *, int);
135
136 static int dma_desc_align_mask;
137 static int dma_desc_sync_size;
138 static int instance;
139
140 static const char b44_gstrings[][ETH_GSTRING_LEN] = {
141 #define _B44(x...) # x,
142 B44_STAT_REG_DECLARE
143 #undef _B44
144 };
145
146 static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
147 dma_addr_t dma_base,
148 unsigned long offset,
149 enum dma_data_direction dir)
150 {
151 ssb_dma_sync_single_range_for_device(sdev, dma_base,
152 offset & dma_desc_align_mask,
153 dma_desc_sync_size, dir);
154 }
155
156 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
157 dma_addr_t dma_base,
158 unsigned long offset,
159 enum dma_data_direction dir)
160 {
161 ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
162 offset & dma_desc_align_mask,
163 dma_desc_sync_size, dir);
164 }
165
166 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
167 {
168 return ssb_read32(bp->sdev, reg);
169 }
170
171 static inline void bw32(const struct b44 *bp,
172 unsigned long reg, unsigned long val)
173 {
174 ssb_write32(bp->sdev, reg, val);
175 }
176
177 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
178 u32 bit, unsigned long timeout, const int clear)
179 {
180 unsigned long i;
181
182 for (i = 0; i < timeout; i++) {
183 u32 val = br32(bp, reg);
184
185 if (clear && !(val & bit))
186 break;
187 if (!clear && (val & bit))
188 break;
189 udelay(10);
190 }
191 if (i == timeout) {
192 printk(KERN_ERR PFX "%s: BUG! Timeout waiting for bit %08x of register "
193 "%lx to %s.\n",
194 bp->dev->name,
195 bit, reg,
196 (clear ? "clear" : "set"));
197 return -ENODEV;
198 }
199 return 0;
200 }
201
202 static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
203 {
204 u32 val;
205
206 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
207 (index << CAM_CTRL_INDEX_SHIFT)));
208
209 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
210
211 val = br32(bp, B44_CAM_DATA_LO);
212
213 data[2] = (val >> 24) & 0xFF;
214 data[3] = (val >> 16) & 0xFF;
215 data[4] = (val >> 8) & 0xFF;
216 data[5] = (val >> 0) & 0xFF;
217
218 val = br32(bp, B44_CAM_DATA_HI);
219
220 data[0] = (val >> 8) & 0xFF;
221 data[1] = (val >> 0) & 0xFF;
222 }
223
224 static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
225 {
226 u32 val;
227
228 val = ((u32) data[2]) << 24;
229 val |= ((u32) data[3]) << 16;
230 val |= ((u32) data[4]) << 8;
231 val |= ((u32) data[5]) << 0;
232 bw32(bp, B44_CAM_DATA_LO, val);
233 val = (CAM_DATA_HI_VALID |
234 (((u32) data[0]) << 8) |
235 (((u32) data[1]) << 0));
236 bw32(bp, B44_CAM_DATA_HI, val);
237 bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
238 (index << CAM_CTRL_INDEX_SHIFT)));
239 b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
240 }
241
242 static inline void __b44_disable_ints(struct b44 *bp)
243 {
244 bw32(bp, B44_IMASK, 0);
245 }
246
247 static void b44_disable_ints(struct b44 *bp)
248 {
249 __b44_disable_ints(bp);
250
251 /* Flush posted writes. */
252 br32(bp, B44_IMASK);
253 }
254
255 static void b44_enable_ints(struct b44 *bp)
256 {
257 bw32(bp, B44_IMASK, bp->imask);
258 }
259
260 static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
261 {
262 int err;
263
264 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
265 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
266 (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
267 (phy_addr << MDIO_DATA_PMD_SHIFT) |
268 (reg << MDIO_DATA_RA_SHIFT) |
269 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
270 err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
271 *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
272
273 return err;
274 }
275
276 static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
277 {
278 bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
279 bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
280 (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
281 (phy_addr << MDIO_DATA_PMD_SHIFT) |
282 (reg << MDIO_DATA_RA_SHIFT) |
283 (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
284 (val & MDIO_DATA_DATA)));
285 return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
286 }
287
288 static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
289 {
290 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
291 return 0;
292
293 return __b44_readphy(bp, bp->phy_addr, reg, val);
294 }
295
296 static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
297 {
298 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
299 return 0;
300
301 return __b44_writephy(bp, bp->phy_addr, reg, val);
302 }
303
304 /* miilib interface */
305 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
306 {
307 u32 val;
308 struct b44 *bp = netdev_priv(dev);
309 int rc = __b44_readphy(bp, phy_id, location, &val);
310 if (rc)
311 return 0xffffffff;
312 return val;
313 }
314
315 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
316 int val)
317 {
318 struct b44 *bp = netdev_priv(dev);
319 __b44_writephy(bp, phy_id, location, val);
320 }
321
322 static int b44_phy_reset(struct b44 *bp)
323 {
324 u32 val;
325 int err;
326
327 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
328 return 0;
329 err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
330 if (err)
331 return err;
332 udelay(100);
333 err = b44_readphy(bp, MII_BMCR, &val);
334 if (!err) {
335 if (val & BMCR_RESET) {
336 printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
337 bp->dev->name);
338 err = -ENODEV;
339 }
340 }
341
342 return 0;
343 }
344
345 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
346 {
347 u32 val;
348
349 bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
350 bp->flags |= pause_flags;
351
352 val = br32(bp, B44_RXCONFIG);
353 if (pause_flags & B44_FLAG_RX_PAUSE)
354 val |= RXCONFIG_FLOW;
355 else
356 val &= ~RXCONFIG_FLOW;
357 bw32(bp, B44_RXCONFIG, val);
358
359 val = br32(bp, B44_MAC_FLOW);
360 if (pause_flags & B44_FLAG_TX_PAUSE)
361 val |= (MAC_FLOW_PAUSE_ENAB |
362 (0xc0 & MAC_FLOW_RX_HI_WATER));
363 else
364 val &= ~MAC_FLOW_PAUSE_ENAB;
365 bw32(bp, B44_MAC_FLOW, val);
366 }
367
368 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
369 {
370 u32 pause_enab = 0;
371
372 /* The driver supports only rx pause by default because
373 the b44 mac tx pause mechanism generates excessive
374 pause frames.
375 Use ethtool to turn on b44 tx pause if necessary.
376 */
377 if ((local & ADVERTISE_PAUSE_CAP) &&
378 (local & ADVERTISE_PAUSE_ASYM)){
379 if ((remote & LPA_PAUSE_ASYM) &&
380 !(remote & LPA_PAUSE_CAP))
381 pause_enab |= B44_FLAG_RX_PAUSE;
382 }
383
384 __b44_set_flow_ctrl(bp, pause_enab);
385 }
386
387 #ifdef SSB_DRIVER_MIPS
388 extern char *nvram_get(char *name);
389 static void b44_wap54g10_workaround(struct b44 *bp)
390 {
391 const char *str;
392 u32 val;
393 int err;
394
395 /*
396 * workaround for bad hardware design in Linksys WAP54G v1.0
397 * see https://dev.openwrt.org/ticket/146
398 * check and reset bit "isolate"
399 */
400 str = nvram_get("boardnum");
401 if (!str)
402 return;
403 if (simple_strtoul(str, NULL, 0) == 2) {
404 err = __b44_readphy(bp, 0, MII_BMCR, &val);
405 if (err)
406 goto error;
407 if (!(val & BMCR_ISOLATE))
408 return;
409 val &= ~BMCR_ISOLATE;
410 err = __b44_writephy(bp, 0, MII_BMCR, val);
411 if (err)
412 goto error;
413 }
414 return;
415 error:
416 printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
417 }
418 #else
419 static inline void b44_wap54g10_workaround(struct b44 *bp)
420 {
421 }
422 #endif
423
424 static int b44_setup_phy(struct b44 *bp)
425 {
426 u32 val;
427 int err;
428
429 b44_wap54g10_workaround(bp);
430
431 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
432 return 0;
433 if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
434 goto out;
435 if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
436 val & MII_ALEDCTRL_ALLMSK)) != 0)
437 goto out;
438 if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
439 goto out;
440 if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
441 val | MII_TLEDCTRL_ENABLE)) != 0)
442 goto out;
443
444 if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
445 u32 adv = ADVERTISE_CSMA;
446
447 if (bp->flags & B44_FLAG_ADV_10HALF)
448 adv |= ADVERTISE_10HALF;
449 if (bp->flags & B44_FLAG_ADV_10FULL)
450 adv |= ADVERTISE_10FULL;
451 if (bp->flags & B44_FLAG_ADV_100HALF)
452 adv |= ADVERTISE_100HALF;
453 if (bp->flags & B44_FLAG_ADV_100FULL)
454 adv |= ADVERTISE_100FULL;
455
456 if (bp->flags & B44_FLAG_PAUSE_AUTO)
457 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
458
459 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
460 goto out;
461 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
462 BMCR_ANRESTART))) != 0)
463 goto out;
464 } else {
465 u32 bmcr;
466
467 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
468 goto out;
469 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
470 if (bp->flags & B44_FLAG_100_BASE_T)
471 bmcr |= BMCR_SPEED100;
472 if (bp->flags & B44_FLAG_FULL_DUPLEX)
473 bmcr |= BMCR_FULLDPLX;
474 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
475 goto out;
476
477 /* Since we will not be negotiating there is no safe way
478 * to determine if the link partner supports flow control
479 * or not. So just disable it completely in this case.
480 */
481 b44_set_flow_ctrl(bp, 0, 0);
482 }
483
484 out:
485 return err;
486 }
487
488 static void b44_stats_update(struct b44 *bp)
489 {
490 unsigned long reg;
491 u32 *val;
492
493 val = &bp->hw_stats.tx_good_octets;
494 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
495 *val++ += br32(bp, reg);
496 }
497
498 /* Pad */
499 reg += 8*4UL;
500
501 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
502 *val++ += br32(bp, reg);
503 }
504 }
505
506 static void b44_link_report(struct b44 *bp)
507 {
508 if (!netif_carrier_ok(bp->dev)) {
509 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
510 } else {
511 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
512 bp->dev->name,
513 (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
514 (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
515
516 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
517 "%s for RX.\n",
518 bp->dev->name,
519 (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
520 (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
521 }
522 }
523
524 static void b44_check_phy(struct b44 *bp)
525 {
526 u32 bmsr, aux;
527
528 if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
529 bp->flags |= B44_FLAG_100_BASE_T;
530 bp->flags |= B44_FLAG_FULL_DUPLEX;
531 if (!netif_carrier_ok(bp->dev)) {
532 u32 val = br32(bp, B44_TX_CTRL);
533 val |= TX_CTRL_DUPLEX;
534 bw32(bp, B44_TX_CTRL, val);
535 netif_carrier_on(bp->dev);
536 b44_link_report(bp);
537 }
538 return;
539 }
540
541 if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
542 !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
543 (bmsr != 0xffff)) {
544 if (aux & MII_AUXCTRL_SPEED)
545 bp->flags |= B44_FLAG_100_BASE_T;
546 else
547 bp->flags &= ~B44_FLAG_100_BASE_T;
548 if (aux & MII_AUXCTRL_DUPLEX)
549 bp->flags |= B44_FLAG_FULL_DUPLEX;
550 else
551 bp->flags &= ~B44_FLAG_FULL_DUPLEX;
552
553 if (!netif_carrier_ok(bp->dev) &&
554 (bmsr & BMSR_LSTATUS)) {
555 u32 val = br32(bp, B44_TX_CTRL);
556 u32 local_adv, remote_adv;
557
558 if (bp->flags & B44_FLAG_FULL_DUPLEX)
559 val |= TX_CTRL_DUPLEX;
560 else
561 val &= ~TX_CTRL_DUPLEX;
562 bw32(bp, B44_TX_CTRL, val);
563
564 if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
565 !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
566 !b44_readphy(bp, MII_LPA, &remote_adv))
567 b44_set_flow_ctrl(bp, local_adv, remote_adv);
568
569 /* Link now up */
570 netif_carrier_on(bp->dev);
571 b44_link_report(bp);
572 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
573 /* Link now down */
574 netif_carrier_off(bp->dev);
575 b44_link_report(bp);
576 }
577
578 if (bmsr & BMSR_RFAULT)
579 printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
580 bp->dev->name);
581 if (bmsr & BMSR_JCD)
582 printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
583 bp->dev->name);
584 }
585 }
586
587 static void b44_timer(unsigned long __opaque)
588 {
589 struct b44 *bp = (struct b44 *) __opaque;
590
591 spin_lock_irq(&bp->lock);
592
593 b44_check_phy(bp);
594
595 b44_stats_update(bp);
596
597 spin_unlock_irq(&bp->lock);
598
599 mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
600 }
601
602 static void b44_tx(struct b44 *bp)
603 {
604 u32 cur, cons;
605
606 cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
607 cur /= sizeof(struct dma_desc);
608
609 /* XXX needs updating when NETIF_F_SG is supported */
610 for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
611 struct ring_info *rp = &bp->tx_buffers[cons];
612 struct sk_buff *skb = rp->skb;
613
614 BUG_ON(skb == NULL);
615
616 ssb_dma_unmap_single(bp->sdev,
617 rp->mapping,
618 skb->len,
619 DMA_TO_DEVICE);
620 rp->skb = NULL;
621 dev_kfree_skb_irq(skb);
622 }
623
624 bp->tx_cons = cons;
625 if (netif_queue_stopped(bp->dev) &&
626 TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
627 netif_wake_queue(bp->dev);
628
629 bw32(bp, B44_GPTIMER, 0);
630 }
631
632 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
633 * before the DMA address you give it. So we allocate 30 more bytes
634 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
635 * point the chip at 30 bytes past where the rx_header will go.
636 */
637 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
638 {
639 struct dma_desc *dp;
640 struct ring_info *src_map, *map;
641 struct rx_header *rh;
642 struct sk_buff *skb;
643 dma_addr_t mapping;
644 int dest_idx;
645 u32 ctrl;
646
647 src_map = NULL;
648 if (src_idx >= 0)
649 src_map = &bp->rx_buffers[src_idx];
650 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
651 map = &bp->rx_buffers[dest_idx];
652 skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
653 if (skb == NULL)
654 return -ENOMEM;
655
656 mapping = ssb_dma_map_single(bp->sdev, skb->data,
657 RX_PKT_BUF_SZ,
658 DMA_FROM_DEVICE);
659
660 /* Hardware bug work-around, the chip is unable to do PCI DMA
661 to/from anything above 1GB :-( */
662 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
663 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
664 /* Sigh... */
665 if (!ssb_dma_mapping_error(bp->sdev, mapping))
666 ssb_dma_unmap_single(bp->sdev, mapping,
667 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
668 dev_kfree_skb_any(skb);
669 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
670 if (skb == NULL)
671 return -ENOMEM;
672 mapping = ssb_dma_map_single(bp->sdev, skb->data,
673 RX_PKT_BUF_SZ,
674 DMA_FROM_DEVICE);
675 if (ssb_dma_mapping_error(bp->sdev, mapping) ||
676 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
677 if (!ssb_dma_mapping_error(bp->sdev, mapping))
678 ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
679 dev_kfree_skb_any(skb);
680 return -ENOMEM;
681 }
682 bp->force_copybreak = 1;
683 }
684
685 rh = (struct rx_header *) skb->data;
686
687 rh->len = 0;
688 rh->flags = 0;
689
690 map->skb = skb;
691 map->mapping = mapping;
692
693 if (src_map != NULL)
694 src_map->skb = NULL;
695
696 ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
697 if (dest_idx == (B44_RX_RING_SIZE - 1))
698 ctrl |= DESC_CTRL_EOT;
699
700 dp = &bp->rx_ring[dest_idx];
701 dp->ctrl = cpu_to_le32(ctrl);
702 dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
703
704 if (bp->flags & B44_FLAG_RX_RING_HACK)
705 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
706 dest_idx * sizeof(*dp),
707 DMA_BIDIRECTIONAL);
708
709 return RX_PKT_BUF_SZ;
710 }
711
712 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
713 {
714 struct dma_desc *src_desc, *dest_desc;
715 struct ring_info *src_map, *dest_map;
716 struct rx_header *rh;
717 int dest_idx;
718 __le32 ctrl;
719
720 dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
721 dest_desc = &bp->rx_ring[dest_idx];
722 dest_map = &bp->rx_buffers[dest_idx];
723 src_desc = &bp->rx_ring[src_idx];
724 src_map = &bp->rx_buffers[src_idx];
725
726 dest_map->skb = src_map->skb;
727 rh = (struct rx_header *) src_map->skb->data;
728 rh->len = 0;
729 rh->flags = 0;
730 dest_map->mapping = src_map->mapping;
731
732 if (bp->flags & B44_FLAG_RX_RING_HACK)
733 b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
734 src_idx * sizeof(*src_desc),
735 DMA_BIDIRECTIONAL);
736
737 ctrl = src_desc->ctrl;
738 if (dest_idx == (B44_RX_RING_SIZE - 1))
739 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
740 else
741 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
742
743 dest_desc->ctrl = ctrl;
744 dest_desc->addr = src_desc->addr;
745
746 src_map->skb = NULL;
747
748 if (bp->flags & B44_FLAG_RX_RING_HACK)
749 b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
750 dest_idx * sizeof(*dest_desc),
751 DMA_BIDIRECTIONAL);
752
753 ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
754 RX_PKT_BUF_SZ,
755 DMA_FROM_DEVICE);
756 }
757
758 static int b44_rx(struct b44 *bp, int budget)
759 {
760 int received;
761 u32 cons, prod;
762
763 received = 0;
764 prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
765 prod /= sizeof(struct dma_desc);
766 cons = bp->rx_cons;
767
768 while (cons != prod && budget > 0) {
769 struct ring_info *rp = &bp->rx_buffers[cons];
770 struct sk_buff *skb = rp->skb;
771 dma_addr_t map = rp->mapping;
772 struct rx_header *rh;
773 u16 len;
774
775 ssb_dma_sync_single_for_cpu(bp->sdev, map,
776 RX_PKT_BUF_SZ,
777 DMA_FROM_DEVICE);
778 rh = (struct rx_header *) skb->data;
779 len = le16_to_cpu(rh->len);
780 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
781 (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
782 drop_it:
783 b44_recycle_rx(bp, cons, bp->rx_prod);
784 drop_it_no_recycle:
785 bp->dev->stats.rx_dropped++;
786 goto next_pkt;
787 }
788
789 if (len == 0) {
790 int i = 0;
791
792 do {
793 udelay(2);
794 barrier();
795 len = le16_to_cpu(rh->len);
796 } while (len == 0 && i++ < 5);
797 if (len == 0)
798 goto drop_it;
799 }
800
801 /* Omit CRC. */
802 len -= 4;
803
804 if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
805 int skb_size;
806 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
807 if (skb_size < 0)
808 goto drop_it;
809 ssb_dma_unmap_single(bp->sdev, map,
810 skb_size, DMA_FROM_DEVICE);
811 /* Leave out rx_header */
812 skb_put(skb, len + RX_PKT_OFFSET);
813 skb_pull(skb, RX_PKT_OFFSET);
814 } else {
815 struct sk_buff *copy_skb;
816
817 b44_recycle_rx(bp, cons, bp->rx_prod);
818 copy_skb = dev_alloc_skb(len + 2);
819 if (copy_skb == NULL)
820 goto drop_it_no_recycle;
821
822 skb_reserve(copy_skb, 2);
823 skb_put(copy_skb, len);
824 /* DMA sync done above, copy just the actual packet */
825 skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
826 copy_skb->data, len);
827 skb = copy_skb;
828 }
829 skb->ip_summed = CHECKSUM_NONE;
830 skb->protocol = eth_type_trans(skb, bp->dev);
831 netif_receive_skb(skb);
832 received++;
833 budget--;
834 next_pkt:
835 bp->rx_prod = (bp->rx_prod + 1) &
836 (B44_RX_RING_SIZE - 1);
837 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
838 }
839
840 bp->rx_cons = cons;
841 bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
842
843 return received;
844 }
845
846 static int b44_poll(struct napi_struct *napi, int budget)
847 {
848 struct b44 *bp = container_of(napi, struct b44, napi);
849 int work_done;
850 unsigned long flags;
851
852 spin_lock_irqsave(&bp->lock, flags);
853
854 if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
855 /* spin_lock(&bp->tx_lock); */
856 b44_tx(bp);
857 /* spin_unlock(&bp->tx_lock); */
858 }
859 spin_unlock_irqrestore(&bp->lock, flags);
860
861 work_done = 0;
862 if (bp->istat & ISTAT_RX)
863 work_done += b44_rx(bp, budget);
864
865 if (bp->istat & ISTAT_ERRORS) {
866 spin_lock_irqsave(&bp->lock, flags);
867 b44_halt(bp);
868 b44_init_rings(bp);
869 b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
870 netif_wake_queue(bp->dev);
871 spin_unlock_irqrestore(&bp->lock, flags);
872 work_done = 0;
873 }
874
875 if (work_done < budget) {
876 napi_complete(napi);
877 b44_enable_ints(bp);
878 }
879
880 return work_done;
881 }
882
883 static irqreturn_t b44_interrupt(int irq, void *dev_id)
884 {
885 struct net_device *dev = dev_id;
886 struct b44 *bp = netdev_priv(dev);
887 u32 istat, imask;
888 int handled = 0;
889
890 spin_lock(&bp->lock);
891
892 istat = br32(bp, B44_ISTAT);
893 imask = br32(bp, B44_IMASK);
894
895 /* The interrupt mask register controls which interrupt bits
896 * will actually raise an interrupt to the CPU when set by hw/firmware,
897 * but doesn't mask off the bits.
898 */
899 istat &= imask;
900 if (istat) {
901 handled = 1;
902
903 if (unlikely(!netif_running(dev))) {
904 printk(KERN_INFO "%s: late interrupt.\n", dev->name);
905 goto irq_ack;
906 }
907
908 if (napi_schedule_prep(&bp->napi)) {
909 /* NOTE: These writes are posted by the readback of
910 * the ISTAT register below.
911 */
912 bp->istat = istat;
913 __b44_disable_ints(bp);
914 __napi_schedule(&bp->napi);
915 } else {
916 printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
917 dev->name);
918 }
919
920 irq_ack:
921 bw32(bp, B44_ISTAT, istat);
922 br32(bp, B44_ISTAT);
923 }
924 spin_unlock(&bp->lock);
925 return IRQ_RETVAL(handled);
926 }
927
928 static void b44_tx_timeout(struct net_device *dev)
929 {
930 struct b44 *bp = netdev_priv(dev);
931
932 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
933 dev->name);
934
935 spin_lock_irq(&bp->lock);
936
937 b44_halt(bp);
938 b44_init_rings(bp);
939 b44_init_hw(bp, B44_FULL_RESET);
940
941 spin_unlock_irq(&bp->lock);
942
943 b44_enable_ints(bp);
944
945 netif_wake_queue(dev);
946 }
947
948 static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
949 {
950 struct b44 *bp = netdev_priv(dev);
951 int rc = NETDEV_TX_OK;
952 dma_addr_t mapping;
953 u32 len, entry, ctrl;
954 unsigned long flags;
955
956 len = skb->len;
957 spin_lock_irqsave(&bp->lock, flags);
958
959 /* This is a hard error, log it. */
960 if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
961 netif_stop_queue(dev);
962 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
963 dev->name);
964 goto err_out;
965 }
966
967 mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
968 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
969 struct sk_buff *bounce_skb;
970
971 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
972 if (!ssb_dma_mapping_error(bp->sdev, mapping))
973 ssb_dma_unmap_single(bp->sdev, mapping, len,
974 DMA_TO_DEVICE);
975
976 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
977 if (!bounce_skb)
978 goto err_out;
979
980 mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
981 len, DMA_TO_DEVICE);
982 if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
983 if (!ssb_dma_mapping_error(bp->sdev, mapping))
984 ssb_dma_unmap_single(bp->sdev, mapping,
985 len, DMA_TO_DEVICE);
986 dev_kfree_skb_any(bounce_skb);
987 goto err_out;
988 }
989
990 skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
991 dev_kfree_skb_any(skb);
992 skb = bounce_skb;
993 }
994
995 entry = bp->tx_prod;
996 bp->tx_buffers[entry].skb = skb;
997 bp->tx_buffers[entry].mapping = mapping;
998
999 ctrl = (len & DESC_CTRL_LEN);
1000 ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
1001 if (entry == (B44_TX_RING_SIZE - 1))
1002 ctrl |= DESC_CTRL_EOT;
1003
1004 bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
1005 bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
1006
1007 if (bp->flags & B44_FLAG_TX_RING_HACK)
1008 b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
1009 entry * sizeof(bp->tx_ring[0]),
1010 DMA_TO_DEVICE);
1011
1012 entry = NEXT_TX(entry);
1013
1014 bp->tx_prod = entry;
1015
1016 wmb();
1017
1018 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1019 if (bp->flags & B44_FLAG_BUGGY_TXPTR)
1020 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
1021 if (bp->flags & B44_FLAG_REORDER_BUG)
1022 br32(bp, B44_DMATX_PTR);
1023
1024 if (TX_BUFFS_AVAIL(bp) < 1)
1025 netif_stop_queue(dev);
1026
1027 dev->trans_start = jiffies;
1028
1029 out_unlock:
1030 spin_unlock_irqrestore(&bp->lock, flags);
1031
1032 return rc;
1033
1034 err_out:
1035 rc = NETDEV_TX_BUSY;
1036 goto out_unlock;
1037 }
1038
1039 static int b44_change_mtu(struct net_device *dev, int new_mtu)
1040 {
1041 struct b44 *bp = netdev_priv(dev);
1042
1043 if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
1044 return -EINVAL;
1045
1046 if (!netif_running(dev)) {
1047 /* We'll just catch it later when the
1048 * device is up'd.
1049 */
1050 dev->mtu = new_mtu;
1051 return 0;
1052 }
1053
1054 spin_lock_irq(&bp->lock);
1055 b44_halt(bp);
1056 dev->mtu = new_mtu;
1057 b44_init_rings(bp);
1058 b44_init_hw(bp, B44_FULL_RESET);
1059 spin_unlock_irq(&bp->lock);
1060
1061 b44_enable_ints(bp);
1062
1063 return 0;
1064 }
1065
1066 /* Free up pending packets in all rx/tx rings.
1067 *
1068 * The chip has been shut down and the driver detached from
1069 * the networking, so no interrupts or new tx packets will
1070 * end up in the driver. bp->lock is not held and we are not
1071 * in an interrupt context and thus may sleep.
1072 */
1073 static void b44_free_rings(struct b44 *bp)
1074 {
1075 struct ring_info *rp;
1076 int i;
1077
1078 for (i = 0; i < B44_RX_RING_SIZE; i++) {
1079 rp = &bp->rx_buffers[i];
1080
1081 if (rp->skb == NULL)
1082 continue;
1083 ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
1084 DMA_FROM_DEVICE);
1085 dev_kfree_skb_any(rp->skb);
1086 rp->skb = NULL;
1087 }
1088
1089 /* XXX needs changes once NETIF_F_SG is set... */
1090 for (i = 0; i < B44_TX_RING_SIZE; i++) {
1091 rp = &bp->tx_buffers[i];
1092
1093 if (rp->skb == NULL)
1094 continue;
1095 ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
1096 DMA_TO_DEVICE);
1097 dev_kfree_skb_any(rp->skb);
1098 rp->skb = NULL;
1099 }
1100 }
1101
1102 /* Initialize tx/rx rings for packet processing.
1103 *
1104 * The chip has been shut down and the driver detached from
1105 * the networking, so no interrupts or new tx packets will
1106 * end up in the driver.
1107 */
1108 static void b44_init_rings(struct b44 *bp)
1109 {
1110 int i;
1111
1112 b44_free_rings(bp);
1113
1114 memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1115 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1116
1117 if (bp->flags & B44_FLAG_RX_RING_HACK)
1118 ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
1119 DMA_TABLE_BYTES,
1120 DMA_BIDIRECTIONAL);
1121
1122 if (bp->flags & B44_FLAG_TX_RING_HACK)
1123 ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
1124 DMA_TABLE_BYTES,
1125 DMA_TO_DEVICE);
1126
1127 for (i = 0; i < bp->rx_pending; i++) {
1128 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1129 break;
1130 }
1131 }
1132
1133 /*
1134 * Must not be invoked with interrupt sources disabled and
1135 * the hardware shutdown down.
1136 */
1137 static void b44_free_consistent(struct b44 *bp)
1138 {
1139 kfree(bp->rx_buffers);
1140 bp->rx_buffers = NULL;
1141 kfree(bp->tx_buffers);
1142 bp->tx_buffers = NULL;
1143 if (bp->rx_ring) {
1144 if (bp->flags & B44_FLAG_RX_RING_HACK) {
1145 ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
1146 DMA_TABLE_BYTES,
1147 DMA_BIDIRECTIONAL);
1148 kfree(bp->rx_ring);
1149 } else
1150 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1151 bp->rx_ring, bp->rx_ring_dma,
1152 GFP_KERNEL);
1153 bp->rx_ring = NULL;
1154 bp->flags &= ~B44_FLAG_RX_RING_HACK;
1155 }
1156 if (bp->tx_ring) {
1157 if (bp->flags & B44_FLAG_TX_RING_HACK) {
1158 ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
1159 DMA_TABLE_BYTES,
1160 DMA_TO_DEVICE);
1161 kfree(bp->tx_ring);
1162 } else
1163 ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
1164 bp->tx_ring, bp->tx_ring_dma,
1165 GFP_KERNEL);
1166 bp->tx_ring = NULL;
1167 bp->flags &= ~B44_FLAG_TX_RING_HACK;
1168 }
1169 }
1170
1171 /*
1172 * Must not be invoked with interrupt sources disabled and
1173 * the hardware shutdown down. Can sleep.
1174 */
1175 static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
1176 {
1177 int size;
1178
1179 size = B44_RX_RING_SIZE * sizeof(struct ring_info);
1180 bp->rx_buffers = kzalloc(size, gfp);
1181 if (!bp->rx_buffers)
1182 goto out_err;
1183
1184 size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1185 bp->tx_buffers = kzalloc(size, gfp);
1186 if (!bp->tx_buffers)
1187 goto out_err;
1188
1189 size = DMA_TABLE_BYTES;
1190 bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
1191 if (!bp->rx_ring) {
1192 /* Allocation may have failed due to pci_alloc_consistent
1193 insisting on use of GFP_DMA, which is more restrictive
1194 than necessary... */
1195 struct dma_desc *rx_ring;
1196 dma_addr_t rx_ring_dma;
1197
1198 rx_ring = kzalloc(size, gfp);
1199 if (!rx_ring)
1200 goto out_err;
1201
1202 rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
1203 DMA_TABLE_BYTES,
1204 DMA_BIDIRECTIONAL);
1205
1206 if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
1207 rx_ring_dma + size > DMA_BIT_MASK(30)) {
1208 kfree(rx_ring);
1209 goto out_err;
1210 }
1211
1212 bp->rx_ring = rx_ring;
1213 bp->rx_ring_dma = rx_ring_dma;
1214 bp->flags |= B44_FLAG_RX_RING_HACK;
1215 }
1216
1217 bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
1218 if (!bp->tx_ring) {
1219 /* Allocation may have failed due to ssb_dma_alloc_consistent
1220 insisting on use of GFP_DMA, which is more restrictive
1221 than necessary... */
1222 struct dma_desc *tx_ring;
1223 dma_addr_t tx_ring_dma;
1224
1225 tx_ring = kzalloc(size, gfp);
1226 if (!tx_ring)
1227 goto out_err;
1228
1229 tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
1230 DMA_TABLE_BYTES,
1231 DMA_TO_DEVICE);
1232
1233 if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
1234 tx_ring_dma + size > DMA_BIT_MASK(30)) {
1235 kfree(tx_ring);
1236 goto out_err;
1237 }
1238
1239 bp->tx_ring = tx_ring;
1240 bp->tx_ring_dma = tx_ring_dma;
1241 bp->flags |= B44_FLAG_TX_RING_HACK;
1242 }
1243
1244 return 0;
1245
1246 out_err:
1247 b44_free_consistent(bp);
1248 return -ENOMEM;
1249 }
1250
1251 /* bp->lock is held. */
1252 static void b44_clear_stats(struct b44 *bp)
1253 {
1254 unsigned long reg;
1255
1256 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1257 for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1258 br32(bp, reg);
1259 for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1260 br32(bp, reg);
1261 }
1262
1263 /* bp->lock is held. */
1264 static void b44_chip_reset(struct b44 *bp, int reset_kind)
1265 {
1266 struct ssb_device *sdev = bp->sdev;
1267 bool was_enabled;
1268
1269 was_enabled = ssb_device_is_enabled(bp->sdev);
1270
1271 ssb_device_enable(bp->sdev, 0);
1272 ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
1273
1274 if (was_enabled) {
1275 bw32(bp, B44_RCV_LAZY, 0);
1276 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1277 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
1278 bw32(bp, B44_DMATX_CTRL, 0);
1279 bp->tx_prod = bp->tx_cons = 0;
1280 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1281 b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1282 100, 0);
1283 }
1284 bw32(bp, B44_DMARX_CTRL, 0);
1285 bp->rx_prod = bp->rx_cons = 0;
1286 }
1287
1288 b44_clear_stats(bp);
1289
1290 /*
1291 * Don't enable PHY if we are doing a partial reset
1292 * we are probably going to power down
1293 */
1294 if (reset_kind == B44_CHIP_RESET_PARTIAL)
1295 return;
1296
1297 switch (sdev->bus->bustype) {
1298 case SSB_BUSTYPE_SSB:
1299 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1300 (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
1301 B44_MDC_RATIO)
1302 & MDIO_CTRL_MAXF_MASK)));
1303 break;
1304 case SSB_BUSTYPE_PCI:
1305 bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1306 (0x0d & MDIO_CTRL_MAXF_MASK)));
1307 break;
1308 case SSB_BUSTYPE_PCMCIA:
1309 case SSB_BUSTYPE_SDIO:
1310 WARN_ON(1); /* A device with this bus does not exist. */
1311 break;
1312 }
1313
1314 br32(bp, B44_MDIO_CTRL);
1315
1316 if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1317 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1318 br32(bp, B44_ENET_CTRL);
1319 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1320 } else {
1321 u32 val = br32(bp, B44_DEVCTRL);
1322
1323 if (val & DEVCTRL_EPR) {
1324 bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1325 br32(bp, B44_DEVCTRL);
1326 udelay(100);
1327 }
1328 bp->flags |= B44_FLAG_INTERNAL_PHY;
1329 }
1330 }
1331
1332 /* bp->lock is held. */
1333 static void b44_halt(struct b44 *bp)
1334 {
1335 b44_disable_ints(bp);
1336 /* reset PHY */
1337 b44_phy_reset(bp);
1338 /* power down PHY */
1339 printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
1340 bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
1341 /* now reset the chip, but without enabling the MAC&PHY
1342 * part of it. This has to be done _after_ we shut down the PHY */
1343 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1344 }
1345
1346 /* bp->lock is held. */
1347 static void __b44_set_mac_addr(struct b44 *bp)
1348 {
1349 bw32(bp, B44_CAM_CTRL, 0);
1350 if (!(bp->dev->flags & IFF_PROMISC)) {
1351 u32 val;
1352
1353 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1354 val = br32(bp, B44_CAM_CTRL);
1355 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1356 }
1357 }
1358
1359 static int b44_set_mac_addr(struct net_device *dev, void *p)
1360 {
1361 struct b44 *bp = netdev_priv(dev);
1362 struct sockaddr *addr = p;
1363 u32 val;
1364
1365 if (netif_running(dev))
1366 return -EBUSY;
1367
1368 if (!is_valid_ether_addr(addr->sa_data))
1369 return -EINVAL;
1370
1371 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1372
1373 spin_lock_irq(&bp->lock);
1374
1375 val = br32(bp, B44_RXCONFIG);
1376 if (!(val & RXCONFIG_CAM_ABSENT))
1377 __b44_set_mac_addr(bp);
1378
1379 spin_unlock_irq(&bp->lock);
1380
1381 return 0;
1382 }
1383
1384 /* Called at device open time to get the chip ready for
1385 * packet processing. Invoked with bp->lock held.
1386 */
1387 static void __b44_set_rx_mode(struct net_device *);
1388 static void b44_init_hw(struct b44 *bp, int reset_kind)
1389 {
1390 u32 val;
1391
1392 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
1393 if (reset_kind == B44_FULL_RESET) {
1394 b44_phy_reset(bp);
1395 b44_setup_phy(bp);
1396 }
1397
1398 /* Enable CRC32, set proper LED modes and power on PHY */
1399 bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1400 bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1401
1402 /* This sets the MAC address too. */
1403 __b44_set_rx_mode(bp->dev);
1404
1405 /* MTU + eth header + possible VLAN tag + struct rx_header */
1406 bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1407 bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1408
1409 bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1410 if (reset_kind == B44_PARTIAL_RESET) {
1411 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1412 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1413 } else {
1414 bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1415 bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1416 bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1417 (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
1418 bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1419
1420 bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1421 bp->rx_prod = bp->rx_pending;
1422
1423 bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1424 }
1425
1426 val = br32(bp, B44_ENET_CTRL);
1427 bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1428 }
1429
1430 static int b44_open(struct net_device *dev)
1431 {
1432 struct b44 *bp = netdev_priv(dev);
1433 int err;
1434
1435 err = b44_alloc_consistent(bp, GFP_KERNEL);
1436 if (err)
1437 goto out;
1438
1439 napi_enable(&bp->napi);
1440
1441 b44_init_rings(bp);
1442 b44_init_hw(bp, B44_FULL_RESET);
1443
1444 b44_check_phy(bp);
1445
1446 err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
1447 if (unlikely(err < 0)) {
1448 napi_disable(&bp->napi);
1449 b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
1450 b44_free_rings(bp);
1451 b44_free_consistent(bp);
1452 goto out;
1453 }
1454
1455 init_timer(&bp->timer);
1456 bp->timer.expires = jiffies + HZ;
1457 bp->timer.data = (unsigned long) bp;
1458 bp->timer.function = b44_timer;
1459 add_timer(&bp->timer);
1460
1461 b44_enable_ints(bp);
1462 netif_start_queue(dev);
1463 out:
1464 return err;
1465 }
1466
1467 #ifdef CONFIG_NET_POLL_CONTROLLER
1468 /*
1469 * Polling receive - used by netconsole and other diagnostic tools
1470 * to allow network i/o with interrupts disabled.
1471 */
1472 static void b44_poll_controller(struct net_device *dev)
1473 {
1474 disable_irq(dev->irq);
1475 b44_interrupt(dev->irq, dev);
1476 enable_irq(dev->irq);
1477 }
1478 #endif
1479
1480 static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
1481 {
1482 u32 i;
1483 u32 *pattern = (u32 *) pp;
1484
1485 for (i = 0; i < bytes; i += sizeof(u32)) {
1486 bw32(bp, B44_FILT_ADDR, table_offset + i);
1487 bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
1488 }
1489 }
1490
1491 static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
1492 {
1493 int magicsync = 6;
1494 int k, j, len = offset;
1495 int ethaddr_bytes = ETH_ALEN;
1496
1497 memset(ppattern + offset, 0xff, magicsync);
1498 for (j = 0; j < magicsync; j++)
1499 set_bit(len++, (unsigned long *) pmask);
1500
1501 for (j = 0; j < B44_MAX_PATTERNS; j++) {
1502 if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
1503 ethaddr_bytes = ETH_ALEN;
1504 else
1505 ethaddr_bytes = B44_PATTERN_SIZE - len;
1506 if (ethaddr_bytes <=0)
1507 break;
1508 for (k = 0; k< ethaddr_bytes; k++) {
1509 ppattern[offset + magicsync +
1510 (j * ETH_ALEN) + k] = macaddr[k];
1511 len++;
1512 set_bit(len, (unsigned long *) pmask);
1513 }
1514 }
1515 return len - 1;
1516 }
1517
1518 /* Setup magic packet patterns in the b44 WOL
1519 * pattern matching filter.
1520 */
1521 static void b44_setup_pseudo_magicp(struct b44 *bp)
1522 {
1523
1524 u32 val;
1525 int plen0, plen1, plen2;
1526 u8 *pwol_pattern;
1527 u8 pwol_mask[B44_PMASK_SIZE];
1528
1529 pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
1530 if (!pwol_pattern) {
1531 printk(KERN_ERR PFX "Memory not available for WOL\n");
1532 return;
1533 }
1534
1535 /* Ipv4 magic packet pattern - pattern 0.*/
1536 memset(pwol_mask, 0, B44_PMASK_SIZE);
1537 plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1538 B44_ETHIPV4UDP_HLEN);
1539
1540 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
1541 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
1542
1543 /* Raw ethernet II magic packet pattern - pattern 1 */
1544 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1545 memset(pwol_mask, 0, B44_PMASK_SIZE);
1546 plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1547 ETH_HLEN);
1548
1549 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1550 B44_PATTERN_BASE + B44_PATTERN_SIZE);
1551 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1552 B44_PMASK_BASE + B44_PMASK_SIZE);
1553
1554 /* Ipv6 magic packet pattern - pattern 2 */
1555 memset(pwol_pattern, 0, B44_PATTERN_SIZE);
1556 memset(pwol_mask, 0, B44_PMASK_SIZE);
1557 plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
1558 B44_ETHIPV6UDP_HLEN);
1559
1560 bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
1561 B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
1562 bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
1563 B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
1564
1565 kfree(pwol_pattern);
1566
1567 /* set these pattern's lengths: one less than each real length */
1568 val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
1569 bw32(bp, B44_WKUP_LEN, val);
1570
1571 /* enable wakeup pattern matching */
1572 val = br32(bp, B44_DEVCTRL);
1573 bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
1574
1575 }
1576
1577 #ifdef CONFIG_B44_PCI
1578 static void b44_setup_wol_pci(struct b44 *bp)
1579 {
1580 u16 val;
1581
1582 if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
1583 bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
1584 pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
1585 pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
1586 }
1587 }
1588 #else
1589 static inline void b44_setup_wol_pci(struct b44 *bp) { }
1590 #endif /* CONFIG_B44_PCI */
1591
1592 static void b44_setup_wol(struct b44 *bp)
1593 {
1594 u32 val;
1595
1596 bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
1597
1598 if (bp->flags & B44_FLAG_B0_ANDLATER) {
1599
1600 bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
1601
1602 val = bp->dev->dev_addr[2] << 24 |
1603 bp->dev->dev_addr[3] << 16 |
1604 bp->dev->dev_addr[4] << 8 |
1605 bp->dev->dev_addr[5];
1606 bw32(bp, B44_ADDR_LO, val);
1607
1608 val = bp->dev->dev_addr[0] << 8 |
1609 bp->dev->dev_addr[1];
1610 bw32(bp, B44_ADDR_HI, val);
1611
1612 val = br32(bp, B44_DEVCTRL);
1613 bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
1614
1615 } else {
1616 b44_setup_pseudo_magicp(bp);
1617 }
1618 b44_setup_wol_pci(bp);
1619 }
1620
1621 static int b44_close(struct net_device *dev)
1622 {
1623 struct b44 *bp = netdev_priv(dev);
1624
1625 netif_stop_queue(dev);
1626
1627 napi_disable(&bp->napi);
1628
1629 del_timer_sync(&bp->timer);
1630
1631 spin_lock_irq(&bp->lock);
1632
1633 b44_halt(bp);
1634 b44_free_rings(bp);
1635 netif_carrier_off(dev);
1636
1637 spin_unlock_irq(&bp->lock);
1638
1639 free_irq(dev->irq, dev);
1640
1641 if (bp->flags & B44_FLAG_WOL_ENABLE) {
1642 b44_init_hw(bp, B44_PARTIAL_RESET);
1643 b44_setup_wol(bp);
1644 }
1645
1646 b44_free_consistent(bp);
1647
1648 return 0;
1649 }
1650
1651 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1652 {
1653 struct b44 *bp = netdev_priv(dev);
1654 struct net_device_stats *nstat = &dev->stats;
1655 struct b44_hw_stats *hwstat = &bp->hw_stats;
1656
1657 /* Convert HW stats into netdevice stats. */
1658 nstat->rx_packets = hwstat->rx_pkts;
1659 nstat->tx_packets = hwstat->tx_pkts;
1660 nstat->rx_bytes = hwstat->rx_octets;
1661 nstat->tx_bytes = hwstat->tx_octets;
1662 nstat->tx_errors = (hwstat->tx_jabber_pkts +
1663 hwstat->tx_oversize_pkts +
1664 hwstat->tx_underruns +
1665 hwstat->tx_excessive_cols +
1666 hwstat->tx_late_cols);
1667 nstat->multicast = hwstat->tx_multicast_pkts;
1668 nstat->collisions = hwstat->tx_total_cols;
1669
1670 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1671 hwstat->rx_undersize);
1672 nstat->rx_over_errors = hwstat->rx_missed_pkts;
1673 nstat->rx_frame_errors = hwstat->rx_align_errs;
1674 nstat->rx_crc_errors = hwstat->rx_crc_errs;
1675 nstat->rx_errors = (hwstat->rx_jabber_pkts +
1676 hwstat->rx_oversize_pkts +
1677 hwstat->rx_missed_pkts +
1678 hwstat->rx_crc_align_errs +
1679 hwstat->rx_undersize +
1680 hwstat->rx_crc_errs +
1681 hwstat->rx_align_errs +
1682 hwstat->rx_symbol_errs);
1683
1684 nstat->tx_aborted_errors = hwstat->tx_underruns;
1685 #if 0
1686 /* Carrier lost counter seems to be broken for some devices */
1687 nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1688 #endif
1689
1690 return nstat;
1691 }
1692
1693 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1694 {
1695 struct dev_mc_list *mclist;
1696 int i, num_ents;
1697
1698 num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1699 mclist = dev->mc_list;
1700 for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1701 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1702 }
1703 return i+1;
1704 }
1705
1706 static void __b44_set_rx_mode(struct net_device *dev)
1707 {
1708 struct b44 *bp = netdev_priv(dev);
1709 u32 val;
1710
1711 val = br32(bp, B44_RXCONFIG);
1712 val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1713 if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
1714 val |= RXCONFIG_PROMISC;
1715 bw32(bp, B44_RXCONFIG, val);
1716 } else {
1717 unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
1718 int i = 1;
1719
1720 __b44_set_mac_addr(bp);
1721
1722 if ((dev->flags & IFF_ALLMULTI) ||
1723 (dev->mc_count > B44_MCAST_TABLE_SIZE))
1724 val |= RXCONFIG_ALLMULTI;
1725 else
1726 i = __b44_load_mcast(bp, dev);
1727
1728 for (; i < 64; i++)
1729 __b44_cam_write(bp, zero, i);
1730
1731 bw32(bp, B44_RXCONFIG, val);
1732 val = br32(bp, B44_CAM_CTRL);
1733 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1734 }
1735 }
1736
1737 static void b44_set_rx_mode(struct net_device *dev)
1738 {
1739 struct b44 *bp = netdev_priv(dev);
1740
1741 spin_lock_irq(&bp->lock);
1742 __b44_set_rx_mode(dev);
1743 spin_unlock_irq(&bp->lock);
1744 }
1745
1746 static u32 b44_get_msglevel(struct net_device *dev)
1747 {
1748 struct b44 *bp = netdev_priv(dev);
1749 return bp->msg_enable;
1750 }
1751
1752 static void b44_set_msglevel(struct net_device *dev, u32 value)
1753 {
1754 struct b44 *bp = netdev_priv(dev);
1755 bp->msg_enable = value;
1756 }
1757
1758 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1759 {
1760 struct b44 *bp = netdev_priv(dev);
1761 struct ssb_bus *bus = bp->sdev->bus;
1762
1763 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1764 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1765 switch (bus->bustype) {
1766 case SSB_BUSTYPE_PCI:
1767 strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
1768 break;
1769 case SSB_BUSTYPE_SSB:
1770 strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
1771 break;
1772 case SSB_BUSTYPE_PCMCIA:
1773 case SSB_BUSTYPE_SDIO:
1774 WARN_ON(1); /* A device with this bus does not exist. */
1775 break;
1776 }
1777 }
1778
1779 static int b44_nway_reset(struct net_device *dev)
1780 {
1781 struct b44 *bp = netdev_priv(dev);
1782 u32 bmcr;
1783 int r;
1784
1785 spin_lock_irq(&bp->lock);
1786 b44_readphy(bp, MII_BMCR, &bmcr);
1787 b44_readphy(bp, MII_BMCR, &bmcr);
1788 r = -EINVAL;
1789 if (bmcr & BMCR_ANENABLE) {
1790 b44_writephy(bp, MII_BMCR,
1791 bmcr | BMCR_ANRESTART);
1792 r = 0;
1793 }
1794 spin_unlock_irq(&bp->lock);
1795
1796 return r;
1797 }
1798
1799 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1800 {
1801 struct b44 *bp = netdev_priv(dev);
1802
1803 cmd->supported = (SUPPORTED_Autoneg);
1804 cmd->supported |= (SUPPORTED_100baseT_Half |
1805 SUPPORTED_100baseT_Full |
1806 SUPPORTED_10baseT_Half |
1807 SUPPORTED_10baseT_Full |
1808 SUPPORTED_MII);
1809
1810 cmd->advertising = 0;
1811 if (bp->flags & B44_FLAG_ADV_10HALF)
1812 cmd->advertising |= ADVERTISED_10baseT_Half;
1813 if (bp->flags & B44_FLAG_ADV_10FULL)
1814 cmd->advertising |= ADVERTISED_10baseT_Full;
1815 if (bp->flags & B44_FLAG_ADV_100HALF)
1816 cmd->advertising |= ADVERTISED_100baseT_Half;
1817 if (bp->flags & B44_FLAG_ADV_100FULL)
1818 cmd->advertising |= ADVERTISED_100baseT_Full;
1819 cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
1820 cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1821 SPEED_100 : SPEED_10;
1822 cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1823 DUPLEX_FULL : DUPLEX_HALF;
1824 cmd->port = 0;
1825 cmd->phy_address = bp->phy_addr;
1826 cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1827 XCVR_INTERNAL : XCVR_EXTERNAL;
1828 cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1829 AUTONEG_DISABLE : AUTONEG_ENABLE;
1830 if (cmd->autoneg == AUTONEG_ENABLE)
1831 cmd->advertising |= ADVERTISED_Autoneg;
1832 if (!netif_running(dev)){
1833 cmd->speed = 0;
1834 cmd->duplex = 0xff;
1835 }
1836 cmd->maxtxpkt = 0;
1837 cmd->maxrxpkt = 0;
1838 return 0;
1839 }
1840
1841 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1842 {
1843 struct b44 *bp = netdev_priv(dev);
1844
1845 /* We do not support gigabit. */
1846 if (cmd->autoneg == AUTONEG_ENABLE) {
1847 if (cmd->advertising &
1848 (ADVERTISED_1000baseT_Half |
1849 ADVERTISED_1000baseT_Full))
1850 return -EINVAL;
1851 } else if ((cmd->speed != SPEED_100 &&
1852 cmd->speed != SPEED_10) ||
1853 (cmd->duplex != DUPLEX_HALF &&
1854 cmd->duplex != DUPLEX_FULL)) {
1855 return -EINVAL;
1856 }
1857
1858 spin_lock_irq(&bp->lock);
1859
1860 if (cmd->autoneg == AUTONEG_ENABLE) {
1861 bp->flags &= ~(B44_FLAG_FORCE_LINK |
1862 B44_FLAG_100_BASE_T |
1863 B44_FLAG_FULL_DUPLEX |
1864 B44_FLAG_ADV_10HALF |
1865 B44_FLAG_ADV_10FULL |
1866 B44_FLAG_ADV_100HALF |
1867 B44_FLAG_ADV_100FULL);
1868 if (cmd->advertising == 0) {
1869 bp->flags |= (B44_FLAG_ADV_10HALF |
1870 B44_FLAG_ADV_10FULL |
1871 B44_FLAG_ADV_100HALF |
1872 B44_FLAG_ADV_100FULL);
1873 } else {
1874 if (cmd->advertising & ADVERTISED_10baseT_Half)
1875 bp->flags |= B44_FLAG_ADV_10HALF;
1876 if (cmd->advertising & ADVERTISED_10baseT_Full)
1877 bp->flags |= B44_FLAG_ADV_10FULL;
1878 if (cmd->advertising & ADVERTISED_100baseT_Half)
1879 bp->flags |= B44_FLAG_ADV_100HALF;
1880 if (cmd->advertising & ADVERTISED_100baseT_Full)
1881 bp->flags |= B44_FLAG_ADV_100FULL;
1882 }
1883 } else {
1884 bp->flags |= B44_FLAG_FORCE_LINK;
1885 bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
1886 if (cmd->speed == SPEED_100)
1887 bp->flags |= B44_FLAG_100_BASE_T;
1888 if (cmd->duplex == DUPLEX_FULL)
1889 bp->flags |= B44_FLAG_FULL_DUPLEX;
1890 }
1891
1892 if (netif_running(dev))
1893 b44_setup_phy(bp);
1894
1895 spin_unlock_irq(&bp->lock);
1896
1897 return 0;
1898 }
1899
1900 static void b44_get_ringparam(struct net_device *dev,
1901 struct ethtool_ringparam *ering)
1902 {
1903 struct b44 *bp = netdev_priv(dev);
1904
1905 ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1906 ering->rx_pending = bp->rx_pending;
1907
1908 /* XXX ethtool lacks a tx_max_pending, oops... */
1909 }
1910
1911 static int b44_set_ringparam(struct net_device *dev,
1912 struct ethtool_ringparam *ering)
1913 {
1914 struct b44 *bp = netdev_priv(dev);
1915
1916 if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1917 (ering->rx_mini_pending != 0) ||
1918 (ering->rx_jumbo_pending != 0) ||
1919 (ering->tx_pending > B44_TX_RING_SIZE - 1))
1920 return -EINVAL;
1921
1922 spin_lock_irq(&bp->lock);
1923
1924 bp->rx_pending = ering->rx_pending;
1925 bp->tx_pending = ering->tx_pending;
1926
1927 b44_halt(bp);
1928 b44_init_rings(bp);
1929 b44_init_hw(bp, B44_FULL_RESET);
1930 netif_wake_queue(bp->dev);
1931 spin_unlock_irq(&bp->lock);
1932
1933 b44_enable_ints(bp);
1934
1935 return 0;
1936 }
1937
1938 static void b44_get_pauseparam(struct net_device *dev,
1939 struct ethtool_pauseparam *epause)
1940 {
1941 struct b44 *bp = netdev_priv(dev);
1942
1943 epause->autoneg =
1944 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1945 epause->rx_pause =
1946 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1947 epause->tx_pause =
1948 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1949 }
1950
1951 static int b44_set_pauseparam(struct net_device *dev,
1952 struct ethtool_pauseparam *epause)
1953 {
1954 struct b44 *bp = netdev_priv(dev);
1955
1956 spin_lock_irq(&bp->lock);
1957 if (epause->autoneg)
1958 bp->flags |= B44_FLAG_PAUSE_AUTO;
1959 else
1960 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1961 if (epause->rx_pause)
1962 bp->flags |= B44_FLAG_RX_PAUSE;
1963 else
1964 bp->flags &= ~B44_FLAG_RX_PAUSE;
1965 if (epause->tx_pause)
1966 bp->flags |= B44_FLAG_TX_PAUSE;
1967 else
1968 bp->flags &= ~B44_FLAG_TX_PAUSE;
1969 if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1970 b44_halt(bp);
1971 b44_init_rings(bp);
1972 b44_init_hw(bp, B44_FULL_RESET);
1973 } else {
1974 __b44_set_flow_ctrl(bp, bp->flags);
1975 }
1976 spin_unlock_irq(&bp->lock);
1977
1978 b44_enable_ints(bp);
1979
1980 return 0;
1981 }
1982
1983 static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1984 {
1985 switch(stringset) {
1986 case ETH_SS_STATS:
1987 memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
1988 break;
1989 }
1990 }
1991
1992 static int b44_get_sset_count(struct net_device *dev, int sset)
1993 {
1994 switch (sset) {
1995 case ETH_SS_STATS:
1996 return ARRAY_SIZE(b44_gstrings);
1997 default:
1998 return -EOPNOTSUPP;
1999 }
2000 }
2001
2002 static void b44_get_ethtool_stats(struct net_device *dev,
2003 struct ethtool_stats *stats, u64 *data)
2004 {
2005 struct b44 *bp = netdev_priv(dev);
2006 u32 *val = &bp->hw_stats.tx_good_octets;
2007 u32 i;
2008
2009 spin_lock_irq(&bp->lock);
2010
2011 b44_stats_update(bp);
2012
2013 for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
2014 *data++ = *val++;
2015
2016 spin_unlock_irq(&bp->lock);
2017 }
2018
2019 static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2020 {
2021 struct b44 *bp = netdev_priv(dev);
2022
2023 wol->supported = WAKE_MAGIC;
2024 if (bp->flags & B44_FLAG_WOL_ENABLE)
2025 wol->wolopts = WAKE_MAGIC;
2026 else
2027 wol->wolopts = 0;
2028 memset(&wol->sopass, 0, sizeof(wol->sopass));
2029 }
2030
2031 static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2032 {
2033 struct b44 *bp = netdev_priv(dev);
2034
2035 spin_lock_irq(&bp->lock);
2036 if (wol->wolopts & WAKE_MAGIC)
2037 bp->flags |= B44_FLAG_WOL_ENABLE;
2038 else
2039 bp->flags &= ~B44_FLAG_WOL_ENABLE;
2040 spin_unlock_irq(&bp->lock);
2041
2042 return 0;
2043 }
2044
2045 static const struct ethtool_ops b44_ethtool_ops = {
2046 .get_drvinfo = b44_get_drvinfo,
2047 .get_settings = b44_get_settings,
2048 .set_settings = b44_set_settings,
2049 .nway_reset = b44_nway_reset,
2050 .get_link = ethtool_op_get_link,
2051 .get_wol = b44_get_wol,
2052 .set_wol = b44_set_wol,
2053 .get_ringparam = b44_get_ringparam,
2054 .set_ringparam = b44_set_ringparam,
2055 .get_pauseparam = b44_get_pauseparam,
2056 .set_pauseparam = b44_set_pauseparam,
2057 .get_msglevel = b44_get_msglevel,
2058 .set_msglevel = b44_set_msglevel,
2059 .get_strings = b44_get_strings,
2060 .get_sset_count = b44_get_sset_count,
2061 .get_ethtool_stats = b44_get_ethtool_stats,
2062 };
2063
2064 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2065 {
2066 struct mii_ioctl_data *data = if_mii(ifr);
2067 struct b44 *bp = netdev_priv(dev);
2068 int err = -EINVAL;
2069
2070 if (!netif_running(dev))
2071 goto out;
2072
2073 spin_lock_irq(&bp->lock);
2074 err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
2075 spin_unlock_irq(&bp->lock);
2076 out:
2077 return err;
2078 }
2079
2080 static int __devinit b44_get_invariants(struct b44 *bp)
2081 {
2082 struct ssb_device *sdev = bp->sdev;
2083 int err = 0;
2084 u8 *addr;
2085
2086 bp->dma_offset = ssb_dma_translation(sdev);
2087
2088 if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
2089 instance > 1) {
2090 addr = sdev->bus->sprom.et1mac;
2091 bp->phy_addr = sdev->bus->sprom.et1phyaddr;
2092 } else {
2093 addr = sdev->bus->sprom.et0mac;
2094 bp->phy_addr = sdev->bus->sprom.et0phyaddr;
2095 }
2096 /* Some ROMs have buggy PHY addresses with the high
2097 * bits set (sign extension?). Truncate them to a
2098 * valid PHY address. */
2099 bp->phy_addr &= 0x1F;
2100
2101 memcpy(bp->dev->dev_addr, addr, 6);
2102
2103 if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
2104 printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
2105 return -EINVAL;
2106 }
2107
2108 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
2109
2110 bp->imask = IMASK_DEF;
2111
2112 /* XXX - really required?
2113 bp->flags |= B44_FLAG_BUGGY_TXPTR;
2114 */
2115
2116 if (bp->sdev->id.revision >= 7)
2117 bp->flags |= B44_FLAG_B0_ANDLATER;
2118
2119 return err;
2120 }
2121
2122 static const struct net_device_ops b44_netdev_ops = {
2123 .ndo_open = b44_open,
2124 .ndo_stop = b44_close,
2125 .ndo_start_xmit = b44_start_xmit,
2126 .ndo_get_stats = b44_get_stats,
2127 .ndo_set_multicast_list = b44_set_rx_mode,
2128 .ndo_set_mac_address = b44_set_mac_addr,
2129 .ndo_validate_addr = eth_validate_addr,
2130 .ndo_do_ioctl = b44_ioctl,
2131 .ndo_tx_timeout = b44_tx_timeout,
2132 .ndo_change_mtu = b44_change_mtu,
2133 #ifdef CONFIG_NET_POLL_CONTROLLER
2134 .ndo_poll_controller = b44_poll_controller,
2135 #endif
2136 };
2137
2138 static int __devinit b44_init_one(struct ssb_device *sdev,
2139 const struct ssb_device_id *ent)
2140 {
2141 static int b44_version_printed = 0;
2142 struct net_device *dev;
2143 struct b44 *bp;
2144 int err;
2145
2146 instance++;
2147
2148 if (b44_version_printed++ == 0)
2149 printk(KERN_INFO "%s", version);
2150
2151
2152 dev = alloc_etherdev(sizeof(*bp));
2153 if (!dev) {
2154 dev_err(sdev->dev, "Etherdev alloc failed, aborting.\n");
2155 err = -ENOMEM;
2156 goto out;
2157 }
2158
2159 SET_NETDEV_DEV(dev, sdev->dev);
2160
2161 /* No interesting netdevice features in this card... */
2162 dev->features |= 0;
2163
2164 bp = netdev_priv(dev);
2165 bp->sdev = sdev;
2166 bp->dev = dev;
2167 bp->force_copybreak = 0;
2168
2169 bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
2170
2171 spin_lock_init(&bp->lock);
2172
2173 bp->rx_pending = B44_DEF_RX_RING_PENDING;
2174 bp->tx_pending = B44_DEF_TX_RING_PENDING;
2175
2176 dev->netdev_ops = &b44_netdev_ops;
2177 netif_napi_add(dev, &bp->napi, b44_poll, 64);
2178 dev->watchdog_timeo = B44_TX_TIMEOUT;
2179 dev->irq = sdev->irq;
2180 SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
2181
2182 netif_carrier_off(dev);
2183
2184 err = ssb_bus_powerup(sdev->bus, 0);
2185 if (err) {
2186 dev_err(sdev->dev,
2187 "Failed to powerup the bus\n");
2188 goto err_out_free_dev;
2189 }
2190 err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
2191 if (err) {
2192 dev_err(sdev->dev,
2193 "Required 30BIT DMA mask unsupported by the system.\n");
2194 goto err_out_powerdown;
2195 }
2196 err = b44_get_invariants(bp);
2197 if (err) {
2198 dev_err(sdev->dev,
2199 "Problem fetching invariants of chip, aborting.\n");
2200 goto err_out_powerdown;
2201 }
2202
2203 bp->mii_if.dev = dev;
2204 bp->mii_if.mdio_read = b44_mii_read;
2205 bp->mii_if.mdio_write = b44_mii_write;
2206 bp->mii_if.phy_id = bp->phy_addr;
2207 bp->mii_if.phy_id_mask = 0x1f;
2208 bp->mii_if.reg_num_mask = 0x1f;
2209
2210 /* By default, advertise all speed/duplex settings. */
2211 bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
2212 B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
2213
2214 /* By default, auto-negotiate PAUSE. */
2215 bp->flags |= B44_FLAG_PAUSE_AUTO;
2216
2217 err = register_netdev(dev);
2218 if (err) {
2219 dev_err(sdev->dev, "Cannot register net device, aborting.\n");
2220 goto err_out_powerdown;
2221 }
2222
2223 ssb_set_drvdata(sdev, dev);
2224
2225 /* Chip reset provides power to the b44 MAC & PCI cores, which
2226 * is necessary for MAC register access.
2227 */
2228 b44_chip_reset(bp, B44_CHIP_RESET_FULL);
2229
2230 printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %pM\n",
2231 dev->name, dev->dev_addr);
2232
2233 return 0;
2234
2235 err_out_powerdown:
2236 ssb_bus_may_powerdown(sdev->bus);
2237
2238 err_out_free_dev:
2239 free_netdev(dev);
2240
2241 out:
2242 return err;
2243 }
2244
2245 static void __devexit b44_remove_one(struct ssb_device *sdev)
2246 {
2247 struct net_device *dev = ssb_get_drvdata(sdev);
2248
2249 unregister_netdev(dev);
2250 ssb_device_disable(sdev, 0);
2251 ssb_bus_may_powerdown(sdev->bus);
2252 free_netdev(dev);
2253 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2254 ssb_set_drvdata(sdev, NULL);
2255 }
2256
2257 static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
2258 {
2259 struct net_device *dev = ssb_get_drvdata(sdev);
2260 struct b44 *bp = netdev_priv(dev);
2261
2262 if (!netif_running(dev))
2263 return 0;
2264
2265 del_timer_sync(&bp->timer);
2266
2267 spin_lock_irq(&bp->lock);
2268
2269 b44_halt(bp);
2270 netif_carrier_off(bp->dev);
2271 netif_device_detach(bp->dev);
2272 b44_free_rings(bp);
2273
2274 spin_unlock_irq(&bp->lock);
2275
2276 free_irq(dev->irq, dev);
2277 if (bp->flags & B44_FLAG_WOL_ENABLE) {
2278 b44_init_hw(bp, B44_PARTIAL_RESET);
2279 b44_setup_wol(bp);
2280 }
2281
2282 ssb_pcihost_set_power_state(sdev, PCI_D3hot);
2283 return 0;
2284 }
2285
2286 static int b44_resume(struct ssb_device *sdev)
2287 {
2288 struct net_device *dev = ssb_get_drvdata(sdev);
2289 struct b44 *bp = netdev_priv(dev);
2290 int rc = 0;
2291
2292 rc = ssb_bus_powerup(sdev->bus, 0);
2293 if (rc) {
2294 dev_err(sdev->dev,
2295 "Failed to powerup the bus\n");
2296 return rc;
2297 }
2298
2299 if (!netif_running(dev))
2300 return 0;
2301
2302 rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
2303 if (rc) {
2304 printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
2305 return rc;
2306 }
2307
2308 spin_lock_irq(&bp->lock);
2309
2310 b44_init_rings(bp);
2311 b44_init_hw(bp, B44_FULL_RESET);
2312 netif_device_attach(bp->dev);
2313 spin_unlock_irq(&bp->lock);
2314
2315 b44_enable_ints(bp);
2316 netif_wake_queue(dev);
2317
2318 mod_timer(&bp->timer, jiffies + 1);
2319
2320 return 0;
2321 }
2322
2323 static struct ssb_driver b44_ssb_driver = {
2324 .name = DRV_MODULE_NAME,
2325 .id_table = b44_ssb_tbl,
2326 .probe = b44_init_one,
2327 .remove = __devexit_p(b44_remove_one),
2328 .suspend = b44_suspend,
2329 .resume = b44_resume,
2330 };
2331
2332 static inline int b44_pci_init(void)
2333 {
2334 int err = 0;
2335 #ifdef CONFIG_B44_PCI
2336 err = ssb_pcihost_register(&b44_pci_driver);
2337 #endif
2338 return err;
2339 }
2340
2341 static inline void b44_pci_exit(void)
2342 {
2343 #ifdef CONFIG_B44_PCI
2344 ssb_pcihost_unregister(&b44_pci_driver);
2345 #endif
2346 }
2347
2348 static int __init b44_init(void)
2349 {
2350 unsigned int dma_desc_align_size = dma_get_cache_alignment();
2351 int err;
2352
2353 /* Setup paramaters for syncing RX/TX DMA descriptors */
2354 dma_desc_align_mask = ~(dma_desc_align_size - 1);
2355 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
2356
2357 err = b44_pci_init();
2358 if (err)
2359 return err;
2360 err = ssb_driver_register(&b44_ssb_driver);
2361 if (err)
2362 b44_pci_exit();
2363 return err;
2364 }
2365
2366 static void __exit b44_cleanup(void)
2367 {
2368 ssb_driver_unregister(&b44_ssb_driver);
2369 b44_pci_exit();
2370 }
2371
2372 module_init(b44_init);
2373 module_exit(b44_cleanup);
2374
Verdex Pro support