drivers/net/bnx2x_init.h

   1 /* bnx2x_init.h: Broadcom Everest network driver.
   2  *               Structures and macroes needed during the initialization.
   3  *
   4  * Copyright (c) 2007-2009 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  *
  10  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  11  * Written by: Eliezer Tamir
  12  * Modified by: Vladislav Zolotarov <vladz@broadcom.com>
  13  */
  14
  15 #ifndef BNX2X_INIT_H
  16 #define BNX2X_INIT_H
  17
  18 /* RAM0 size in bytes */
  19 #define STORM_INTMEM_SIZE_E1            0x5800
  20 #define STORM_INTMEM_SIZE_E1H           0x10000
  21 #define STORM_INTMEM_SIZE(bp) ((CHIP_IS_E1(bp) ? STORM_INTMEM_SIZE_E1 : \
  22                                                     STORM_INTMEM_SIZE_E1H) / 4)
  23
  24
  25 /* Init operation types and structures */
  26 /* Common for both E1 and E1H */
  27 #define OP_RD                   0x1 /* read single register */
  28 #define OP_WR                   0x2 /* write single register */
  29 #define OP_IW                   0x3 /* write single register using mailbox */
  30 #define OP_SW                   0x4 /* copy a string to the device */
  31 #define OP_SI                   0x5 /* copy a string using mailbox */
  32 #define OP_ZR                   0x6 /* clear memory */
  33 #define OP_ZP                   0x7 /* unzip then copy with DMAE */
  34 #define OP_WR_64                0x8 /* write 64 bit pattern */
  35 #define OP_WB                   0x9 /* copy a string using DMAE */
  36
  37 /* FPGA and EMUL specific operations */
  38 #define OP_WR_EMUL              0xa /* write single register on Emulation */
  39 #define OP_WR_FPGA              0xb /* write single register on FPGA */
  40 #define OP_WR_ASIC              0xc /* write single register on ASIC */
  41
  42 /* Init stages */
  43 /* Never reorder stages !!! */
  44 #define COMMON_STAGE            0
  45 #define PORT0_STAGE             1
  46 #define PORT1_STAGE             2
  47 #define FUNC0_STAGE             3
  48 #define FUNC1_STAGE             4
  49 #define FUNC2_STAGE             5
  50 #define FUNC3_STAGE             6
  51 #define FUNC4_STAGE             7
  52 #define FUNC5_STAGE             8
  53 #define FUNC6_STAGE             9
  54 #define FUNC7_STAGE             10
  55 #define STAGE_IDX_MAX           11
  56
  57 #define STAGE_START             0
  58 #define STAGE_END               1
  59
  60
  61 /* Indices of blocks */
  62 #define PRS_BLOCK               0
  63 #define SRCH_BLOCK              1
  64 #define TSDM_BLOCK              2
  65 #define TCM_BLOCK               3
  66 #define BRB1_BLOCK              4
  67 #define TSEM_BLOCK              5
  68 #define PXPCS_BLOCK             6
  69 #define EMAC0_BLOCK             7
  70 #define EMAC1_BLOCK             8
  71 #define DBU_BLOCK               9
  72 #define MISC_BLOCK              10
  73 #define DBG_BLOCK               11
  74 #define NIG_BLOCK               12
  75 #define MCP_BLOCK               13
  76 #define UPB_BLOCK               14
  77 #define CSDM_BLOCK              15
  78 #define USDM_BLOCK              16
  79 #define CCM_BLOCK               17
  80 #define UCM_BLOCK               18
  81 #define USEM_BLOCK              19
  82 #define CSEM_BLOCK              20
  83 #define XPB_BLOCK               21
  84 #define DQ_BLOCK                22
  85 #define TIMERS_BLOCK            23
  86 #define XSDM_BLOCK              24
  87 #define QM_BLOCK                25
  88 #define PBF_BLOCK               26
  89 #define XCM_BLOCK               27
  90 #define XSEM_BLOCK              28
  91 #define CDU_BLOCK               29
  92 #define DMAE_BLOCK              30
  93 #define PXP_BLOCK               31
  94 #define CFC_BLOCK               32
  95 #define HC_BLOCK                33
  96 #define PXP2_BLOCK              34
  97 #define MISC_AEU_BLOCK          35
  98 #define PGLUE_B_BLOCK           36
  99 #define IGU_BLOCK               37
 100
 101
 102 /* Returns the index of start or end of a specific block stage in ops array*/
 103 #define BLOCK_OPS_IDX(block, stage, end) \
 104                         (2*(((block)*STAGE_IDX_MAX) + (stage)) + (end))
 105
 106
 107 struct raw_op {
 108         u32 op:8;
 109         u32 offset:24;
 110         u32 raw_data;
 111 };
 112
 113 struct op_read {
 114         u32 op:8;
 115         u32 offset:24;
 116         u32 pad;
 117 };
 118
 119 struct op_write {
 120         u32 op:8;
 121         u32 offset:24;
 122         u32 val;
 123 };
 124
 125 struct op_string_write {
 126         u32 op:8;
 127         u32 offset:24;
 128 #ifdef __LITTLE_ENDIAN
 129         u16 data_off;
 130         u16 data_len;
 131 #else /* __BIG_ENDIAN */
 132         u16 data_len;
 133         u16 data_off;
 134 #endif
 135 };
 136
 137 struct op_zero {
 138         u32 op:8;
 139         u32 offset:24;
 140         u32 len;
 141 };
 142
 143 union init_op {
 144         struct op_read          read;
 145         struct op_write         write;
 146         struct op_string_write  str_wr;
 147         struct op_zero          zero;
 148         struct raw_op           raw;
 149 };
 150
 151 #endif /* BNX2X_INIT_H */
 152