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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / ethoc.c
blob9c950bb5e90c7fe4e74fae553f4697146eaf046e
1 /*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14 #include <linux/etherdevice.h>
15 #include <linux/crc32.h>
16 #include <linux/io.h>
17 #include <linux/mii.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/sched.h>
21 #include <net/ethoc.h>
22
23 static int buffer_size = 0x8000; /* 32 KBytes */
24 module_param(buffer_size, int, 0);
25 MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
26
27 /* register offsets */
28 #define MODER 0x00
29 #define INT_SOURCE 0x04
30 #define INT_MASK 0x08
31 #define IPGT 0x0c
32 #define IPGR1 0x10
33 #define IPGR2 0x14
34 #define PACKETLEN 0x18
35 #define COLLCONF 0x1c
36 #define TX_BD_NUM 0x20
37 #define CTRLMODER 0x24
38 #define MIIMODER 0x28
39 #define MIICOMMAND 0x2c
40 #define MIIADDRESS 0x30
41 #define MIITX_DATA 0x34
42 #define MIIRX_DATA 0x38
43 #define MIISTATUS 0x3c
44 #define MAC_ADDR0 0x40
45 #define MAC_ADDR1 0x44
46 #define ETH_HASH0 0x48
47 #define ETH_HASH1 0x4c
48 #define ETH_TXCTRL 0x50
49
50 /* mode register */
51 #define MODER_RXEN (1 << 0) /* receive enable */
52 #define MODER_TXEN (1 << 1) /* transmit enable */
53 #define MODER_NOPRE (1 << 2) /* no preamble */
54 #define MODER_BRO (1 << 3) /* broadcast address */
55 #define MODER_IAM (1 << 4) /* individual address mode */
56 #define MODER_PRO (1 << 5) /* promiscuous mode */
57 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
58 #define MODER_LOOP (1 << 7) /* loopback */
59 #define MODER_NBO (1 << 8) /* no back-off */
60 #define MODER_EDE (1 << 9) /* excess defer enable */
61 #define MODER_FULLD (1 << 10) /* full duplex */
62 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
63 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
64 #define MODER_CRC (1 << 13) /* CRC enable */
65 #define MODER_HUGE (1 << 14) /* huge packets enable */
66 #define MODER_PAD (1 << 15) /* padding enabled */
67 #define MODER_RSM (1 << 16) /* receive small packets */
68
69 /* interrupt source and mask registers */
70 #define INT_MASK_TXF (1 << 0) /* transmit frame */
71 #define INT_MASK_TXE (1 << 1) /* transmit error */
72 #define INT_MASK_RXF (1 << 2) /* receive frame */
73 #define INT_MASK_RXE (1 << 3) /* receive error */
74 #define INT_MASK_BUSY (1 << 4)
75 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
76 #define INT_MASK_RXC (1 << 6) /* receive control frame */
77
78 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
79 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
80
81 #define INT_MASK_ALL ( \
82 INT_MASK_TXF | INT_MASK_TXE | \
83 INT_MASK_RXF | INT_MASK_RXE | \
84 INT_MASK_TXC | INT_MASK_RXC | \
85 INT_MASK_BUSY \
86 )
87
88 /* packet length register */
89 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
90 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
91 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
92 PACKETLEN_MAX(max))
93
94 /* transmit buffer number register */
95 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
96
97 /* control module mode register */
98 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
99 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
100 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
101
102 /* MII mode register */
103 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
104 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
105
106 /* MII command register */
107 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
108 #define MIICOMMAND_READ (1 << 1) /* read status */
109 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
110
111 /* MII address register */
112 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
113 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
114 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
115 MIIADDRESS_RGAD(reg))
116
117 /* MII transmit data register */
118 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
119
120 /* MII receive data register */
121 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
122
123 /* MII status register */
124 #define MIISTATUS_LINKFAIL (1 << 0)
125 #define MIISTATUS_BUSY (1 << 1)
126 #define MIISTATUS_INVALID (1 << 2)
127
128 /* TX buffer descriptor */
129 #define TX_BD_CS (1 << 0) /* carrier sense lost */
130 #define TX_BD_DF (1 << 1) /* defer indication */
131 #define TX_BD_LC (1 << 2) /* late collision */
132 #define TX_BD_RL (1 << 3) /* retransmission limit */
133 #define TX_BD_RETRY_MASK (0x00f0)
134 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
135 #define TX_BD_UR (1 << 8) /* transmitter underrun */
136 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
137 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
138 #define TX_BD_WRAP (1 << 13)
139 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
140 #define TX_BD_READY (1 << 15) /* TX buffer ready */
141 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
142 #define TX_BD_LEN_MASK (0xffff << 16)
143
144 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
145 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
146
147 /* RX buffer descriptor */
148 #define RX_BD_LC (1 << 0) /* late collision */
149 #define RX_BD_CRC (1 << 1) /* RX CRC error */
150 #define RX_BD_SF (1 << 2) /* short frame */
151 #define RX_BD_TL (1 << 3) /* too long */
152 #define RX_BD_DN (1 << 4) /* dribble nibble */
153 #define RX_BD_IS (1 << 5) /* invalid symbol */
154 #define RX_BD_OR (1 << 6) /* receiver overrun */
155 #define RX_BD_MISS (1 << 7)
156 #define RX_BD_CF (1 << 8) /* control frame */
157 #define RX_BD_WRAP (1 << 13)
158 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
159 #define RX_BD_EMPTY (1 << 15)
160 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
161
162 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
163 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
164
165 #define ETHOC_BUFSIZ 1536
166 #define ETHOC_ZLEN 64
167 #define ETHOC_BD_BASE 0x400
168 #define ETHOC_TIMEOUT (HZ / 2)
169 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
170
171 /**
172 * struct ethoc - driver-private device structure
173 * @iobase: pointer to I/O memory region
174 * @membase: pointer to buffer memory region
175 * @dma_alloc: dma allocated buffer size
176 * @num_tx: number of send buffers
177 * @cur_tx: last send buffer written
178 * @dty_tx: last buffer actually sent
179 * @num_rx: number of receive buffers
180 * @cur_rx: current receive buffer
181 * @netdev: pointer to network device structure
182 * @napi: NAPI structure
183 * @stats: network device statistics
184 * @msg_enable: device state flags
185 * @rx_lock: receive lock
186 * @lock: device lock
187 * @phy: attached PHY
188 * @mdio: MDIO bus for PHY access
189 * @phy_id: address of attached PHY
190 */
191 struct ethoc {
192 void __iomem *iobase;
193 void __iomem *membase;
194 int dma_alloc;
195
196 unsigned int num_tx;
197 unsigned int cur_tx;
198 unsigned int dty_tx;
199
200 unsigned int num_rx;
201 unsigned int cur_rx;
202
203 struct net_device *netdev;
204 struct napi_struct napi;
205 struct net_device_stats stats;
206 u32 msg_enable;
207
208 spinlock_t rx_lock;
209 spinlock_t lock;
210
211 struct phy_device *phy;
212 struct mii_bus *mdio;
213 s8 phy_id;
214 };
215
216 /**
217 * struct ethoc_bd - buffer descriptor
218 * @stat: buffer statistics
219 * @addr: physical memory address
220 */
221 struct ethoc_bd {
222 u32 stat;
223 u32 addr;
224 };
225
226 static u32 ethoc_read(struct ethoc *dev, loff_t offset)
227 {
228 return ioread32(dev->iobase + offset);
229 }
230
231 static void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
232 {
233 iowrite32(data, dev->iobase + offset);
234 }
235
236 static void ethoc_read_bd(struct ethoc *dev, int index, struct ethoc_bd *bd)
237 {
238 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
239 bd->stat = ethoc_read(dev, offset + 0);
240 bd->addr = ethoc_read(dev, offset + 4);
241 }
242
243 static void ethoc_write_bd(struct ethoc *dev, int index,
244 const struct ethoc_bd *bd)
245 {
246 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
247 ethoc_write(dev, offset + 0, bd->stat);
248 ethoc_write(dev, offset + 4, bd->addr);
249 }
250
251 static void ethoc_enable_irq(struct ethoc *dev, u32 mask)
252 {
253 u32 imask = ethoc_read(dev, INT_MASK);
254 imask |= mask;
255 ethoc_write(dev, INT_MASK, imask);
256 }
257
258 static void ethoc_disable_irq(struct ethoc *dev, u32 mask)
259 {
260 u32 imask = ethoc_read(dev, INT_MASK);
261 imask &= ~mask;
262 ethoc_write(dev, INT_MASK, imask);
263 }
264
265 static void ethoc_ack_irq(struct ethoc *dev, u32 mask)
266 {
267 ethoc_write(dev, INT_SOURCE, mask);
268 }
269
270 static void ethoc_enable_rx_and_tx(struct ethoc *dev)
271 {
272 u32 mode = ethoc_read(dev, MODER);
273 mode |= MODER_RXEN | MODER_TXEN;
274 ethoc_write(dev, MODER, mode);
275 }
276
277 static void ethoc_disable_rx_and_tx(struct ethoc *dev)
278 {
279 u32 mode = ethoc_read(dev, MODER);
280 mode &= ~(MODER_RXEN | MODER_TXEN);
281 ethoc_write(dev, MODER, mode);
282 }
283
284 static int ethoc_init_ring(struct ethoc *dev)
285 {
286 struct ethoc_bd bd;
287 int i;
288
289 dev->cur_tx = 0;
290 dev->dty_tx = 0;
291 dev->cur_rx = 0;
292
293 /* setup transmission buffers */
294 bd.addr = virt_to_phys(dev->membase);
295 bd.stat = TX_BD_IRQ | TX_BD_CRC;
296
297 for (i = 0; i < dev->num_tx; i++) {
298 if (i == dev->num_tx - 1)
299 bd.stat |= TX_BD_WRAP;
300
301 ethoc_write_bd(dev, i, &bd);
302 bd.addr += ETHOC_BUFSIZ;
303 }
304
305 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
306
307 for (i = 0; i < dev->num_rx; i++) {
308 if (i == dev->num_rx - 1)
309 bd.stat |= RX_BD_WRAP;
310
311 ethoc_write_bd(dev, dev->num_tx + i, &bd);
312 bd.addr += ETHOC_BUFSIZ;
313 }
314
315 return 0;
316 }
317
318 static int ethoc_reset(struct ethoc *dev)
319 {
320 u32 mode;
321
322 /* TODO: reset controller? */
323
324 ethoc_disable_rx_and_tx(dev);
325
326 /* TODO: setup registers */
327
328 /* enable FCS generation and automatic padding */
329 mode = ethoc_read(dev, MODER);
330 mode |= MODER_CRC | MODER_PAD;
331 ethoc_write(dev, MODER, mode);
332
333 /* set full-duplex mode */
334 mode = ethoc_read(dev, MODER);
335 mode |= MODER_FULLD;
336 ethoc_write(dev, MODER, mode);
337 ethoc_write(dev, IPGT, 0x15);
338
339 ethoc_ack_irq(dev, INT_MASK_ALL);
340 ethoc_enable_irq(dev, INT_MASK_ALL);
341 ethoc_enable_rx_and_tx(dev);
342 return 0;
343 }
344
345 static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
346 struct ethoc_bd *bd)
347 {
348 struct net_device *netdev = dev->netdev;
349 unsigned int ret = 0;
350
351 if (bd->stat & RX_BD_TL) {
352 dev_err(&netdev->dev, "RX: frame too long\n");
353 dev->stats.rx_length_errors++;
354 ret++;
355 }
356
357 if (bd->stat & RX_BD_SF) {
358 dev_err(&netdev->dev, "RX: frame too short\n");
359 dev->stats.rx_length_errors++;
360 ret++;
361 }
362
363 if (bd->stat & RX_BD_DN) {
364 dev_err(&netdev->dev, "RX: dribble nibble\n");
365 dev->stats.rx_frame_errors++;
366 }
367
368 if (bd->stat & RX_BD_CRC) {
369 dev_err(&netdev->dev, "RX: wrong CRC\n");
370 dev->stats.rx_crc_errors++;
371 ret++;
372 }
373
374 if (bd->stat & RX_BD_OR) {
375 dev_err(&netdev->dev, "RX: overrun\n");
376 dev->stats.rx_over_errors++;
377 ret++;
378 }
379
380 if (bd->stat & RX_BD_MISS)
381 dev->stats.rx_missed_errors++;
382
383 if (bd->stat & RX_BD_LC) {
384 dev_err(&netdev->dev, "RX: late collision\n");
385 dev->stats.collisions++;
386 ret++;
387 }
388
389 return ret;
390 }
391
392 static int ethoc_rx(struct net_device *dev, int limit)
393 {
394 struct ethoc *priv = netdev_priv(dev);
395 int count;
396
397 for (count = 0; count < limit; ++count) {
398 unsigned int entry;
399 struct ethoc_bd bd;
400
401 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
402 ethoc_read_bd(priv, entry, &bd);
403 if (bd.stat & RX_BD_EMPTY)
404 break;
405
406 if (ethoc_update_rx_stats(priv, &bd) == 0) {
407 int size = bd.stat >> 16;
408 struct sk_buff *skb = netdev_alloc_skb(dev, size);
409
410 size -= 4; /* strip the CRC */
411 skb_reserve(skb, 2); /* align TCP/IP header */
412
413 if (likely(skb)) {
414 void *src = phys_to_virt(bd.addr);
415 memcpy_fromio(skb_put(skb, size), src, size);
416 skb->protocol = eth_type_trans(skb, dev);
417 priv->stats.rx_packets++;
418 priv->stats.rx_bytes += size;
419 netif_receive_skb(skb);
420 } else {
421 if (net_ratelimit())
422 dev_warn(&dev->dev, "low on memory - "
423 "packet dropped\n");
424
425 priv->stats.rx_dropped++;
426 break;
427 }
428 }
429
430 /* clear the buffer descriptor so it can be reused */
431 bd.stat &= ~RX_BD_STATS;
432 bd.stat |= RX_BD_EMPTY;
433 ethoc_write_bd(priv, entry, &bd);
434 priv->cur_rx++;
435 }
436
437 return count;
438 }
439
440 static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
441 {
442 struct net_device *netdev = dev->netdev;
443
444 if (bd->stat & TX_BD_LC) {
445 dev_err(&netdev->dev, "TX: late collision\n");
446 dev->stats.tx_window_errors++;
447 }
448
449 if (bd->stat & TX_BD_RL) {
450 dev_err(&netdev->dev, "TX: retransmit limit\n");
451 dev->stats.tx_aborted_errors++;
452 }
453
454 if (bd->stat & TX_BD_UR) {
455 dev_err(&netdev->dev, "TX: underrun\n");
456 dev->stats.tx_fifo_errors++;
457 }
458
459 if (bd->stat & TX_BD_CS) {
460 dev_err(&netdev->dev, "TX: carrier sense lost\n");
461 dev->stats.tx_carrier_errors++;
462 }
463
464 if (bd->stat & TX_BD_STATS)
465 dev->stats.tx_errors++;
466
467 dev->stats.collisions += (bd->stat >> 4) & 0xf;
468 dev->stats.tx_bytes += bd->stat >> 16;
469 dev->stats.tx_packets++;
470 return 0;
471 }
472
473 static void ethoc_tx(struct net_device *dev)
474 {
475 struct ethoc *priv = netdev_priv(dev);
476
477 spin_lock(&priv->lock);
478
479 while (priv->dty_tx != priv->cur_tx) {
480 unsigned int entry = priv->dty_tx % priv->num_tx;
481 struct ethoc_bd bd;
482
483 ethoc_read_bd(priv, entry, &bd);
484 if (bd.stat & TX_BD_READY)
485 break;
486
487 entry = (++priv->dty_tx) % priv->num_tx;
488 (void)ethoc_update_tx_stats(priv, &bd);
489 }
490
491 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
492 netif_wake_queue(dev);
493
494 ethoc_ack_irq(priv, INT_MASK_TX);
495 spin_unlock(&priv->lock);
496 }
497
498 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
499 {
500 struct net_device *dev = (struct net_device *)dev_id;
501 struct ethoc *priv = netdev_priv(dev);
502 u32 pending;
503
504 ethoc_disable_irq(priv, INT_MASK_ALL);
505 pending = ethoc_read(priv, INT_SOURCE);
506 if (unlikely(pending == 0)) {
507 ethoc_enable_irq(priv, INT_MASK_ALL);
508 return IRQ_NONE;
509 }
510
511 ethoc_ack_irq(priv, INT_MASK_ALL);
512
513 if (pending & INT_MASK_BUSY) {
514 dev_err(&dev->dev, "packet dropped\n");
515 priv->stats.rx_dropped++;
516 }
517
518 if (pending & INT_MASK_RX) {
519 if (napi_schedule_prep(&priv->napi))
520 __napi_schedule(&priv->napi);
521 } else {
522 ethoc_enable_irq(priv, INT_MASK_RX);
523 }
524
525 if (pending & INT_MASK_TX)
526 ethoc_tx(dev);
527
528 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
529 return IRQ_HANDLED;
530 }
531
532 static int ethoc_get_mac_address(struct net_device *dev, void *addr)
533 {
534 struct ethoc *priv = netdev_priv(dev);
535 u8 *mac = (u8 *)addr;
536 u32 reg;
537
538 reg = ethoc_read(priv, MAC_ADDR0);
539 mac[2] = (reg >> 24) & 0xff;
540 mac[3] = (reg >> 16) & 0xff;
541 mac[4] = (reg >> 8) & 0xff;
542 mac[5] = (reg >> 0) & 0xff;
543
544 reg = ethoc_read(priv, MAC_ADDR1);
545 mac[0] = (reg >> 8) & 0xff;
546 mac[1] = (reg >> 0) & 0xff;
547
548 return 0;
549 }
550
551 static int ethoc_poll(struct napi_struct *napi, int budget)
552 {
553 struct ethoc *priv = container_of(napi, struct ethoc, napi);
554 int work_done = 0;
555
556 work_done = ethoc_rx(priv->netdev, budget);
557 if (work_done < budget) {
558 ethoc_enable_irq(priv, INT_MASK_RX);
559 napi_complete(napi);
560 }
561
562 return work_done;
563 }
564
565 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
566 {
567 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
568 struct ethoc *priv = bus->priv;
569
570 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
571 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
572
573 while (time_before(jiffies, timeout)) {
574 u32 status = ethoc_read(priv, MIISTATUS);
575 if (!(status & MIISTATUS_BUSY)) {
576 u32 data = ethoc_read(priv, MIIRX_DATA);
577 /* reset MII command register */
578 ethoc_write(priv, MIICOMMAND, 0);
579 return data;
580 }
581
582 schedule();
583 }
584
585 return -EBUSY;
586 }
587
588 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
589 {
590 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
591 struct ethoc *priv = bus->priv;
592
593 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
594 ethoc_write(priv, MIITX_DATA, val);
595 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
596
597 while (time_before(jiffies, timeout)) {
598 u32 stat = ethoc_read(priv, MIISTATUS);
599 if (!(stat & MIISTATUS_BUSY))
600 return 0;
601
602 schedule();
603 }
604
605 return -EBUSY;
606 }
607
608 static int ethoc_mdio_reset(struct mii_bus *bus)
609 {
610 return 0;
611 }
612
613 static void ethoc_mdio_poll(struct net_device *dev)
614 {
615 }
616
617 static int ethoc_mdio_probe(struct net_device *dev)
618 {
619 struct ethoc *priv = netdev_priv(dev);
620 struct phy_device *phy;
621 int i;
622
623 for (i = 0; i < PHY_MAX_ADDR; i++) {
624 phy = priv->mdio->phy_map[i];
625 if (phy) {
626 if (priv->phy_id != -1) {
627 /* attach to specified PHY */
628 if (priv->phy_id == phy->addr)
629 break;
630 } else {
631 /* autoselect PHY if none was specified */
632 if (phy->addr != 0)
633 break;
634 }
635 }
636 }
637
638 if (!phy) {
639 dev_err(&dev->dev, "no PHY found\n");
640 return -ENXIO;
641 }
642
643 phy = phy_connect(dev, dev_name(&phy->dev), &ethoc_mdio_poll, 0,
644 PHY_INTERFACE_MODE_GMII);
645 if (IS_ERR(phy)) {
646 dev_err(&dev->dev, "could not attach to PHY\n");
647 return PTR_ERR(phy);
648 }
649
650 priv->phy = phy;
651 return 0;
652 }
653
654 static int ethoc_open(struct net_device *dev)
655 {
656 struct ethoc *priv = netdev_priv(dev);
657 unsigned int min_tx = 2;
658 unsigned int num_bd;
659 int ret;
660
661 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
662 dev->name, dev);
663 if (ret)
664 return ret;
665
666 /* calculate the number of TX/RX buffers, maximum 128 supported */
667 num_bd = min_t(unsigned int,
668 128, (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ);
669 priv->num_tx = max(min_tx, num_bd / 4);
670 priv->num_rx = num_bd - priv->num_tx;
671 ethoc_write(priv, TX_BD_NUM, priv->num_tx);
672
673 ethoc_init_ring(priv);
674 ethoc_reset(priv);
675
676 if (netif_queue_stopped(dev)) {
677 dev_dbg(&dev->dev, " resuming queue\n");
678 netif_wake_queue(dev);
679 } else {
680 dev_dbg(&dev->dev, " starting queue\n");
681 netif_start_queue(dev);
682 }
683
684 phy_start(priv->phy);
685 napi_enable(&priv->napi);
686
687 if (netif_msg_ifup(priv)) {
688 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
689 dev->base_addr, dev->mem_start, dev->mem_end);
690 }
691
692 return 0;
693 }
694
695 static int ethoc_stop(struct net_device *dev)
696 {
697 struct ethoc *priv = netdev_priv(dev);
698
699 napi_disable(&priv->napi);
700
701 if (priv->phy)
702 phy_stop(priv->phy);
703
704 ethoc_disable_rx_and_tx(priv);
705 free_irq(dev->irq, dev);
706
707 if (!netif_queue_stopped(dev))
708 netif_stop_queue(dev);
709
710 return 0;
711 }
712
713 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
714 {
715 struct ethoc *priv = netdev_priv(dev);
716 struct mii_ioctl_data *mdio = if_mii(ifr);
717 struct phy_device *phy = NULL;
718
719 if (!netif_running(dev))
720 return -EINVAL;
721
722 if (cmd != SIOCGMIIPHY) {
723 if (mdio->phy_id >= PHY_MAX_ADDR)
724 return -ERANGE;
725
726 phy = priv->mdio->phy_map[mdio->phy_id];
727 if (!phy)
728 return -ENODEV;
729 } else {
730 phy = priv->phy;
731 }
732
733 return phy_mii_ioctl(phy, mdio, cmd);
734 }
735
736 static int ethoc_config(struct net_device *dev, struct ifmap *map)
737 {
738 return -ENOSYS;
739 }
740
741 static int ethoc_set_mac_address(struct net_device *dev, void *addr)
742 {
743 struct ethoc *priv = netdev_priv(dev);
744 u8 *mac = (u8 *)addr;
745
746 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
747 (mac[4] << 8) | (mac[5] << 0));
748 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
749
750 return 0;
751 }
752
753 static void ethoc_set_multicast_list(struct net_device *dev)
754 {
755 struct ethoc *priv = netdev_priv(dev);
756 u32 mode = ethoc_read(priv, MODER);
757 struct dev_mc_list *mc = NULL;
758 u32 hash[2] = { 0, 0 };
759
760 /* set loopback mode if requested */
761 if (dev->flags & IFF_LOOPBACK)
762 mode |= MODER_LOOP;
763 else
764 mode &= ~MODER_LOOP;
765
766 /* receive broadcast frames if requested */
767 if (dev->flags & IFF_BROADCAST)
768 mode &= ~MODER_BRO;
769 else
770 mode |= MODER_BRO;
771
772 /* enable promiscuous mode if requested */
773 if (dev->flags & IFF_PROMISC)
774 mode |= MODER_PRO;
775 else
776 mode &= ~MODER_PRO;
777
778 ethoc_write(priv, MODER, mode);
779
780 /* receive multicast frames */
781 if (dev->flags & IFF_ALLMULTI) {
782 hash[0] = 0xffffffff;
783 hash[1] = 0xffffffff;
784 } else {
785 for (mc = dev->mc_list; mc; mc = mc->next) {
786 u32 crc = ether_crc(mc->dmi_addrlen, mc->dmi_addr);
787 int bit = (crc >> 26) & 0x3f;
788 hash[bit >> 5] |= 1 << (bit & 0x1f);
789 }
790 }
791
792 ethoc_write(priv, ETH_HASH0, hash[0]);
793 ethoc_write(priv, ETH_HASH1, hash[1]);
794 }
795
796 static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
797 {
798 return -ENOSYS;
799 }
800
801 static void ethoc_tx_timeout(struct net_device *dev)
802 {
803 struct ethoc *priv = netdev_priv(dev);
804 u32 pending = ethoc_read(priv, INT_SOURCE);
805 if (likely(pending))
806 ethoc_interrupt(dev->irq, dev);
807 }
808
809 static struct net_device_stats *ethoc_stats(struct net_device *dev)
810 {
811 struct ethoc *priv = netdev_priv(dev);
812 return &priv->stats;
813 }
814
815 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
816 {
817 struct ethoc *priv = netdev_priv(dev);
818 struct ethoc_bd bd;
819 unsigned int entry;
820 void *dest;
821
822 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
823 priv->stats.tx_errors++;
824 goto out;
825 }
826
827 entry = priv->cur_tx % priv->num_tx;
828 spin_lock_irq(&priv->lock);
829 priv->cur_tx++;
830
831 ethoc_read_bd(priv, entry, &bd);
832 if (unlikely(skb->len < ETHOC_ZLEN))
833 bd.stat |= TX_BD_PAD;
834 else
835 bd.stat &= ~TX_BD_PAD;
836
837 dest = phys_to_virt(bd.addr);
838 memcpy_toio(dest, skb->data, skb->len);
839
840 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
841 bd.stat |= TX_BD_LEN(skb->len);
842 ethoc_write_bd(priv, entry, &bd);
843
844 bd.stat |= TX_BD_READY;
845 ethoc_write_bd(priv, entry, &bd);
846
847 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
848 dev_dbg(&dev->dev, "stopping queue\n");
849 netif_stop_queue(dev);
850 }
851
852 dev->trans_start = jiffies;
853 spin_unlock_irq(&priv->lock);
854 out:
855 dev_kfree_skb(skb);
856 return NETDEV_TX_OK;
857 }
858
859 static const struct net_device_ops ethoc_netdev_ops = {
860 .ndo_open = ethoc_open,
861 .ndo_stop = ethoc_stop,
862 .ndo_do_ioctl = ethoc_ioctl,
863 .ndo_set_config = ethoc_config,
864 .ndo_set_mac_address = ethoc_set_mac_address,
865 .ndo_set_multicast_list = ethoc_set_multicast_list,
866 .ndo_change_mtu = ethoc_change_mtu,
867 .ndo_tx_timeout = ethoc_tx_timeout,
868 .ndo_get_stats = ethoc_stats,
869 .ndo_start_xmit = ethoc_start_xmit,
870 };
871
872 /**
873 * ethoc_probe() - initialize OpenCores ethernet MAC
874 * pdev: platform device
875 */
876 static int ethoc_probe(struct platform_device *pdev)
877 {
878 struct net_device *netdev = NULL;
879 struct resource *res = NULL;
880 struct resource *mmio = NULL;
881 struct resource *mem = NULL;
882 struct ethoc *priv = NULL;
883 unsigned int phy;
884 int ret = 0;
885
886 /* allocate networking device */
887 netdev = alloc_etherdev(sizeof(struct ethoc));
888 if (!netdev) {
889 dev_err(&pdev->dev, "cannot allocate network device\n");
890 ret = -ENOMEM;
891 goto out;
892 }
893
894 SET_NETDEV_DEV(netdev, &pdev->dev);
895 platform_set_drvdata(pdev, netdev);
896
897 /* obtain I/O memory space */
898 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
899 if (!res) {
900 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
901 ret = -ENXIO;
902 goto free;
903 }
904
905 mmio = devm_request_mem_region(&pdev->dev, res->start,
906 res->end - res->start + 1, res->name);
907 if (!mmio) {
908 dev_err(&pdev->dev, "cannot request I/O memory space\n");
909 ret = -ENXIO;
910 goto free;
911 }
912
913 netdev->base_addr = mmio->start;
914
915 /* obtain buffer memory space */
916 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
917 if (res) {
918 mem = devm_request_mem_region(&pdev->dev, res->start,
919 res->end - res->start + 1, res->name);
920 if (!mem) {
921 dev_err(&pdev->dev, "cannot request memory space\n");
922 ret = -ENXIO;
923 goto free;
924 }
925
926 netdev->mem_start = mem->start;
927 netdev->mem_end = mem->end;
928 }
929
930
931 /* obtain device IRQ number */
932 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
933 if (!res) {
934 dev_err(&pdev->dev, "cannot obtain IRQ\n");
935 ret = -ENXIO;
936 goto free;
937 }
938
939 netdev->irq = res->start;
940
941 /* setup driver-private data */
942 priv = netdev_priv(netdev);
943 priv->netdev = netdev;
944 priv->dma_alloc = 0;
945
946 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
947 mmio->end - mmio->start + 1);
948 if (!priv->iobase) {
949 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
950 ret = -ENXIO;
951 goto error;
952 }
953
954 if (netdev->mem_end) {
955 priv->membase = devm_ioremap_nocache(&pdev->dev,
956 netdev->mem_start, mem->end - mem->start + 1);
957 if (!priv->membase) {
958 dev_err(&pdev->dev, "cannot remap memory space\n");
959 ret = -ENXIO;
960 goto error;
961 }
962 } else {
963 /* Allocate buffer memory */
964 priv->membase = dma_alloc_coherent(NULL,
965 buffer_size, (void *)&netdev->mem_start,
966 GFP_KERNEL);
967 if (!priv->membase) {
968 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
969 buffer_size);
970 ret = -ENOMEM;
971 goto error;
972 }
973 netdev->mem_end = netdev->mem_start + buffer_size;
974 priv->dma_alloc = buffer_size;
975 }
976
977 /* Allow the platform setup code to pass in a MAC address. */
978 if (pdev->dev.platform_data) {
979 struct ethoc_platform_data *pdata =
980 (struct ethoc_platform_data *)pdev->dev.platform_data;
981 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
982 priv->phy_id = pdata->phy_id;
983 }
984
985 /* Check that the given MAC address is valid. If it isn't, read the
986 * current MAC from the controller. */
987 if (!is_valid_ether_addr(netdev->dev_addr))
988 ethoc_get_mac_address(netdev, netdev->dev_addr);
989
990 /* Check the MAC again for validity, if it still isn't choose and
991 * program a random one. */
992 if (!is_valid_ether_addr(netdev->dev_addr))
993 random_ether_addr(netdev->dev_addr);
994
995 ethoc_set_mac_address(netdev, netdev->dev_addr);
996
997 /* register MII bus */
998 priv->mdio = mdiobus_alloc();
999 if (!priv->mdio) {
1000 ret = -ENOMEM;
1001 goto free;
1002 }
1003
1004 priv->mdio->name = "ethoc-mdio";
1005 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1006 priv->mdio->name, pdev->id);
1007 priv->mdio->read = ethoc_mdio_read;
1008 priv->mdio->write = ethoc_mdio_write;
1009 priv->mdio->reset = ethoc_mdio_reset;
1010 priv->mdio->priv = priv;
1011
1012 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1013 if (!priv->mdio->irq) {
1014 ret = -ENOMEM;
1015 goto free_mdio;
1016 }
1017
1018 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1019 priv->mdio->irq[phy] = PHY_POLL;
1020
1021 ret = mdiobus_register(priv->mdio);
1022 if (ret) {
1023 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1024 goto free_mdio;
1025 }
1026
1027 ret = ethoc_mdio_probe(netdev);
1028 if (ret) {
1029 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1030 goto error;
1031 }
1032
1033 ether_setup(netdev);
1034
1035 /* setup the net_device structure */
1036 netdev->netdev_ops = &ethoc_netdev_ops;
1037 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1038 netdev->features |= 0;
1039
1040 /* setup NAPI */
1041 memset(&priv->napi, 0, sizeof(priv->napi));
1042 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1043
1044 spin_lock_init(&priv->rx_lock);
1045 spin_lock_init(&priv->lock);
1046
1047 ret = register_netdev(netdev);
1048 if (ret < 0) {
1049 dev_err(&netdev->dev, "failed to register interface\n");
1050 goto error;
1051 }
1052
1053 goto out;
1054
1055 error:
1056 mdiobus_unregister(priv->mdio);
1057 free_mdio:
1058 kfree(priv->mdio->irq);
1059 mdiobus_free(priv->mdio);
1060 free:
1061 if (priv->dma_alloc)
1062 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1063 netdev->mem_start);
1064 free_netdev(netdev);
1065 out:
1066 return ret;
1067 }
1068
1069 /**
1070 * ethoc_remove() - shutdown OpenCores ethernet MAC
1071 * @pdev: platform device
1072 */
1073 static int ethoc_remove(struct platform_device *pdev)
1074 {
1075 struct net_device *netdev = platform_get_drvdata(pdev);
1076 struct ethoc *priv = netdev_priv(netdev);
1077
1078 platform_set_drvdata(pdev, NULL);
1079
1080 if (netdev) {
1081 phy_disconnect(priv->phy);
1082 priv->phy = NULL;
1083
1084 if (priv->mdio) {
1085 mdiobus_unregister(priv->mdio);
1086 kfree(priv->mdio->irq);
1087 mdiobus_free(priv->mdio);
1088 }
1089 if (priv->dma_alloc)
1090 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1091 netdev->mem_start);
1092 unregister_netdev(netdev);
1093 free_netdev(netdev);
1094 }
1095
1096 return 0;
1097 }
1098
1099 #ifdef CONFIG_PM
1100 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1101 {
1102 return -ENOSYS;
1103 }
1104
1105 static int ethoc_resume(struct platform_device *pdev)
1106 {
1107 return -ENOSYS;
1108 }
1109 #else
1110 # define ethoc_suspend NULL
1111 # define ethoc_resume NULL
1112 #endif
1113
1114 static struct platform_driver ethoc_driver = {
1115 .probe = ethoc_probe,
1116 .remove = ethoc_remove,
1117 .suspend = ethoc_suspend,
1118 .resume = ethoc_resume,
1119 .driver = {
1120 .name = "ethoc",
1121 },
1122 };
1123
1124 static int __init ethoc_init(void)
1125 {
1126 return platform_driver_register(&ethoc_driver);
1127 }
1128
1129 static void __exit ethoc_exit(void)
1130 {
1131 platform_driver_unregister(&ethoc_driver);
1132 }
1133
1134 module_init(ethoc_init);
1135 module_exit(ethoc_exit);
1136
1137 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1138 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1139 MODULE_LICENSE("GPL v2");
1140
Verdex Pro support