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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / r6040.c
blob7dfcb58b0eb42d807f401b69b37499b059c8ef08
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/mii.h>
41 #include <linux/ethtool.h>
42 #include <linux/crc32.h>
43 #include <linux/spinlock.h>
44 #include <linux/bitops.h>
45 #include <linux/io.h>
46 #include <linux/irq.h>
47 #include <linux/uaccess.h>
48
49 #include <asm/processor.h>
50
51 #define DRV_NAME "r6040"
52 #define DRV_VERSION "0.25"
53 #define DRV_RELDATE "20Aug2009"
54
55 /* PHY CHIP Address */
56 #define PHY1_ADDR 1 /* For MAC1 */
57 #define PHY2_ADDR 3 /* For MAC2 */
58 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
59 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
60
61 /* Time in jiffies before concluding the transmitter is hung. */
62 #define TX_TIMEOUT (6000 * HZ / 1000)
63
64 /* RDC MAC I/O Size */
65 #define R6040_IO_SIZE 256
66
67 /* MAX RDC MAC */
68 #define MAX_MAC 2
69
70 /* MAC registers */
71 #define MCR0 0x00 /* Control register 0 */
72 #define MCR1 0x04 /* Control register 1 */
73 #define MAC_RST 0x0001 /* Reset the MAC */
74 #define MBCR 0x08 /* Bus control */
75 #define MT_ICR 0x0C /* TX interrupt control */
76 #define MR_ICR 0x10 /* RX interrupt control */
77 #define MTPR 0x14 /* TX poll command register */
78 #define MR_BSR 0x18 /* RX buffer size */
79 #define MR_DCR 0x1A /* RX descriptor control */
80 #define MLSR 0x1C /* Last status */
81 #define MMDIO 0x20 /* MDIO control register */
82 #define MDIO_WRITE 0x4000 /* MDIO write */
83 #define MDIO_READ 0x2000 /* MDIO read */
84 #define MMRD 0x24 /* MDIO read data register */
85 #define MMWD 0x28 /* MDIO write data register */
86 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
87 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
88 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
89 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
90 #define MISR 0x3C /* Status register */
91 #define MIER 0x40 /* INT enable register */
92 #define MSK_INT 0x0000 /* Mask off interrupts */
93 #define RX_FINISH 0x0001 /* RX finished */
94 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
95 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
96 #define RX_EARLY 0x0008 /* RX early */
97 #define TX_FINISH 0x0010 /* TX finished */
98 #define TX_EARLY 0x0080 /* TX early */
99 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
100 #define LINK_CHANGED 0x0200 /* PHY link changed */
101 #define ME_CISR 0x44 /* Event counter INT status */
102 #define ME_CIER 0x48 /* Event counter INT enable */
103 #define MR_CNT 0x50 /* Successfully received packet counter */
104 #define ME_CNT0 0x52 /* Event counter 0 */
105 #define ME_CNT1 0x54 /* Event counter 1 */
106 #define ME_CNT2 0x56 /* Event counter 2 */
107 #define ME_CNT3 0x58 /* Event counter 3 */
108 #define MT_CNT 0x5A /* Successfully transmit packet counter */
109 #define ME_CNT4 0x5C /* Event counter 4 */
110 #define MP_CNT 0x5E /* Pause frame counter register */
111 #define MAR0 0x60 /* Hash table 0 */
112 #define MAR1 0x62 /* Hash table 1 */
113 #define MAR2 0x64 /* Hash table 2 */
114 #define MAR3 0x66 /* Hash table 3 */
115 #define MID_0L 0x68 /* Multicast address MID0 Low */
116 #define MID_0M 0x6A /* Multicast address MID0 Medium */
117 #define MID_0H 0x6C /* Multicast address MID0 High */
118 #define MID_1L 0x70 /* MID1 Low */
119 #define MID_1M 0x72 /* MID1 Medium */
120 #define MID_1H 0x74 /* MID1 High */
121 #define MID_2L 0x78 /* MID2 Low */
122 #define MID_2M 0x7A /* MID2 Medium */
123 #define MID_2H 0x7C /* MID2 High */
124 #define MID_3L 0x80 /* MID3 Low */
125 #define MID_3M 0x82 /* MID3 Medium */
126 #define MID_3H 0x84 /* MID3 High */
127 #define PHY_CC 0x88 /* PHY status change configuration register */
128 #define PHY_ST 0x8A /* PHY status register */
129 #define MAC_SM 0xAC /* MAC status machine */
130 #define MAC_ID 0xBE /* Identifier register */
131
132 #define TX_DCNT 0x80 /* TX descriptor count */
133 #define RX_DCNT 0x80 /* RX descriptor count */
134 #define MAX_BUF_SIZE 0x600
135 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
136 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
137 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
138 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
139
140 /* Descriptor status */
141 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
142 #define DSC_RX_OK 0x4000 /* RX was successful */
143 #define DSC_RX_ERR 0x0800 /* RX PHY error */
144 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
145 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
146 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
147 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
148 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
149 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
150 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
151 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
152 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
153 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154
155 /* PHY settings */
156 #define ICPLUS_PHY_ID 0x0243
157
158 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
159 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
160 "Florian Fainelli <florian@openwrt.org>");
161 MODULE_LICENSE("GPL");
162 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
163 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
164
165 /* RX and TX interrupts that we handle */
166 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
167 #define TX_INTS (TX_FINISH)
168 #define INT_MASK (RX_INTS | TX_INTS)
169
170 struct r6040_descriptor {
171 u16 status, len; /* 0-3 */
172 __le32 buf; /* 4-7 */
173 __le32 ndesc; /* 8-B */
174 u32 rev1; /* C-F */
175 char *vbufp; /* 10-13 */
176 struct r6040_descriptor *vndescp; /* 14-17 */
177 struct sk_buff *skb_ptr; /* 18-1B */
178 u32 rev2; /* 1C-1F */
179 } __attribute__((aligned(32)));
180
181 struct r6040_private {
182 spinlock_t lock; /* driver lock */
183 struct timer_list timer;
184 struct pci_dev *pdev;
185 struct r6040_descriptor *rx_insert_ptr;
186 struct r6040_descriptor *rx_remove_ptr;
187 struct r6040_descriptor *tx_insert_ptr;
188 struct r6040_descriptor *tx_remove_ptr;
189 struct r6040_descriptor *rx_ring;
190 struct r6040_descriptor *tx_ring;
191 dma_addr_t rx_ring_dma;
192 dma_addr_t tx_ring_dma;
193 u16 tx_free_desc, phy_addr, phy_mode;
194 u16 mcr0, mcr1;
195 u16 switch_sig;
196 struct net_device *dev;
197 struct mii_if_info mii_if;
198 struct napi_struct napi;
199 void __iomem *base;
200 };
201
202 static char version[] __devinitdata = KERN_INFO DRV_NAME
203 ": RDC R6040 NAPI net driver,"
204 "version "DRV_VERSION " (" DRV_RELDATE ")";
205
206 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
207
208 /* Read a word data from PHY Chip */
209 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
210 {
211 int limit = 2048;
212 u16 cmd;
213
214 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
215 /* Wait for the read bit to be cleared */
216 while (limit--) {
217 cmd = ioread16(ioaddr + MMDIO);
218 if (!(cmd & MDIO_READ))
219 break;
220 }
221
222 return ioread16(ioaddr + MMRD);
223 }
224
225 /* Write a word data from PHY Chip */
226 static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
227 {
228 int limit = 2048;
229 u16 cmd;
230
231 iowrite16(val, ioaddr + MMWD);
232 /* Write the command to the MDIO bus */
233 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
234 /* Wait for the write bit to be cleared */
235 while (limit--) {
236 cmd = ioread16(ioaddr + MMDIO);
237 if (!(cmd & MDIO_WRITE))
238 break;
239 }
240 }
241
242 static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
243 {
244 struct r6040_private *lp = netdev_priv(dev);
245 void __iomem *ioaddr = lp->base;
246
247 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
248 }
249
250 static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
251 {
252 struct r6040_private *lp = netdev_priv(dev);
253 void __iomem *ioaddr = lp->base;
254
255 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
256 }
257
258 static void r6040_free_txbufs(struct net_device *dev)
259 {
260 struct r6040_private *lp = netdev_priv(dev);
261 int i;
262
263 for (i = 0; i < TX_DCNT; i++) {
264 if (lp->tx_insert_ptr->skb_ptr) {
265 pci_unmap_single(lp->pdev,
266 le32_to_cpu(lp->tx_insert_ptr->buf),
267 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
268 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
269 lp->tx_insert_ptr->skb_ptr = NULL;
270 }
271 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
272 }
273 }
274
275 static void r6040_free_rxbufs(struct net_device *dev)
276 {
277 struct r6040_private *lp = netdev_priv(dev);
278 int i;
279
280 for (i = 0; i < RX_DCNT; i++) {
281 if (lp->rx_insert_ptr->skb_ptr) {
282 pci_unmap_single(lp->pdev,
283 le32_to_cpu(lp->rx_insert_ptr->buf),
284 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
285 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
286 lp->rx_insert_ptr->skb_ptr = NULL;
287 }
288 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
289 }
290 }
291
292 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
293 dma_addr_t desc_dma, int size)
294 {
295 struct r6040_descriptor *desc = desc_ring;
296 dma_addr_t mapping = desc_dma;
297
298 while (size-- > 0) {
299 mapping += sizeof(*desc);
300 desc->ndesc = cpu_to_le32(mapping);
301 desc->vndescp = desc + 1;
302 desc++;
303 }
304 desc--;
305 desc->ndesc = cpu_to_le32(desc_dma);
306 desc->vndescp = desc_ring;
307 }
308
309 static void r6040_init_txbufs(struct net_device *dev)
310 {
311 struct r6040_private *lp = netdev_priv(dev);
312
313 lp->tx_free_desc = TX_DCNT;
314
315 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
316 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
317 }
318
319 static int r6040_alloc_rxbufs(struct net_device *dev)
320 {
321 struct r6040_private *lp = netdev_priv(dev);
322 struct r6040_descriptor *desc;
323 struct sk_buff *skb;
324 int rc;
325
326 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
327 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
328
329 /* Allocate skbs for the rx descriptors */
330 desc = lp->rx_ring;
331 do {
332 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
333 if (!skb) {
334 printk(KERN_ERR DRV_NAME "%s: failed to alloc skb for rx\n", dev->name);
335 rc = -ENOMEM;
336 goto err_exit;
337 }
338 desc->skb_ptr = skb;
339 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
340 desc->skb_ptr->data,
341 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
342 desc->status = DSC_OWNER_MAC;
343 desc = desc->vndescp;
344 } while (desc != lp->rx_ring);
345
346 return 0;
347
348 err_exit:
349 /* Deallocate all previously allocated skbs */
350 r6040_free_rxbufs(dev);
351 return rc;
352 }
353
354 static void r6040_init_mac_regs(struct net_device *dev)
355 {
356 struct r6040_private *lp = netdev_priv(dev);
357 void __iomem *ioaddr = lp->base;
358 int limit = 2048;
359 u16 cmd;
360
361 /* Mask Off Interrupt */
362 iowrite16(MSK_INT, ioaddr + MIER);
363
364 /* Reset RDC MAC */
365 iowrite16(MAC_RST, ioaddr + MCR1);
366 while (limit--) {
367 cmd = ioread16(ioaddr + MCR1);
368 if (cmd & 0x1)
369 break;
370 }
371 /* Reset internal state machine */
372 iowrite16(2, ioaddr + MAC_SM);
373 iowrite16(0, ioaddr + MAC_SM);
374 mdelay(5);
375
376 /* MAC Bus Control Register */
377 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
378
379 /* Buffer Size Register */
380 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
381
382 /* Write TX ring start address */
383 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
384 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
385
386 /* Write RX ring start address */
387 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
388 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
389
390 /* Set interrupt waiting time and packet numbers */
391 iowrite16(0, ioaddr + MT_ICR);
392 iowrite16(0, ioaddr + MR_ICR);
393
394 /* Enable interrupts */
395 iowrite16(INT_MASK, ioaddr + MIER);
396
397 /* Enable TX and RX */
398 iowrite16(lp->mcr0 | 0x0002, ioaddr);
399
400 /* Let TX poll the descriptors
401 * we may got called by r6040_tx_timeout which has left
402 * some unsent tx buffers */
403 iowrite16(0x01, ioaddr + MTPR);
404
405 /* Check media */
406 mii_check_media(&lp->mii_if, 1, 1);
407 }
408
409 static void r6040_tx_timeout(struct net_device *dev)
410 {
411 struct r6040_private *priv = netdev_priv(dev);
412 void __iomem *ioaddr = priv->base;
413
414 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
415 "status %4.4x, PHY status %4.4x\n",
416 dev->name, ioread16(ioaddr + MIER),
417 ioread16(ioaddr + MISR),
418 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
419
420 dev->stats.tx_errors++;
421
422 /* Reset MAC and re-init all registers */
423 r6040_init_mac_regs(dev);
424 }
425
426 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
427 {
428 struct r6040_private *priv = netdev_priv(dev);
429 void __iomem *ioaddr = priv->base;
430 unsigned long flags;
431
432 spin_lock_irqsave(&priv->lock, flags);
433 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
434 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
435 spin_unlock_irqrestore(&priv->lock, flags);
436
437 return &dev->stats;
438 }
439
440 /* Stop RDC MAC and Free the allocated resource */
441 static void r6040_down(struct net_device *dev)
442 {
443 struct r6040_private *lp = netdev_priv(dev);
444 void __iomem *ioaddr = lp->base;
445 int limit = 2048;
446 u16 *adrp;
447 u16 cmd;
448
449 /* Stop MAC */
450 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
451 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
452 while (limit--) {
453 cmd = ioread16(ioaddr + MCR1);
454 if (cmd & 0x1)
455 break;
456 }
457
458 /* Restore MAC Address to MIDx */
459 adrp = (u16 *) dev->dev_addr;
460 iowrite16(adrp[0], ioaddr + MID_0L);
461 iowrite16(adrp[1], ioaddr + MID_0M);
462 iowrite16(adrp[2], ioaddr + MID_0H);
463 }
464
465 static int r6040_close(struct net_device *dev)
466 {
467 struct r6040_private *lp = netdev_priv(dev);
468 struct pci_dev *pdev = lp->pdev;
469
470 /* deleted timer */
471 del_timer_sync(&lp->timer);
472
473 spin_lock_irq(&lp->lock);
474 napi_disable(&lp->napi);
475 netif_stop_queue(dev);
476 r6040_down(dev);
477
478 free_irq(dev->irq, dev);
479
480 /* Free RX buffer */
481 r6040_free_rxbufs(dev);
482
483 /* Free TX buffer */
484 r6040_free_txbufs(dev);
485
486 spin_unlock_irq(&lp->lock);
487
488 /* Free Descriptor memory */
489 if (lp->rx_ring) {
490 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
491 lp->rx_ring = NULL;
492 }
493
494 if (lp->tx_ring) {
495 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
496 lp->tx_ring = NULL;
497 }
498
499 return 0;
500 }
501
502 /* Status of PHY CHIP */
503 static int r6040_phy_mode_chk(struct net_device *dev)
504 {
505 struct r6040_private *lp = netdev_priv(dev);
506 void __iomem *ioaddr = lp->base;
507 int phy_dat;
508
509 /* PHY Link Status Check */
510 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
511 if (!(phy_dat & 0x4))
512 phy_dat = 0x8000; /* Link Failed, full duplex */
513
514 /* PHY Chip Auto-Negotiation Status */
515 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
516 if (phy_dat & 0x0020) {
517 /* Auto Negotiation Mode */
518 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
519 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
520 if (phy_dat & 0x140)
521 /* Force full duplex */
522 phy_dat = 0x8000;
523 else
524 phy_dat = 0;
525 } else {
526 /* Force Mode */
527 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
528 if (phy_dat & 0x100)
529 phy_dat = 0x8000;
530 else
531 phy_dat = 0x0000;
532 }
533
534 mii_check_media(&lp->mii_if, 0, 1);
535
536 return phy_dat;
537 };
538
539 static void r6040_set_carrier(struct mii_if_info *mii)
540 {
541 if (r6040_phy_mode_chk(mii->dev)) {
542 /* autoneg is off: Link is always assumed to be up */
543 if (!netif_carrier_ok(mii->dev))
544 netif_carrier_on(mii->dev);
545 } else
546 r6040_phy_mode_chk(mii->dev);
547 }
548
549 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
550 {
551 struct r6040_private *lp = netdev_priv(dev);
552 struct mii_ioctl_data *data = if_mii(rq);
553 int rc;
554
555 if (!netif_running(dev))
556 return -EINVAL;
557 spin_lock_irq(&lp->lock);
558 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
559 spin_unlock_irq(&lp->lock);
560 r6040_set_carrier(&lp->mii_if);
561 return rc;
562 }
563
564 static int r6040_rx(struct net_device *dev, int limit)
565 {
566 struct r6040_private *priv = netdev_priv(dev);
567 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
568 struct sk_buff *skb_ptr, *new_skb;
569 int count = 0;
570 u16 err;
571
572 /* Limit not reached and the descriptor belongs to the CPU */
573 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
574 /* Read the descriptor status */
575 err = descptr->status;
576 /* Global error status set */
577 if (err & DSC_RX_ERR) {
578 /* RX dribble */
579 if (err & DSC_RX_ERR_DRI)
580 dev->stats.rx_frame_errors++;
581 /* Buffer lenght exceeded */
582 if (err & DSC_RX_ERR_BUF)
583 dev->stats.rx_length_errors++;
584 /* Packet too long */
585 if (err & DSC_RX_ERR_LONG)
586 dev->stats.rx_length_errors++;
587 /* Packet < 64 bytes */
588 if (err & DSC_RX_ERR_RUNT)
589 dev->stats.rx_length_errors++;
590 /* CRC error */
591 if (err & DSC_RX_ERR_CRC) {
592 spin_lock(&priv->lock);
593 dev->stats.rx_crc_errors++;
594 spin_unlock(&priv->lock);
595 }
596 goto next_descr;
597 }
598
599 /* Packet successfully received */
600 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
601 if (!new_skb) {
602 dev->stats.rx_dropped++;
603 goto next_descr;
604 }
605 skb_ptr = descptr->skb_ptr;
606 skb_ptr->dev = priv->dev;
607
608 /* Do not count the CRC */
609 skb_put(skb_ptr, descptr->len - 4);
610 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
611 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
612 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
613
614 /* Send to upper layer */
615 netif_receive_skb(skb_ptr);
616 dev->stats.rx_packets++;
617 dev->stats.rx_bytes += descptr->len - 4;
618
619 /* put new skb into descriptor */
620 descptr->skb_ptr = new_skb;
621 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
622 descptr->skb_ptr->data,
623 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
624
625 next_descr:
626 /* put the descriptor back to the MAC */
627 descptr->status = DSC_OWNER_MAC;
628 descptr = descptr->vndescp;
629 count++;
630 }
631 priv->rx_remove_ptr = descptr;
632
633 return count;
634 }
635
636 static void r6040_tx(struct net_device *dev)
637 {
638 struct r6040_private *priv = netdev_priv(dev);
639 struct r6040_descriptor *descptr;
640 void __iomem *ioaddr = priv->base;
641 struct sk_buff *skb_ptr;
642 u16 err;
643
644 spin_lock(&priv->lock);
645 descptr = priv->tx_remove_ptr;
646 while (priv->tx_free_desc < TX_DCNT) {
647 /* Check for errors */
648 err = ioread16(ioaddr + MLSR);
649
650 if (err & 0x0200)
651 dev->stats.rx_fifo_errors++;
652 if (err & (0x2000 | 0x4000))
653 dev->stats.tx_carrier_errors++;
654
655 if (descptr->status & DSC_OWNER_MAC)
656 break; /* Not complete */
657 skb_ptr = descptr->skb_ptr;
658 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
659 skb_ptr->len, PCI_DMA_TODEVICE);
660 /* Free buffer */
661 dev_kfree_skb_irq(skb_ptr);
662 descptr->skb_ptr = NULL;
663 /* To next descriptor */
664 descptr = descptr->vndescp;
665 priv->tx_free_desc++;
666 }
667 priv->tx_remove_ptr = descptr;
668
669 if (priv->tx_free_desc)
670 netif_wake_queue(dev);
671 spin_unlock(&priv->lock);
672 }
673
674 static int r6040_poll(struct napi_struct *napi, int budget)
675 {
676 struct r6040_private *priv =
677 container_of(napi, struct r6040_private, napi);
678 struct net_device *dev = priv->dev;
679 void __iomem *ioaddr = priv->base;
680 int work_done;
681
682 work_done = r6040_rx(dev, budget);
683
684 if (work_done < budget) {
685 napi_complete(napi);
686 /* Enable RX interrupt */
687 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
688 }
689 return work_done;
690 }
691
692 /* The RDC interrupt handler. */
693 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
694 {
695 struct net_device *dev = dev_id;
696 struct r6040_private *lp = netdev_priv(dev);
697 void __iomem *ioaddr = lp->base;
698 u16 misr, status;
699
700 /* Save MIER */
701 misr = ioread16(ioaddr + MIER);
702 /* Mask off RDC MAC interrupt */
703 iowrite16(MSK_INT, ioaddr + MIER);
704 /* Read MISR status and clear */
705 status = ioread16(ioaddr + MISR);
706
707 if (status == 0x0000 || status == 0xffff) {
708 /* Restore RDC MAC interrupt */
709 iowrite16(misr, ioaddr + MIER);
710 return IRQ_NONE;
711 }
712
713 /* RX interrupt request */
714 if (status & RX_INTS) {
715 if (status & RX_NO_DESC) {
716 /* RX descriptor unavailable */
717 dev->stats.rx_dropped++;
718 dev->stats.rx_missed_errors++;
719 }
720 if (status & RX_FIFO_FULL)
721 dev->stats.rx_fifo_errors++;
722
723 /* Mask off RX interrupt */
724 misr &= ~RX_INTS;
725 napi_schedule(&lp->napi);
726 }
727
728 /* TX interrupt request */
729 if (status & TX_INTS)
730 r6040_tx(dev);
731
732 /* Restore RDC MAC interrupt */
733 iowrite16(misr, ioaddr + MIER);
734
735 return IRQ_HANDLED;
736 }
737
738 #ifdef CONFIG_NET_POLL_CONTROLLER
739 static void r6040_poll_controller(struct net_device *dev)
740 {
741 disable_irq(dev->irq);
742 r6040_interrupt(dev->irq, dev);
743 enable_irq(dev->irq);
744 }
745 #endif
746
747 /* Init RDC MAC */
748 static int r6040_up(struct net_device *dev)
749 {
750 struct r6040_private *lp = netdev_priv(dev);
751 void __iomem *ioaddr = lp->base;
752 int ret;
753
754 /* Initialise and alloc RX/TX buffers */
755 r6040_init_txbufs(dev);
756 ret = r6040_alloc_rxbufs(dev);
757 if (ret)
758 return ret;
759
760 /* Read the PHY ID */
761 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
762
763 if (lp->switch_sig == ICPLUS_PHY_ID) {
764 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
765 lp->phy_mode = 0x8000;
766 } else {
767 /* PHY Mode Check */
768 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
769 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
770
771 if (PHY_MODE == 0x3100)
772 lp->phy_mode = r6040_phy_mode_chk(dev);
773 else
774 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
775 }
776
777 /* Set duplex mode */
778 lp->mcr0 |= lp->phy_mode;
779
780 /* improve performance (by RDC guys) */
781 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
782 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
783 r6040_phy_write(ioaddr, 0, 19, 0x0000);
784 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
785
786 /* Initialize all MAC registers */
787 r6040_init_mac_regs(dev);
788
789 return 0;
790 }
791
792 /*
793 A periodic timer routine
794 Polling PHY Chip Link Status
795 */
796 static void r6040_timer(unsigned long data)
797 {
798 struct net_device *dev = (struct net_device *)data;
799 struct r6040_private *lp = netdev_priv(dev);
800 void __iomem *ioaddr = lp->base;
801 u16 phy_mode;
802
803 /* Polling PHY Chip Status */
804 if (PHY_MODE == 0x3100)
805 phy_mode = r6040_phy_mode_chk(dev);
806 else
807 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
808
809 if (phy_mode != lp->phy_mode) {
810 lp->phy_mode = phy_mode;
811 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
812 iowrite16(lp->mcr0, ioaddr);
813 }
814
815 /* Timer active again */
816 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
817 }
818
819 /* Read/set MAC address routines */
820 static void r6040_mac_address(struct net_device *dev)
821 {
822 struct r6040_private *lp = netdev_priv(dev);
823 void __iomem *ioaddr = lp->base;
824 u16 *adrp;
825
826 /* MAC operation register */
827 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
828 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
829 iowrite16(0, ioaddr + MAC_SM);
830 mdelay(5);
831
832 /* Restore MAC Address */
833 adrp = (u16 *) dev->dev_addr;
834 iowrite16(adrp[0], ioaddr + MID_0L);
835 iowrite16(adrp[1], ioaddr + MID_0M);
836 iowrite16(adrp[2], ioaddr + MID_0H);
837 }
838
839 static int r6040_open(struct net_device *dev)
840 {
841 struct r6040_private *lp = netdev_priv(dev);
842 int ret;
843
844 /* Request IRQ and Register interrupt handler */
845 ret = request_irq(dev->irq, &r6040_interrupt,
846 IRQF_SHARED, dev->name, dev);
847 if (ret)
848 return ret;
849
850 /* Set MAC address */
851 r6040_mac_address(dev);
852
853 /* Allocate Descriptor memory */
854 lp->rx_ring =
855 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
856 if (!lp->rx_ring)
857 return -ENOMEM;
858
859 lp->tx_ring =
860 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
861 if (!lp->tx_ring) {
862 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
863 lp->rx_ring_dma);
864 return -ENOMEM;
865 }
866
867 ret = r6040_up(dev);
868 if (ret) {
869 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
870 lp->tx_ring_dma);
871 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
872 lp->rx_ring_dma);
873 return ret;
874 }
875
876 napi_enable(&lp->napi);
877 netif_start_queue(dev);
878
879 /* set and active a timer process */
880 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
881 if (lp->switch_sig != ICPLUS_PHY_ID)
882 mod_timer(&lp->timer, jiffies + HZ);
883 return 0;
884 }
885
886 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
887 struct net_device *dev)
888 {
889 struct r6040_private *lp = netdev_priv(dev);
890 struct r6040_descriptor *descptr;
891 void __iomem *ioaddr = lp->base;
892 unsigned long flags;
893
894 /* Critical Section */
895 spin_lock_irqsave(&lp->lock, flags);
896
897 /* TX resource check */
898 if (!lp->tx_free_desc) {
899 spin_unlock_irqrestore(&lp->lock, flags);
900 netif_stop_queue(dev);
901 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
902 return NETDEV_TX_BUSY;
903 }
904
905 /* Statistic Counter */
906 dev->stats.tx_packets++;
907 dev->stats.tx_bytes += skb->len;
908 /* Set TX descriptor & Transmit it */
909 lp->tx_free_desc--;
910 descptr = lp->tx_insert_ptr;
911 if (skb->len < MISR)
912 descptr->len = MISR;
913 else
914 descptr->len = skb->len;
915
916 descptr->skb_ptr = skb;
917 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
918 skb->data, skb->len, PCI_DMA_TODEVICE));
919 descptr->status = DSC_OWNER_MAC;
920 /* Trigger the MAC to check the TX descriptor */
921 iowrite16(0x01, ioaddr + MTPR);
922 lp->tx_insert_ptr = descptr->vndescp;
923
924 /* If no tx resource, stop */
925 if (!lp->tx_free_desc)
926 netif_stop_queue(dev);
927
928 dev->trans_start = jiffies;
929 spin_unlock_irqrestore(&lp->lock, flags);
930
931 return NETDEV_TX_OK;
932 }
933
934 static void r6040_multicast_list(struct net_device *dev)
935 {
936 struct r6040_private *lp = netdev_priv(dev);
937 void __iomem *ioaddr = lp->base;
938 u16 *adrp;
939 u16 reg;
940 unsigned long flags;
941 struct dev_mc_list *dmi = dev->mc_list;
942 int i;
943
944 /* MAC Address */
945 adrp = (u16 *)dev->dev_addr;
946 iowrite16(adrp[0], ioaddr + MID_0L);
947 iowrite16(adrp[1], ioaddr + MID_0M);
948 iowrite16(adrp[2], ioaddr + MID_0H);
949
950 /* Promiscous Mode */
951 spin_lock_irqsave(&lp->lock, flags);
952
953 /* Clear AMCP & PROM bits */
954 reg = ioread16(ioaddr) & ~0x0120;
955 if (dev->flags & IFF_PROMISC) {
956 reg |= 0x0020;
957 lp->mcr0 |= 0x0020;
958 }
959 /* Too many multicast addresses
960 * accept all traffic */
961 else if ((dev->mc_count > MCAST_MAX)
962 || (dev->flags & IFF_ALLMULTI))
963 reg |= 0x0020;
964
965 iowrite16(reg, ioaddr);
966 spin_unlock_irqrestore(&lp->lock, flags);
967
968 /* Build the hash table */
969 if (dev->mc_count > MCAST_MAX) {
970 u16 hash_table[4];
971 u32 crc;
972
973 for (i = 0; i < 4; i++)
974 hash_table[i] = 0;
975
976 for (i = 0; i < dev->mc_count; i++) {
977 char *addrs = dmi->dmi_addr;
978
979 dmi = dmi->next;
980
981 if (!(*addrs & 1))
982 continue;
983
984 crc = ether_crc_le(6, addrs);
985 crc >>= 26;
986 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
987 }
988 /* Write the index of the hash table */
989 for (i = 0; i < 4; i++)
990 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
991 /* Fill the MAC hash tables with their values */
992 iowrite16(hash_table[0], ioaddr + MAR0);
993 iowrite16(hash_table[1], ioaddr + MAR1);
994 iowrite16(hash_table[2], ioaddr + MAR2);
995 iowrite16(hash_table[3], ioaddr + MAR3);
996 }
997 /* Multicast Address 1~4 case */
998 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
999 adrp = (u16 *)dmi->dmi_addr;
1000 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
1001 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
1002 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
1003 dmi = dmi->next;
1004 }
1005 for (i = dev->mc_count; i < MCAST_MAX; i++) {
1006 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
1007 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
1008 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
1009 }
1010 }
1011
1012 static void netdev_get_drvinfo(struct net_device *dev,
1013 struct ethtool_drvinfo *info)
1014 {
1015 struct r6040_private *rp = netdev_priv(dev);
1016
1017 strcpy(info->driver, DRV_NAME);
1018 strcpy(info->version, DRV_VERSION);
1019 strcpy(info->bus_info, pci_name(rp->pdev));
1020 }
1021
1022 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1023 {
1024 struct r6040_private *rp = netdev_priv(dev);
1025 int rc;
1026
1027 spin_lock_irq(&rp->lock);
1028 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1029 spin_unlock_irq(&rp->lock);
1030
1031 return rc;
1032 }
1033
1034 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1035 {
1036 struct r6040_private *rp = netdev_priv(dev);
1037 int rc;
1038
1039 spin_lock_irq(&rp->lock);
1040 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1041 spin_unlock_irq(&rp->lock);
1042 r6040_set_carrier(&rp->mii_if);
1043
1044 return rc;
1045 }
1046
1047 static u32 netdev_get_link(struct net_device *dev)
1048 {
1049 struct r6040_private *rp = netdev_priv(dev);
1050
1051 return mii_link_ok(&rp->mii_if);
1052 }
1053
1054 static const struct ethtool_ops netdev_ethtool_ops = {
1055 .get_drvinfo = netdev_get_drvinfo,
1056 .get_settings = netdev_get_settings,
1057 .set_settings = netdev_set_settings,
1058 .get_link = netdev_get_link,
1059 };
1060
1061 static const struct net_device_ops r6040_netdev_ops = {
1062 .ndo_open = r6040_open,
1063 .ndo_stop = r6040_close,
1064 .ndo_start_xmit = r6040_start_xmit,
1065 .ndo_get_stats = r6040_get_stats,
1066 .ndo_set_multicast_list = r6040_multicast_list,
1067 .ndo_change_mtu = eth_change_mtu,
1068 .ndo_validate_addr = eth_validate_addr,
1069 .ndo_set_mac_address = eth_mac_addr,
1070 .ndo_do_ioctl = r6040_ioctl,
1071 .ndo_tx_timeout = r6040_tx_timeout,
1072 #ifdef CONFIG_NET_POLL_CONTROLLER
1073 .ndo_poll_controller = r6040_poll_controller,
1074 #endif
1075 };
1076
1077 static int __devinit r6040_init_one(struct pci_dev *pdev,
1078 const struct pci_device_id *ent)
1079 {
1080 struct net_device *dev;
1081 struct r6040_private *lp;
1082 void __iomem *ioaddr;
1083 int err, io_size = R6040_IO_SIZE;
1084 static int card_idx = -1;
1085 int bar = 0;
1086 u16 *adrp;
1087
1088 printk(KERN_INFO "%s\n", version);
1089
1090 err = pci_enable_device(pdev);
1091 if (err)
1092 goto err_out;
1093
1094 /* this should always be supported */
1095 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1096 if (err) {
1097 printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
1098 "not supported by the card\n");
1099 goto err_out;
1100 }
1101 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1102 if (err) {
1103 printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
1104 "not supported by the card\n");
1105 goto err_out;
1106 }
1107
1108 /* IO Size check */
1109 if (pci_resource_len(pdev, bar) < io_size) {
1110 printk(KERN_ERR DRV_NAME ": Insufficient PCI resources, aborting\n");
1111 err = -EIO;
1112 goto err_out;
1113 }
1114
1115 pci_set_master(pdev);
1116
1117 dev = alloc_etherdev(sizeof(struct r6040_private));
1118 if (!dev) {
1119 printk(KERN_ERR DRV_NAME ": Failed to allocate etherdev\n");
1120 err = -ENOMEM;
1121 goto err_out;
1122 }
1123 SET_NETDEV_DEV(dev, &pdev->dev);
1124 lp = netdev_priv(dev);
1125
1126 err = pci_request_regions(pdev, DRV_NAME);
1127
1128 if (err) {
1129 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1130 goto err_out_free_dev;
1131 }
1132
1133 ioaddr = pci_iomap(pdev, bar, io_size);
1134 if (!ioaddr) {
1135 printk(KERN_ERR DRV_NAME ": ioremap failed for device %s\n",
1136 pci_name(pdev));
1137 err = -EIO;
1138 goto err_out_free_res;
1139 }
1140 /* If PHY status change register is still set to zero it means the
1141 * bootloader didn't initialize it */
1142 if (ioread16(ioaddr + PHY_CC) == 0)
1143 iowrite16(0x9f07, ioaddr + PHY_CC);
1144
1145 /* Init system & device */
1146 lp->base = ioaddr;
1147 dev->irq = pdev->irq;
1148
1149 spin_lock_init(&lp->lock);
1150 pci_set_drvdata(pdev, dev);
1151
1152 /* Set MAC address */
1153 card_idx++;
1154
1155 adrp = (u16 *)dev->dev_addr;
1156 adrp[0] = ioread16(ioaddr + MID_0L);
1157 adrp[1] = ioread16(ioaddr + MID_0M);
1158 adrp[2] = ioread16(ioaddr + MID_0H);
1159
1160 /* Some bootloader/BIOSes do not initialize
1161 * MAC address, warn about that */
1162 if (!(adrp[0] || adrp[1] || adrp[2])) {
1163 printk(KERN_WARNING DRV_NAME ": MAC address not initialized, generating random\n");
1164 random_ether_addr(dev->dev_addr);
1165 }
1166
1167 /* Link new device into r6040_root_dev */
1168 lp->pdev = pdev;
1169 lp->dev = dev;
1170
1171 /* Init RDC private data */
1172 lp->mcr0 = 0x1002;
1173 lp->phy_addr = phy_table[card_idx];
1174 lp->switch_sig = 0;
1175
1176 /* The RDC-specific entries in the device structure. */
1177 dev->netdev_ops = &r6040_netdev_ops;
1178 dev->ethtool_ops = &netdev_ethtool_ops;
1179 dev->watchdog_timeo = TX_TIMEOUT;
1180
1181 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1182 lp->mii_if.dev = dev;
1183 lp->mii_if.mdio_read = r6040_mdio_read;
1184 lp->mii_if.mdio_write = r6040_mdio_write;
1185 lp->mii_if.phy_id = lp->phy_addr;
1186 lp->mii_if.phy_id_mask = 0x1f;
1187 lp->mii_if.reg_num_mask = 0x1f;
1188
1189 /* Check the vendor ID on the PHY, if 0xffff assume none attached */
1190 if (r6040_phy_read(ioaddr, lp->phy_addr, 2) == 0xffff) {
1191 printk(KERN_ERR DRV_NAME ": Failed to detect an attached PHY\n");
1192 err = -ENODEV;
1193 goto err_out_unmap;
1194 }
1195
1196 /* Register net device. After this dev->name assign */
1197 err = register_netdev(dev);
1198 if (err) {
1199 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1200 goto err_out_unmap;
1201 }
1202 return 0;
1203
1204 err_out_unmap:
1205 pci_iounmap(pdev, ioaddr);
1206 err_out_free_res:
1207 pci_release_regions(pdev);
1208 err_out_free_dev:
1209 free_netdev(dev);
1210 err_out:
1211 return err;
1212 }
1213
1214 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1215 {
1216 struct net_device *dev = pci_get_drvdata(pdev);
1217
1218 unregister_netdev(dev);
1219 pci_release_regions(pdev);
1220 free_netdev(dev);
1221 pci_disable_device(pdev);
1222 pci_set_drvdata(pdev, NULL);
1223 }
1224
1225
1226 static struct pci_device_id r6040_pci_tbl[] = {
1227 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1228 { 0 }
1229 };
1230 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1231
1232 static struct pci_driver r6040_driver = {
1233 .name = DRV_NAME,
1234 .id_table = r6040_pci_tbl,
1235 .probe = r6040_init_one,
1236 .remove = __devexit_p(r6040_remove_one),
1237 };
1238
1239
1240 static int __init r6040_init(void)
1241 {
1242 return pci_register_driver(&r6040_driver);
1243 }
1244
1245
1246 static void __exit r6040_cleanup(void)
1247 {
1248 pci_unregister_driver(&r6040_driver);
1249 }
1250
1251 module_init(r6040_init);
1252 module_exit(r6040_cleanup);
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