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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / r8169.c
blob83c47d95c3aaf4288360088e891a903924ecf3f1
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
34
35 #ifdef RTL8169_DEBUG
36 #define assert(expr) \
37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
40 }
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43 #else
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
47
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
50
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit = 32;
57
58 /* MAC address length */
59 #define MAC_ADDR_LEN 6
60
61 #define MAX_READ_REQUEST_SHIFT 12
62 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_NAPI_WEIGHT 64
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77 #define RTL8169_TX_TIMEOUT (6*HZ)
78 #define RTL8169_PHY_TIMEOUT (10*HZ)
79
80 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR 0x0000
83
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92 enum mac_version {
93 RTL_GIGA_MAC_NONE = 0x00,
94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
121 };
122
123 #define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
125
126 static const struct {
127 const char *name;
128 u8 mac_version;
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130 } rtl_chip_info[] = {
131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
158 };
159 #undef _R
160
161 enum cfg_version {
162 RTL_CFG_0 = 0x00,
163 RTL_CFG_1,
164 RTL_CFG_2
165 };
166
167 static void rtl_hw_start_8169(struct net_device *);
168 static void rtl_hw_start_8168(struct net_device *);
169 static void rtl_hw_start_8101(struct net_device *);
170
171 static struct pci_device_id rtl8169_pci_tbl[] = {
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
180 { PCI_VENDOR_ID_LINKSYS, 0x1032,
181 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
182 { 0x0001, 0x8168,
183 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
184 {0,},
185 };
186
187 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
188
189 static int rx_copybreak = 200;
190 static int use_dac;
191 static struct {
192 u32 msg_enable;
193 } debug = { -1 };
194
195 enum rtl_registers {
196 MAC0 = 0, /* Ethernet hardware address. */
197 MAC4 = 4,
198 MAR0 = 8, /* Multicast filter. */
199 CounterAddrLow = 0x10,
200 CounterAddrHigh = 0x14,
201 TxDescStartAddrLow = 0x20,
202 TxDescStartAddrHigh = 0x24,
203 TxHDescStartAddrLow = 0x28,
204 TxHDescStartAddrHigh = 0x2c,
205 FLASH = 0x30,
206 ERSR = 0x36,
207 ChipCmd = 0x37,
208 TxPoll = 0x38,
209 IntrMask = 0x3c,
210 IntrStatus = 0x3e,
211 TxConfig = 0x40,
212 RxConfig = 0x44,
213 RxMissed = 0x4c,
214 Cfg9346 = 0x50,
215 Config0 = 0x51,
216 Config1 = 0x52,
217 Config2 = 0x53,
218 Config3 = 0x54,
219 Config4 = 0x55,
220 Config5 = 0x56,
221 MultiIntr = 0x5c,
222 PHYAR = 0x60,
223 PHYstatus = 0x6c,
224 RxMaxSize = 0xda,
225 CPlusCmd = 0xe0,
226 IntrMitigate = 0xe2,
227 RxDescAddrLow = 0xe4,
228 RxDescAddrHigh = 0xe8,
229 EarlyTxThres = 0xec,
230 FuncEvent = 0xf0,
231 FuncEventMask = 0xf4,
232 FuncPresetState = 0xf8,
233 FuncForceEvent = 0xfc,
234 };
235
236 enum rtl8110_registers {
237 TBICSR = 0x64,
238 TBI_ANAR = 0x68,
239 TBI_LPAR = 0x6a,
240 };
241
242 enum rtl8168_8101_registers {
243 CSIDR = 0x64,
244 CSIAR = 0x68,
245 #define CSIAR_FLAG 0x80000000
246 #define CSIAR_WRITE_CMD 0x80000000
247 #define CSIAR_BYTE_ENABLE 0x0f
248 #define CSIAR_BYTE_ENABLE_SHIFT 12
249 #define CSIAR_ADDR_MASK 0x0fff
250
251 EPHYAR = 0x80,
252 #define EPHYAR_FLAG 0x80000000
253 #define EPHYAR_WRITE_CMD 0x80000000
254 #define EPHYAR_REG_MASK 0x1f
255 #define EPHYAR_REG_SHIFT 16
256 #define EPHYAR_DATA_MASK 0xffff
257 DBG_REG = 0xd1,
258 #define FIX_NAK_1 (1 << 4)
259 #define FIX_NAK_2 (1 << 3)
260 EFUSEAR = 0xdc,
261 #define EFUSEAR_FLAG 0x80000000
262 #define EFUSEAR_WRITE_CMD 0x80000000
263 #define EFUSEAR_READ_CMD 0x00000000
264 #define EFUSEAR_REG_MASK 0x03ff
265 #define EFUSEAR_REG_SHIFT 8
266 #define EFUSEAR_DATA_MASK 0xff
267 };
268
269 enum rtl_register_content {
270 /* InterruptStatusBits */
271 SYSErr = 0x8000,
272 PCSTimeout = 0x4000,
273 SWInt = 0x0100,
274 TxDescUnavail = 0x0080,
275 RxFIFOOver = 0x0040,
276 LinkChg = 0x0020,
277 RxOverflow = 0x0010,
278 TxErr = 0x0008,
279 TxOK = 0x0004,
280 RxErr = 0x0002,
281 RxOK = 0x0001,
282
283 /* RxStatusDesc */
284 RxFOVF = (1 << 23),
285 RxRWT = (1 << 22),
286 RxRES = (1 << 21),
287 RxRUNT = (1 << 20),
288 RxCRC = (1 << 19),
289
290 /* ChipCmdBits */
291 CmdReset = 0x10,
292 CmdRxEnb = 0x08,
293 CmdTxEnb = 0x04,
294 RxBufEmpty = 0x01,
295
296 /* TXPoll register p.5 */
297 HPQ = 0x80, /* Poll cmd on the high prio queue */
298 NPQ = 0x40, /* Poll cmd on the low prio queue */
299 FSWInt = 0x01, /* Forced software interrupt */
300
301 /* Cfg9346Bits */
302 Cfg9346_Lock = 0x00,
303 Cfg9346_Unlock = 0xc0,
304
305 /* rx_mode_bits */
306 AcceptErr = 0x20,
307 AcceptRunt = 0x10,
308 AcceptBroadcast = 0x08,
309 AcceptMulticast = 0x04,
310 AcceptMyPhys = 0x02,
311 AcceptAllPhys = 0x01,
312
313 /* RxConfigBits */
314 RxCfgFIFOShift = 13,
315 RxCfgDMAShift = 8,
316
317 /* TxConfigBits */
318 TxInterFrameGapShift = 24,
319 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
320
321 /* Config1 register p.24 */
322 LEDS1 = (1 << 7),
323 LEDS0 = (1 << 6),
324 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
325 Speed_down = (1 << 4),
326 MEMMAP = (1 << 3),
327 IOMAP = (1 << 2),
328 VPD = (1 << 1),
329 PMEnable = (1 << 0), /* Power Management Enable */
330
331 /* Config2 register p. 25 */
332 PCI_Clock_66MHz = 0x01,
333 PCI_Clock_33MHz = 0x00,
334
335 /* Config3 register p.25 */
336 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
337 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
338 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
339
340 /* Config5 register p.27 */
341 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
342 MWF = (1 << 5), /* Accept Multicast wakeup frame */
343 UWF = (1 << 4), /* Accept Unicast wakeup frame */
344 LanWake = (1 << 1), /* LanWake enable/disable */
345 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
346
347 /* TBICSR p.28 */
348 TBIReset = 0x80000000,
349 TBILoopback = 0x40000000,
350 TBINwEnable = 0x20000000,
351 TBINwRestart = 0x10000000,
352 TBILinkOk = 0x02000000,
353 TBINwComplete = 0x01000000,
354
355 /* CPlusCmd p.31 */
356 EnableBist = (1 << 15), // 8168 8101
357 Mac_dbgo_oe = (1 << 14), // 8168 8101
358 Normal_mode = (1 << 13), // unused
359 Force_half_dup = (1 << 12), // 8168 8101
360 Force_rxflow_en = (1 << 11), // 8168 8101
361 Force_txflow_en = (1 << 10), // 8168 8101
362 Cxpl_dbg_sel = (1 << 9), // 8168 8101
363 ASF = (1 << 8), // 8168 8101
364 PktCntrDisable = (1 << 7), // 8168 8101
365 Mac_dbgo_sel = 0x001c, // 8168
366 RxVlan = (1 << 6),
367 RxChkSum = (1 << 5),
368 PCIDAC = (1 << 4),
369 PCIMulRW = (1 << 3),
370 INTT_0 = 0x0000, // 8168
371 INTT_1 = 0x0001, // 8168
372 INTT_2 = 0x0002, // 8168
373 INTT_3 = 0x0003, // 8168
374
375 /* rtl8169_PHYstatus */
376 TBI_Enable = 0x80,
377 TxFlowCtrl = 0x40,
378 RxFlowCtrl = 0x20,
379 _1000bpsF = 0x10,
380 _100bps = 0x08,
381 _10bps = 0x04,
382 LinkStatus = 0x02,
383 FullDup = 0x01,
384
385 /* _TBICSRBit */
386 TBILinkOK = 0x02000000,
387
388 /* DumpCounterCommand */
389 CounterDump = 0x8,
390 };
391
392 enum desc_status_bit {
393 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
394 RingEnd = (1 << 30), /* End of descriptor ring */
395 FirstFrag = (1 << 29), /* First segment of a packet */
396 LastFrag = (1 << 28), /* Final segment of a packet */
397
398 /* Tx private */
399 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
400 MSSShift = 16, /* MSS value position */
401 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
402 IPCS = (1 << 18), /* Calculate IP checksum */
403 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
404 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
405 TxVlanTag = (1 << 17), /* Add VLAN tag */
406
407 /* Rx private */
408 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
409 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
410
411 #define RxProtoUDP (PID1)
412 #define RxProtoTCP (PID0)
413 #define RxProtoIP (PID1 | PID0)
414 #define RxProtoMask RxProtoIP
415
416 IPFail = (1 << 16), /* IP checksum failed */
417 UDPFail = (1 << 15), /* UDP/IP checksum failed */
418 TCPFail = (1 << 14), /* TCP/IP checksum failed */
419 RxVlanTag = (1 << 16), /* VLAN tag available */
420 };
421
422 #define RsvdMask 0x3fffc000
423
424 struct TxDesc {
425 __le32 opts1;
426 __le32 opts2;
427 __le64 addr;
428 };
429
430 struct RxDesc {
431 __le32 opts1;
432 __le32 opts2;
433 __le64 addr;
434 };
435
436 struct ring_info {
437 struct sk_buff *skb;
438 u32 len;
439 u8 __pad[sizeof(void *) - sizeof(u32)];
440 };
441
442 enum features {
443 RTL_FEATURE_WOL = (1 << 0),
444 RTL_FEATURE_MSI = (1 << 1),
445 RTL_FEATURE_GMII = (1 << 2),
446 };
447
448 struct rtl8169_counters {
449 __le64 tx_packets;
450 __le64 rx_packets;
451 __le64 tx_errors;
452 __le32 rx_errors;
453 __le16 rx_missed;
454 __le16 align_errors;
455 __le32 tx_one_collision;
456 __le32 tx_multi_collision;
457 __le64 rx_unicast;
458 __le64 rx_broadcast;
459 __le32 rx_multicast;
460 __le16 tx_aborted;
461 __le16 tx_underun;
462 };
463
464 struct rtl8169_private {
465 void __iomem *mmio_addr; /* memory map physical address */
466 struct pci_dev *pci_dev; /* Index of PCI device */
467 struct net_device *dev;
468 struct napi_struct napi;
469 spinlock_t lock; /* spin lock flag */
470 u32 msg_enable;
471 int chipset;
472 int mac_version;
473 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
474 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
475 u32 dirty_rx;
476 u32 dirty_tx;
477 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
478 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
479 dma_addr_t TxPhyAddr;
480 dma_addr_t RxPhyAddr;
481 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
482 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
483 unsigned align;
484 unsigned rx_buf_sz;
485 struct timer_list timer;
486 u16 cp_cmd;
487 u16 intr_event;
488 u16 napi_event;
489 u16 intr_mask;
490 int phy_1000_ctrl_reg;
491 #ifdef CONFIG_R8169_VLAN
492 struct vlan_group *vlgrp;
493 #endif
494 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
495 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
496 void (*phy_reset_enable)(void __iomem *);
497 void (*hw_start)(struct net_device *);
498 unsigned int (*phy_reset_pending)(void __iomem *);
499 unsigned int (*link_ok)(void __iomem *);
500 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
501 int pcie_cap;
502 struct delayed_work task;
503 unsigned features;
504
505 struct mii_if_info mii;
506 struct rtl8169_counters counters;
507 };
508
509 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
510 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
511 module_param(rx_copybreak, int, 0);
512 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
513 module_param(use_dac, int, 0);
514 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
515 module_param_named(debug, debug.msg_enable, int, 0);
516 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
517 MODULE_LICENSE("GPL");
518 MODULE_VERSION(RTL8169_VERSION);
519
520 static int rtl8169_open(struct net_device *dev);
521 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
522 struct net_device *dev);
523 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
524 static int rtl8169_init_ring(struct net_device *dev);
525 static void rtl_hw_start(struct net_device *dev);
526 static int rtl8169_close(struct net_device *dev);
527 static void rtl_set_rx_mode(struct net_device *dev);
528 static void rtl8169_tx_timeout(struct net_device *dev);
529 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
530 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
531 void __iomem *, u32 budget);
532 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
533 static void rtl8169_down(struct net_device *dev);
534 static void rtl8169_rx_clear(struct rtl8169_private *tp);
535 static int rtl8169_poll(struct napi_struct *napi, int budget);
536
537 static const unsigned int rtl8169_rx_config =
538 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
539
540 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
541 {
542 int i;
543
544 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
545
546 for (i = 20; i > 0; i--) {
547 /*
548 * Check if the RTL8169 has completed writing to the specified
549 * MII register.
550 */
551 if (!(RTL_R32(PHYAR) & 0x80000000))
552 break;
553 udelay(25);
554 }
555 }
556
557 static int mdio_read(void __iomem *ioaddr, int reg_addr)
558 {
559 int i, value = -1;
560
561 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
562
563 for (i = 20; i > 0; i--) {
564 /*
565 * Check if the RTL8169 has completed retrieving data from
566 * the specified MII register.
567 */
568 if (RTL_R32(PHYAR) & 0x80000000) {
569 value = RTL_R32(PHYAR) & 0xffff;
570 break;
571 }
572 udelay(25);
573 }
574 return value;
575 }
576
577 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
578 {
579 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
580 }
581
582 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
583 {
584 int val;
585
586 val = mdio_read(ioaddr, reg_addr);
587 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
588 }
589
590 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
591 int val)
592 {
593 struct rtl8169_private *tp = netdev_priv(dev);
594 void __iomem *ioaddr = tp->mmio_addr;
595
596 mdio_write(ioaddr, location, val);
597 }
598
599 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
600 {
601 struct rtl8169_private *tp = netdev_priv(dev);
602 void __iomem *ioaddr = tp->mmio_addr;
603
604 return mdio_read(ioaddr, location);
605 }
606
607 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
608 {
609 unsigned int i;
610
611 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
612 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
613
614 for (i = 0; i < 100; i++) {
615 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
616 break;
617 udelay(10);
618 }
619 }
620
621 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
622 {
623 u16 value = 0xffff;
624 unsigned int i;
625
626 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
627
628 for (i = 0; i < 100; i++) {
629 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
630 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
631 break;
632 }
633 udelay(10);
634 }
635
636 return value;
637 }
638
639 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
640 {
641 unsigned int i;
642
643 RTL_W32(CSIDR, value);
644 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
645 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
646
647 for (i = 0; i < 100; i++) {
648 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
649 break;
650 udelay(10);
651 }
652 }
653
654 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
655 {
656 u32 value = ~0x00;
657 unsigned int i;
658
659 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
660 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
661
662 for (i = 0; i < 100; i++) {
663 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
664 value = RTL_R32(CSIDR);
665 break;
666 }
667 udelay(10);
668 }
669
670 return value;
671 }
672
673 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
674 {
675 u8 value = 0xff;
676 unsigned int i;
677
678 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
679
680 for (i = 0; i < 300; i++) {
681 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
682 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
683 break;
684 }
685 udelay(100);
686 }
687
688 return value;
689 }
690
691 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
692 {
693 RTL_W16(IntrMask, 0x0000);
694
695 RTL_W16(IntrStatus, 0xffff);
696 }
697
698 static void rtl8169_asic_down(void __iomem *ioaddr)
699 {
700 RTL_W8(ChipCmd, 0x00);
701 rtl8169_irq_mask_and_ack(ioaddr);
702 RTL_R16(CPlusCmd);
703 }
704
705 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
706 {
707 return RTL_R32(TBICSR) & TBIReset;
708 }
709
710 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
711 {
712 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
713 }
714
715 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
716 {
717 return RTL_R32(TBICSR) & TBILinkOk;
718 }
719
720 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
721 {
722 return RTL_R8(PHYstatus) & LinkStatus;
723 }
724
725 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
726 {
727 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
728 }
729
730 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
731 {
732 unsigned int val;
733
734 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
735 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
736 }
737
738 static void rtl8169_check_link_status(struct net_device *dev,
739 struct rtl8169_private *tp,
740 void __iomem *ioaddr)
741 {
742 unsigned long flags;
743
744 spin_lock_irqsave(&tp->lock, flags);
745 if (tp->link_ok(ioaddr)) {
746 netif_carrier_on(dev);
747 if (netif_msg_ifup(tp))
748 printk(KERN_INFO PFX "%s: link up\n", dev->name);
749 } else {
750 if (netif_msg_ifdown(tp))
751 printk(KERN_INFO PFX "%s: link down\n", dev->name);
752 netif_carrier_off(dev);
753 }
754 spin_unlock_irqrestore(&tp->lock, flags);
755 }
756
757 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
758 {
759 struct rtl8169_private *tp = netdev_priv(dev);
760 void __iomem *ioaddr = tp->mmio_addr;
761 u8 options;
762
763 wol->wolopts = 0;
764
765 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
766 wol->supported = WAKE_ANY;
767
768 spin_lock_irq(&tp->lock);
769
770 options = RTL_R8(Config1);
771 if (!(options & PMEnable))
772 goto out_unlock;
773
774 options = RTL_R8(Config3);
775 if (options & LinkUp)
776 wol->wolopts |= WAKE_PHY;
777 if (options & MagicPacket)
778 wol->wolopts |= WAKE_MAGIC;
779
780 options = RTL_R8(Config5);
781 if (options & UWF)
782 wol->wolopts |= WAKE_UCAST;
783 if (options & BWF)
784 wol->wolopts |= WAKE_BCAST;
785 if (options & MWF)
786 wol->wolopts |= WAKE_MCAST;
787
788 out_unlock:
789 spin_unlock_irq(&tp->lock);
790 }
791
792 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
793 {
794 struct rtl8169_private *tp = netdev_priv(dev);
795 void __iomem *ioaddr = tp->mmio_addr;
796 unsigned int i;
797 static struct {
798 u32 opt;
799 u16 reg;
800 u8 mask;
801 } cfg[] = {
802 { WAKE_ANY, Config1, PMEnable },
803 { WAKE_PHY, Config3, LinkUp },
804 { WAKE_MAGIC, Config3, MagicPacket },
805 { WAKE_UCAST, Config5, UWF },
806 { WAKE_BCAST, Config5, BWF },
807 { WAKE_MCAST, Config5, MWF },
808 { WAKE_ANY, Config5, LanWake }
809 };
810
811 spin_lock_irq(&tp->lock);
812
813 RTL_W8(Cfg9346, Cfg9346_Unlock);
814
815 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
816 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
817 if (wol->wolopts & cfg[i].opt)
818 options |= cfg[i].mask;
819 RTL_W8(cfg[i].reg, options);
820 }
821
822 RTL_W8(Cfg9346, Cfg9346_Lock);
823
824 if (wol->wolopts)
825 tp->features |= RTL_FEATURE_WOL;
826 else
827 tp->features &= ~RTL_FEATURE_WOL;
828 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
829
830 spin_unlock_irq(&tp->lock);
831
832 return 0;
833 }
834
835 static void rtl8169_get_drvinfo(struct net_device *dev,
836 struct ethtool_drvinfo *info)
837 {
838 struct rtl8169_private *tp = netdev_priv(dev);
839
840 strcpy(info->driver, MODULENAME);
841 strcpy(info->version, RTL8169_VERSION);
842 strcpy(info->bus_info, pci_name(tp->pci_dev));
843 }
844
845 static int rtl8169_get_regs_len(struct net_device *dev)
846 {
847 return R8169_REGS_SIZE;
848 }
849
850 static int rtl8169_set_speed_tbi(struct net_device *dev,
851 u8 autoneg, u16 speed, u8 duplex)
852 {
853 struct rtl8169_private *tp = netdev_priv(dev);
854 void __iomem *ioaddr = tp->mmio_addr;
855 int ret = 0;
856 u32 reg;
857
858 reg = RTL_R32(TBICSR);
859 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
860 (duplex == DUPLEX_FULL)) {
861 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
862 } else if (autoneg == AUTONEG_ENABLE)
863 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
864 else {
865 if (netif_msg_link(tp)) {
866 printk(KERN_WARNING "%s: "
867 "incorrect speed setting refused in TBI mode\n",
868 dev->name);
869 }
870 ret = -EOPNOTSUPP;
871 }
872
873 return ret;
874 }
875
876 static int rtl8169_set_speed_xmii(struct net_device *dev,
877 u8 autoneg, u16 speed, u8 duplex)
878 {
879 struct rtl8169_private *tp = netdev_priv(dev);
880 void __iomem *ioaddr = tp->mmio_addr;
881 int giga_ctrl, bmcr;
882
883 if (autoneg == AUTONEG_ENABLE) {
884 int auto_nego;
885
886 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
887 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
888 ADVERTISE_100HALF | ADVERTISE_100FULL);
889 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
890
891 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
892 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
893
894 /* The 8100e/8101e/8102e do Fast Ethernet only. */
895 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
896 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
897 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
898 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
899 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
900 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
901 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
902 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
903 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
904 } else if (netif_msg_link(tp)) {
905 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
906 dev->name);
907 }
908
909 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
910
911 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
912 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
913 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
914 /*
915 * Wake up the PHY.
916 * Vendor specific (0x1f) and reserved (0x0e) MII
917 * registers.
918 */
919 mdio_write(ioaddr, 0x1f, 0x0000);
920 mdio_write(ioaddr, 0x0e, 0x0000);
921 }
922
923 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
924 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
925 } else {
926 giga_ctrl = 0;
927
928 if (speed == SPEED_10)
929 bmcr = 0;
930 else if (speed == SPEED_100)
931 bmcr = BMCR_SPEED100;
932 else
933 return -EINVAL;
934
935 if (duplex == DUPLEX_FULL)
936 bmcr |= BMCR_FULLDPLX;
937
938 mdio_write(ioaddr, 0x1f, 0x0000);
939 }
940
941 tp->phy_1000_ctrl_reg = giga_ctrl;
942
943 mdio_write(ioaddr, MII_BMCR, bmcr);
944
945 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
946 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
947 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
948 mdio_write(ioaddr, 0x17, 0x2138);
949 mdio_write(ioaddr, 0x0e, 0x0260);
950 } else {
951 mdio_write(ioaddr, 0x17, 0x2108);
952 mdio_write(ioaddr, 0x0e, 0x0000);
953 }
954 }
955
956 return 0;
957 }
958
959 static int rtl8169_set_speed(struct net_device *dev,
960 u8 autoneg, u16 speed, u8 duplex)
961 {
962 struct rtl8169_private *tp = netdev_priv(dev);
963 int ret;
964
965 ret = tp->set_speed(dev, autoneg, speed, duplex);
966
967 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
968 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
969
970 return ret;
971 }
972
973 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
974 {
975 struct rtl8169_private *tp = netdev_priv(dev);
976 unsigned long flags;
977 int ret;
978
979 spin_lock_irqsave(&tp->lock, flags);
980 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
981 spin_unlock_irqrestore(&tp->lock, flags);
982
983 return ret;
984 }
985
986 static u32 rtl8169_get_rx_csum(struct net_device *dev)
987 {
988 struct rtl8169_private *tp = netdev_priv(dev);
989
990 return tp->cp_cmd & RxChkSum;
991 }
992
993 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
994 {
995 struct rtl8169_private *tp = netdev_priv(dev);
996 void __iomem *ioaddr = tp->mmio_addr;
997 unsigned long flags;
998
999 spin_lock_irqsave(&tp->lock, flags);
1000
1001 if (data)
1002 tp->cp_cmd |= RxChkSum;
1003 else
1004 tp->cp_cmd &= ~RxChkSum;
1005
1006 RTL_W16(CPlusCmd, tp->cp_cmd);
1007 RTL_R16(CPlusCmd);
1008
1009 spin_unlock_irqrestore(&tp->lock, flags);
1010
1011 return 0;
1012 }
1013
1014 #ifdef CONFIG_R8169_VLAN
1015
1016 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1017 struct sk_buff *skb)
1018 {
1019 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1020 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1021 }
1022
1023 static void rtl8169_vlan_rx_register(struct net_device *dev,
1024 struct vlan_group *grp)
1025 {
1026 struct rtl8169_private *tp = netdev_priv(dev);
1027 void __iomem *ioaddr = tp->mmio_addr;
1028 unsigned long flags;
1029
1030 spin_lock_irqsave(&tp->lock, flags);
1031 tp->vlgrp = grp;
1032 if (tp->vlgrp)
1033 tp->cp_cmd |= RxVlan;
1034 else
1035 tp->cp_cmd &= ~RxVlan;
1036 RTL_W16(CPlusCmd, tp->cp_cmd);
1037 RTL_R16(CPlusCmd);
1038 spin_unlock_irqrestore(&tp->lock, flags);
1039 }
1040
1041 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1042 struct sk_buff *skb)
1043 {
1044 u32 opts2 = le32_to_cpu(desc->opts2);
1045 struct vlan_group *vlgrp = tp->vlgrp;
1046 int ret;
1047
1048 if (vlgrp && (opts2 & RxVlanTag)) {
1049 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1050 ret = 0;
1051 } else
1052 ret = -1;
1053 desc->opts2 = 0;
1054 return ret;
1055 }
1056
1057 #else /* !CONFIG_R8169_VLAN */
1058
1059 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1060 struct sk_buff *skb)
1061 {
1062 return 0;
1063 }
1064
1065 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1066 struct sk_buff *skb)
1067 {
1068 return -1;
1069 }
1070
1071 #endif
1072
1073 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1074 {
1075 struct rtl8169_private *tp = netdev_priv(dev);
1076 void __iomem *ioaddr = tp->mmio_addr;
1077 u32 status;
1078
1079 cmd->supported =
1080 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1081 cmd->port = PORT_FIBRE;
1082 cmd->transceiver = XCVR_INTERNAL;
1083
1084 status = RTL_R32(TBICSR);
1085 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1086 cmd->autoneg = !!(status & TBINwEnable);
1087
1088 cmd->speed = SPEED_1000;
1089 cmd->duplex = DUPLEX_FULL; /* Always set */
1090
1091 return 0;
1092 }
1093
1094 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1095 {
1096 struct rtl8169_private *tp = netdev_priv(dev);
1097
1098 return mii_ethtool_gset(&tp->mii, cmd);
1099 }
1100
1101 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1102 {
1103 struct rtl8169_private *tp = netdev_priv(dev);
1104 unsigned long flags;
1105 int rc;
1106
1107 spin_lock_irqsave(&tp->lock, flags);
1108
1109 rc = tp->get_settings(dev, cmd);
1110
1111 spin_unlock_irqrestore(&tp->lock, flags);
1112 return rc;
1113 }
1114
1115 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1116 void *p)
1117 {
1118 struct rtl8169_private *tp = netdev_priv(dev);
1119 unsigned long flags;
1120
1121 if (regs->len > R8169_REGS_SIZE)
1122 regs->len = R8169_REGS_SIZE;
1123
1124 spin_lock_irqsave(&tp->lock, flags);
1125 memcpy_fromio(p, tp->mmio_addr, regs->len);
1126 spin_unlock_irqrestore(&tp->lock, flags);
1127 }
1128
1129 static u32 rtl8169_get_msglevel(struct net_device *dev)
1130 {
1131 struct rtl8169_private *tp = netdev_priv(dev);
1132
1133 return tp->msg_enable;
1134 }
1135
1136 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1137 {
1138 struct rtl8169_private *tp = netdev_priv(dev);
1139
1140 tp->msg_enable = value;
1141 }
1142
1143 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1144 "tx_packets",
1145 "rx_packets",
1146 "tx_errors",
1147 "rx_errors",
1148 "rx_missed",
1149 "align_errors",
1150 "tx_single_collisions",
1151 "tx_multi_collisions",
1152 "unicast",
1153 "broadcast",
1154 "multicast",
1155 "tx_aborted",
1156 "tx_underrun",
1157 };
1158
1159 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1160 {
1161 switch (sset) {
1162 case ETH_SS_STATS:
1163 return ARRAY_SIZE(rtl8169_gstrings);
1164 default:
1165 return -EOPNOTSUPP;
1166 }
1167 }
1168
1169 static void rtl8169_update_counters(struct net_device *dev)
1170 {
1171 struct rtl8169_private *tp = netdev_priv(dev);
1172 void __iomem *ioaddr = tp->mmio_addr;
1173 struct rtl8169_counters *counters;
1174 dma_addr_t paddr;
1175 u32 cmd;
1176 int wait = 1000;
1177
1178 /*
1179 * Some chips are unable to dump tally counters when the receiver
1180 * is disabled.
1181 */
1182 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1183 return;
1184
1185 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1186 if (!counters)
1187 return;
1188
1189 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1190 cmd = (u64)paddr & DMA_BIT_MASK(32);
1191 RTL_W32(CounterAddrLow, cmd);
1192 RTL_W32(CounterAddrLow, cmd | CounterDump);
1193
1194 while (wait--) {
1195 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1196 /* copy updated counters */
1197 memcpy(&tp->counters, counters, sizeof(*counters));
1198 break;
1199 }
1200 udelay(10);
1201 }
1202
1203 RTL_W32(CounterAddrLow, 0);
1204 RTL_W32(CounterAddrHigh, 0);
1205
1206 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1207 }
1208
1209 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1210 struct ethtool_stats *stats, u64 *data)
1211 {
1212 struct rtl8169_private *tp = netdev_priv(dev);
1213
1214 ASSERT_RTNL();
1215
1216 rtl8169_update_counters(dev);
1217
1218 data[0] = le64_to_cpu(tp->counters.tx_packets);
1219 data[1] = le64_to_cpu(tp->counters.rx_packets);
1220 data[2] = le64_to_cpu(tp->counters.tx_errors);
1221 data[3] = le32_to_cpu(tp->counters.rx_errors);
1222 data[4] = le16_to_cpu(tp->counters.rx_missed);
1223 data[5] = le16_to_cpu(tp->counters.align_errors);
1224 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1225 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1226 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1227 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1228 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1229 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1230 data[12] = le16_to_cpu(tp->counters.tx_underun);
1231 }
1232
1233 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1234 {
1235 switch(stringset) {
1236 case ETH_SS_STATS:
1237 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1238 break;
1239 }
1240 }
1241
1242 static const struct ethtool_ops rtl8169_ethtool_ops = {
1243 .get_drvinfo = rtl8169_get_drvinfo,
1244 .get_regs_len = rtl8169_get_regs_len,
1245 .get_link = ethtool_op_get_link,
1246 .get_settings = rtl8169_get_settings,
1247 .set_settings = rtl8169_set_settings,
1248 .get_msglevel = rtl8169_get_msglevel,
1249 .set_msglevel = rtl8169_set_msglevel,
1250 .get_rx_csum = rtl8169_get_rx_csum,
1251 .set_rx_csum = rtl8169_set_rx_csum,
1252 .set_tx_csum = ethtool_op_set_tx_csum,
1253 .set_sg = ethtool_op_set_sg,
1254 .set_tso = ethtool_op_set_tso,
1255 .get_regs = rtl8169_get_regs,
1256 .get_wol = rtl8169_get_wol,
1257 .set_wol = rtl8169_set_wol,
1258 .get_strings = rtl8169_get_strings,
1259 .get_sset_count = rtl8169_get_sset_count,
1260 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1261 };
1262
1263 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1264 void __iomem *ioaddr)
1265 {
1266 /*
1267 * The driver currently handles the 8168Bf and the 8168Be identically
1268 * but they can be identified more specifically through the test below
1269 * if needed:
1270 *
1271 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1272 *
1273 * Same thing for the 8101Eb and the 8101Ec:
1274 *
1275 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1276 */
1277 const struct {
1278 u32 mask;
1279 u32 val;
1280 int mac_version;
1281 } mac_info[] = {
1282 /* 8168D family. */
1283 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1284 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1285 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1286 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1287
1288 /* 8168C family. */
1289 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1290 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1291 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1292 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1293 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1294 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1295 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1296 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1297 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1298
1299 /* 8168B family. */
1300 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1301 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1302 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1303 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1304
1305 /* 8101 family. */
1306 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1307 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1308 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1309 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1310 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1311 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1312 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1313 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1314 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1315 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1316 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1317 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1318 /* FIXME: where did these entries come from ? -- FR */
1319 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1320 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1321
1322 /* 8110 family. */
1323 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1324 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1325 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1326 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1327 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1328 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1329
1330 /* Catch-all */
1331 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1332 }, *p = mac_info;
1333 u32 reg;
1334
1335 reg = RTL_R32(TxConfig);
1336 while ((reg & p->mask) != p->val)
1337 p++;
1338 tp->mac_version = p->mac_version;
1339 }
1340
1341 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1342 {
1343 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1344 }
1345
1346 struct phy_reg {
1347 u16 reg;
1348 u16 val;
1349 };
1350
1351 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1352 {
1353 while (len-- > 0) {
1354 mdio_write(ioaddr, regs->reg, regs->val);
1355 regs++;
1356 }
1357 }
1358
1359 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1360 {
1361 struct phy_reg phy_reg_init[] = {
1362 { 0x1f, 0x0001 },
1363 { 0x06, 0x006e },
1364 { 0x08, 0x0708 },
1365 { 0x15, 0x4000 },
1366 { 0x18, 0x65c7 },
1367
1368 { 0x1f, 0x0001 },
1369 { 0x03, 0x00a1 },
1370 { 0x02, 0x0008 },
1371 { 0x01, 0x0120 },
1372 { 0x00, 0x1000 },
1373 { 0x04, 0x0800 },
1374 { 0x04, 0x0000 },
1375
1376 { 0x03, 0xff41 },
1377 { 0x02, 0xdf60 },
1378 { 0x01, 0x0140 },
1379 { 0x00, 0x0077 },
1380 { 0x04, 0x7800 },
1381 { 0x04, 0x7000 },
1382
1383 { 0x03, 0x802f },
1384 { 0x02, 0x4f02 },
1385 { 0x01, 0x0409 },
1386 { 0x00, 0xf0f9 },
1387 { 0x04, 0x9800 },
1388 { 0x04, 0x9000 },
1389
1390 { 0x03, 0xdf01 },
1391 { 0x02, 0xdf20 },
1392 { 0x01, 0xff95 },
1393 { 0x00, 0xba00 },
1394 { 0x04, 0xa800 },
1395 { 0x04, 0xa000 },
1396
1397 { 0x03, 0xff41 },
1398 { 0x02, 0xdf20 },
1399 { 0x01, 0x0140 },
1400 { 0x00, 0x00bb },
1401 { 0x04, 0xb800 },
1402 { 0x04, 0xb000 },
1403
1404 { 0x03, 0xdf41 },
1405 { 0x02, 0xdc60 },
1406 { 0x01, 0x6340 },
1407 { 0x00, 0x007d },
1408 { 0x04, 0xd800 },
1409 { 0x04, 0xd000 },
1410
1411 { 0x03, 0xdf01 },
1412 { 0x02, 0xdf20 },
1413 { 0x01, 0x100a },
1414 { 0x00, 0xa0ff },
1415 { 0x04, 0xf800 },
1416 { 0x04, 0xf000 },
1417
1418 { 0x1f, 0x0000 },
1419 { 0x0b, 0x0000 },
1420 { 0x00, 0x9200 }
1421 };
1422
1423 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1424 }
1425
1426 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1427 {
1428 struct phy_reg phy_reg_init[] = {
1429 { 0x1f, 0x0002 },
1430 { 0x01, 0x90d0 },
1431 { 0x1f, 0x0000 }
1432 };
1433
1434 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1435 }
1436
1437 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1438 void __iomem *ioaddr)
1439 {
1440 struct pci_dev *pdev = tp->pci_dev;
1441 u16 vendor_id, device_id;
1442
1443 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1444 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1445
1446 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1447 return;
1448
1449 mdio_write(ioaddr, 0x1f, 0x0001);
1450 mdio_write(ioaddr, 0x10, 0xf01b);
1451 mdio_write(ioaddr, 0x1f, 0x0000);
1452 }
1453
1454 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1455 void __iomem *ioaddr)
1456 {
1457 struct phy_reg phy_reg_init[] = {
1458 { 0x1f, 0x0001 },
1459 { 0x04, 0x0000 },
1460 { 0x03, 0x00a1 },
1461 { 0x02, 0x0008 },
1462 { 0x01, 0x0120 },
1463 { 0x00, 0x1000 },
1464 { 0x04, 0x0800 },
1465 { 0x04, 0x9000 },
1466 { 0x03, 0x802f },
1467 { 0x02, 0x4f02 },
1468 { 0x01, 0x0409 },
1469 { 0x00, 0xf099 },
1470 { 0x04, 0x9800 },
1471 { 0x04, 0xa000 },
1472 { 0x03, 0xdf01 },
1473 { 0x02, 0xdf20 },
1474 { 0x01, 0xff95 },
1475 { 0x00, 0xba00 },
1476 { 0x04, 0xa800 },
1477 { 0x04, 0xf000 },
1478 { 0x03, 0xdf01 },
1479 { 0x02, 0xdf20 },
1480 { 0x01, 0x101a },
1481 { 0x00, 0xa0ff },
1482 { 0x04, 0xf800 },
1483 { 0x04, 0x0000 },
1484 { 0x1f, 0x0000 },
1485
1486 { 0x1f, 0x0001 },
1487 { 0x10, 0xf41b },
1488 { 0x14, 0xfb54 },
1489 { 0x18, 0xf5c7 },
1490 { 0x1f, 0x0000 },
1491
1492 { 0x1f, 0x0001 },
1493 { 0x17, 0x0cc0 },
1494 { 0x1f, 0x0000 }
1495 };
1496
1497 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1498
1499 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1500 }
1501
1502 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1503 {
1504 struct phy_reg phy_reg_init[] = {
1505 { 0x1f, 0x0001 },
1506 { 0x04, 0x0000 },
1507 { 0x03, 0x00a1 },
1508 { 0x02, 0x0008 },
1509 { 0x01, 0x0120 },
1510 { 0x00, 0x1000 },
1511 { 0x04, 0x0800 },
1512 { 0x04, 0x9000 },
1513 { 0x03, 0x802f },
1514 { 0x02, 0x4f02 },
1515 { 0x01, 0x0409 },
1516 { 0x00, 0xf099 },
1517 { 0x04, 0x9800 },
1518 { 0x04, 0xa000 },
1519 { 0x03, 0xdf01 },
1520 { 0x02, 0xdf20 },
1521 { 0x01, 0xff95 },
1522 { 0x00, 0xba00 },
1523 { 0x04, 0xa800 },
1524 { 0x04, 0xf000 },
1525 { 0x03, 0xdf01 },
1526 { 0x02, 0xdf20 },
1527 { 0x01, 0x101a },
1528 { 0x00, 0xa0ff },
1529 { 0x04, 0xf800 },
1530 { 0x04, 0x0000 },
1531 { 0x1f, 0x0000 },
1532
1533 { 0x1f, 0x0001 },
1534 { 0x0b, 0x8480 },
1535 { 0x1f, 0x0000 },
1536
1537 { 0x1f, 0x0001 },
1538 { 0x18, 0x67c7 },
1539 { 0x04, 0x2000 },
1540 { 0x03, 0x002f },
1541 { 0x02, 0x4360 },
1542 { 0x01, 0x0109 },
1543 { 0x00, 0x3022 },
1544 { 0x04, 0x2800 },
1545 { 0x1f, 0x0000 },
1546
1547 { 0x1f, 0x0001 },
1548 { 0x17, 0x0cc0 },
1549 { 0x1f, 0x0000 }
1550 };
1551
1552 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1553 }
1554
1555 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1556 {
1557 struct phy_reg phy_reg_init[] = {
1558 { 0x10, 0xf41b },
1559 { 0x1f, 0x0000 }
1560 };
1561
1562 mdio_write(ioaddr, 0x1f, 0x0001);
1563 mdio_patch(ioaddr, 0x16, 1 << 0);
1564
1565 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1566 }
1567
1568 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1569 {
1570 struct phy_reg phy_reg_init[] = {
1571 { 0x1f, 0x0001 },
1572 { 0x10, 0xf41b },
1573 { 0x1f, 0x0000 }
1574 };
1575
1576 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1577 }
1578
1579 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1580 {
1581 struct phy_reg phy_reg_init[] = {
1582 { 0x1f, 0x0000 },
1583 { 0x1d, 0x0f00 },
1584 { 0x1f, 0x0002 },
1585 { 0x0c, 0x1ec8 },
1586 { 0x1f, 0x0000 }
1587 };
1588
1589 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1590 }
1591
1592 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1593 {
1594 struct phy_reg phy_reg_init[] = {
1595 { 0x1f, 0x0001 },
1596 { 0x1d, 0x3d98 },
1597 { 0x1f, 0x0000 }
1598 };
1599
1600 mdio_write(ioaddr, 0x1f, 0x0000);
1601 mdio_patch(ioaddr, 0x14, 1 << 5);
1602 mdio_patch(ioaddr, 0x0d, 1 << 5);
1603
1604 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1605 }
1606
1607 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1608 {
1609 struct phy_reg phy_reg_init[] = {
1610 { 0x1f, 0x0001 },
1611 { 0x12, 0x2300 },
1612 { 0x1f, 0x0002 },
1613 { 0x00, 0x88d4 },
1614 { 0x01, 0x82b1 },
1615 { 0x03, 0x7002 },
1616 { 0x08, 0x9e30 },
1617 { 0x09, 0x01f0 },
1618 { 0x0a, 0x5500 },
1619 { 0x0c, 0x00c8 },
1620 { 0x1f, 0x0003 },
1621 { 0x12, 0xc096 },
1622 { 0x16, 0x000a },
1623 { 0x1f, 0x0000 },
1624 { 0x1f, 0x0000 },
1625 { 0x09, 0x2000 },
1626 { 0x09, 0x0000 }
1627 };
1628
1629 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1630
1631 mdio_patch(ioaddr, 0x14, 1 << 5);
1632 mdio_patch(ioaddr, 0x0d, 1 << 5);
1633 mdio_write(ioaddr, 0x1f, 0x0000);
1634 }
1635
1636 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1637 {
1638 struct phy_reg phy_reg_init[] = {
1639 { 0x1f, 0x0001 },
1640 { 0x12, 0x2300 },
1641 { 0x03, 0x802f },
1642 { 0x02, 0x4f02 },
1643 { 0x01, 0x0409 },
1644 { 0x00, 0xf099 },
1645 { 0x04, 0x9800 },
1646 { 0x04, 0x9000 },
1647 { 0x1d, 0x3d98 },
1648 { 0x1f, 0x0002 },
1649 { 0x0c, 0x7eb8 },
1650 { 0x06, 0x0761 },
1651 { 0x1f, 0x0003 },
1652 { 0x16, 0x0f0a },
1653 { 0x1f, 0x0000 }
1654 };
1655
1656 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1657
1658 mdio_patch(ioaddr, 0x16, 1 << 0);
1659 mdio_patch(ioaddr, 0x14, 1 << 5);
1660 mdio_patch(ioaddr, 0x0d, 1 << 5);
1661 mdio_write(ioaddr, 0x1f, 0x0000);
1662 }
1663
1664 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1665 {
1666 struct phy_reg phy_reg_init[] = {
1667 { 0x1f, 0x0001 },
1668 { 0x12, 0x2300 },
1669 { 0x1d, 0x3d98 },
1670 { 0x1f, 0x0002 },
1671 { 0x0c, 0x7eb8 },
1672 { 0x06, 0x5461 },
1673 { 0x1f, 0x0003 },
1674 { 0x16, 0x0f0a },
1675 { 0x1f, 0x0000 }
1676 };
1677
1678 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1679
1680 mdio_patch(ioaddr, 0x16, 1 << 0);
1681 mdio_patch(ioaddr, 0x14, 1 << 5);
1682 mdio_patch(ioaddr, 0x0d, 1 << 5);
1683 mdio_write(ioaddr, 0x1f, 0x0000);
1684 }
1685
1686 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1687 {
1688 rtl8168c_3_hw_phy_config(ioaddr);
1689 }
1690
1691 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1692 {
1693 static struct phy_reg phy_reg_init_0[] = {
1694 { 0x1f, 0x0001 },
1695 { 0x06, 0x4064 },
1696 { 0x07, 0x2863 },
1697 { 0x08, 0x059c },
1698 { 0x09, 0x26b4 },
1699 { 0x0a, 0x6a19 },
1700 { 0x0b, 0xdcc8 },
1701 { 0x10, 0xf06d },
1702 { 0x14, 0x7f68 },
1703 { 0x18, 0x7fd9 },
1704 { 0x1c, 0xf0ff },
1705 { 0x1d, 0x3d9c },
1706 { 0x1f, 0x0003 },
1707 { 0x12, 0xf49f },
1708 { 0x13, 0x070b },
1709 { 0x1a, 0x05ad },
1710 { 0x14, 0x94c0 }
1711 };
1712 static struct phy_reg phy_reg_init_1[] = {
1713 { 0x1f, 0x0002 },
1714 { 0x06, 0x5561 },
1715 { 0x1f, 0x0005 },
1716 { 0x05, 0x8332 },
1717 { 0x06, 0x5561 }
1718 };
1719 static struct phy_reg phy_reg_init_2[] = {
1720 { 0x1f, 0x0005 },
1721 { 0x05, 0xffc2 },
1722 { 0x1f, 0x0005 },
1723 { 0x05, 0x8000 },
1724 { 0x06, 0xf8f9 },
1725 { 0x06, 0xfaef },
1726 { 0x06, 0x59ee },
1727 { 0x06, 0xf8ea },
1728 { 0x06, 0x00ee },
1729 { 0x06, 0xf8eb },
1730 { 0x06, 0x00e0 },
1731 { 0x06, 0xf87c },
1732 { 0x06, 0xe1f8 },
1733 { 0x06, 0x7d59 },
1734 { 0x06, 0x0fef },
1735 { 0x06, 0x0139 },
1736 { 0x06, 0x029e },
1737 { 0x06, 0x06ef },
1738 { 0x06, 0x1039 },
1739 { 0x06, 0x089f },
1740 { 0x06, 0x2aee },
1741 { 0x06, 0xf8ea },
1742 { 0x06, 0x00ee },
1743 { 0x06, 0xf8eb },
1744 { 0x06, 0x01e0 },
1745 { 0x06, 0xf87c },
1746 { 0x06, 0xe1f8 },
1747 { 0x06, 0x7d58 },
1748 { 0x06, 0x409e },
1749 { 0x06, 0x0f39 },
1750 { 0x06, 0x46aa },
1751 { 0x06, 0x0bbf },
1752 { 0x06, 0x8290 },
1753 { 0x06, 0xd682 },
1754 { 0x06, 0x9802 },
1755 { 0x06, 0x014f },
1756 { 0x06, 0xae09 },
1757 { 0x06, 0xbf82 },
1758 { 0x06, 0x98d6 },
1759 { 0x06, 0x82a0 },
1760 { 0x06, 0x0201 },
1761 { 0x06, 0x4fef },
1762 { 0x06, 0x95fe },
1763 { 0x06, 0xfdfc },
1764 { 0x06, 0x05f8 },
1765 { 0x06, 0xf9fa },
1766 { 0x06, 0xeef8 },
1767 { 0x06, 0xea00 },
1768 { 0x06, 0xeef8 },
1769 { 0x06, 0xeb00 },
1770 { 0x06, 0xe2f8 },
1771 { 0x06, 0x7ce3 },
1772 { 0x06, 0xf87d },
1773 { 0x06, 0xa511 },
1774 { 0x06, 0x1112 },
1775 { 0x06, 0xd240 },
1776 { 0x06, 0xd644 },
1777 { 0x06, 0x4402 },
1778 { 0x06, 0x8217 },
1779 { 0x06, 0xd2a0 },
1780 { 0x06, 0xd6aa },
1781 { 0x06, 0xaa02 },
1782 { 0x06, 0x8217 },
1783 { 0x06, 0xae0f },
1784 { 0x06, 0xa544 },
1785 { 0x06, 0x4402 },
1786 { 0x06, 0xae4d },
1787 { 0x06, 0xa5aa },
1788 { 0x06, 0xaa02 },
1789 { 0x06, 0xae47 },
1790 { 0x06, 0xaf82 },
1791 { 0x06, 0x13ee },
1792 { 0x06, 0x834e },
1793 { 0x06, 0x00ee },
1794 { 0x06, 0x834d },
1795 { 0x06, 0x0fee },
1796 { 0x06, 0x834c },
1797 { 0x06, 0x0fee },
1798 { 0x06, 0x834f },
1799 { 0x06, 0x00ee },
1800 { 0x06, 0x8351 },
1801 { 0x06, 0x00ee },
1802 { 0x06, 0x834a },
1803 { 0x06, 0xffee },
1804 { 0x06, 0x834b },
1805 { 0x06, 0xffe0 },
1806 { 0x06, 0x8330 },
1807 { 0x06, 0xe183 },
1808 { 0x06, 0x3158 },
1809 { 0x06, 0xfee4 },
1810 { 0x06, 0xf88a },
1811 { 0x06, 0xe5f8 },
1812 { 0x06, 0x8be0 },
1813 { 0x06, 0x8332 },
1814 { 0x06, 0xe183 },
1815 { 0x06, 0x3359 },
1816 { 0x06, 0x0fe2 },
1817 { 0x06, 0x834d },
1818 { 0x06, 0x0c24 },
1819 { 0x06, 0x5af0 },
1820 { 0x06, 0x1e12 },
1821 { 0x06, 0xe4f8 },
1822 { 0x06, 0x8ce5 },
1823 { 0x06, 0xf88d },
1824 { 0x06, 0xaf82 },
1825 { 0x06, 0x13e0 },
1826 { 0x06, 0x834f },
1827 { 0x06, 0x10e4 },
1828 { 0x06, 0x834f },
1829 { 0x06, 0xe083 },
1830 { 0x06, 0x4e78 },
1831 { 0x06, 0x009f },
1832 { 0x06, 0x0ae0 },
1833 { 0x06, 0x834f },
1834 { 0x06, 0xa010 },
1835 { 0x06, 0xa5ee },
1836 { 0x06, 0x834e },
1837 { 0x06, 0x01e0 },
1838 { 0x06, 0x834e },
1839 { 0x06, 0x7805 },
1840 { 0x06, 0x9e9a },
1841 { 0x06, 0xe083 },
1842 { 0x06, 0x4e78 },
1843 { 0x06, 0x049e },
1844 { 0x06, 0x10e0 },
1845 { 0x06, 0x834e },
1846 { 0x06, 0x7803 },
1847 { 0x06, 0x9e0f },
1848 { 0x06, 0xe083 },
1849 { 0x06, 0x4e78 },
1850 { 0x06, 0x019e },
1851 { 0x06, 0x05ae },
1852 { 0x06, 0x0caf },
1853 { 0x06, 0x81f8 },
1854 { 0x06, 0xaf81 },
1855 { 0x06, 0xa3af },
1856 { 0x06, 0x81dc },
1857 { 0x06, 0xaf82 },
1858 { 0x06, 0x13ee },
1859 { 0x06, 0x8348 },
1860 { 0x06, 0x00ee },
1861 { 0x06, 0x8349 },
1862 { 0x06, 0x00e0 },
1863 { 0x06, 0x8351 },
1864 { 0x06, 0x10e4 },
1865 { 0x06, 0x8351 },
1866 { 0x06, 0x5801 },
1867 { 0x06, 0x9fea },
1868 { 0x06, 0xd000 },
1869 { 0x06, 0xd180 },
1870 { 0x06, 0x1f66 },
1871 { 0x06, 0xe2f8 },
1872 { 0x06, 0xeae3 },
1873 { 0x06, 0xf8eb },
1874 { 0x06, 0x5af8 },
1875 { 0x06, 0x1e20 },
1876 { 0x06, 0xe6f8 },
1877 { 0x06, 0xeae5 },
1878 { 0x06, 0xf8eb },
1879 { 0x06, 0xd302 },
1880 { 0x06, 0xb3fe },
1881 { 0x06, 0xe2f8 },
1882 { 0x06, 0x7cef },
1883 { 0x06, 0x325b },
1884 { 0x06, 0x80e3 },
1885 { 0x06, 0xf87d },
1886 { 0x06, 0x9e03 },
1887 { 0x06, 0x7dff },
1888 { 0x06, 0xff0d },
1889 { 0x06, 0x581c },
1890 { 0x06, 0x551a },
1891 { 0x06, 0x6511 },
1892 { 0x06, 0xa190 },
1893 { 0x06, 0xd3e2 },
1894 { 0x06, 0x8348 },
1895 { 0x06, 0xe383 },
1896 { 0x06, 0x491b },
1897 { 0x06, 0x56ab },
1898 { 0x06, 0x08ef },
1899 { 0x06, 0x56e6 },
1900 { 0x06, 0x8348 },
1901 { 0x06, 0xe783 },
1902 { 0x06, 0x4910 },
1903 { 0x06, 0xd180 },
1904 { 0x06, 0x1f66 },
1905 { 0x06, 0xa004 },
1906 { 0x06, 0xb9e2 },
1907 { 0x06, 0x8348 },
1908 { 0x06, 0xe383 },
1909 { 0x06, 0x49ef },
1910 { 0x06, 0x65e2 },
1911 { 0x06, 0x834a },
1912 { 0x06, 0xe383 },
1913 { 0x06, 0x4b1b },
1914 { 0x06, 0x56aa },
1915 { 0x06, 0x0eef },
1916 { 0x06, 0x56e6 },
1917 { 0x06, 0x834a },
1918 { 0x06, 0xe783 },
1919 { 0x06, 0x4be2 },
1920 { 0x06, 0x834d },
1921 { 0x06, 0xe683 },
1922 { 0x06, 0x4ce0 },
1923 { 0x06, 0x834d },
1924 { 0x06, 0xa000 },
1925 { 0x06, 0x0caf },
1926 { 0x06, 0x81dc },
1927 { 0x06, 0xe083 },
1928 { 0x06, 0x4d10 },
1929 { 0x06, 0xe483 },
1930 { 0x06, 0x4dae },
1931 { 0x06, 0x0480 },
1932 { 0x06, 0xe483 },
1933 { 0x06, 0x4de0 },
1934 { 0x06, 0x834e },
1935 { 0x06, 0x7803 },
1936 { 0x06, 0x9e0b },
1937 { 0x06, 0xe083 },
1938 { 0x06, 0x4e78 },
1939 { 0x06, 0x049e },
1940 { 0x06, 0x04ee },
1941 { 0x06, 0x834e },
1942 { 0x06, 0x02e0 },
1943 { 0x06, 0x8332 },
1944 { 0x06, 0xe183 },
1945 { 0x06, 0x3359 },
1946 { 0x06, 0x0fe2 },
1947 { 0x06, 0x834d },
1948 { 0x06, 0x0c24 },
1949 { 0x06, 0x5af0 },
1950 { 0x06, 0x1e12 },
1951 { 0x06, 0xe4f8 },
1952 { 0x06, 0x8ce5 },
1953 { 0x06, 0xf88d },
1954 { 0x06, 0xe083 },
1955 { 0x06, 0x30e1 },
1956 { 0x06, 0x8331 },
1957 { 0x06, 0x6801 },
1958 { 0x06, 0xe4f8 },
1959 { 0x06, 0x8ae5 },
1960 { 0x06, 0xf88b },
1961 { 0x06, 0xae37 },
1962 { 0x06, 0xee83 },
1963 { 0x06, 0x4e03 },
1964 { 0x06, 0xe083 },
1965 { 0x06, 0x4ce1 },
1966 { 0x06, 0x834d },
1967 { 0x06, 0x1b01 },
1968 { 0x06, 0x9e04 },
1969 { 0x06, 0xaaa1 },
1970 { 0x06, 0xaea8 },
1971 { 0x06, 0xee83 },
1972 { 0x06, 0x4e04 },
1973 { 0x06, 0xee83 },
1974 { 0x06, 0x4f00 },
1975 { 0x06, 0xaeab },
1976 { 0x06, 0xe083 },
1977 { 0x06, 0x4f78 },
1978 { 0x06, 0x039f },
1979 { 0x06, 0x14ee },
1980 { 0x06, 0x834e },
1981 { 0x06, 0x05d2 },
1982 { 0x06, 0x40d6 },
1983 { 0x06, 0x5554 },
1984 { 0x06, 0x0282 },
1985 { 0x06, 0x17d2 },
1986 { 0x06, 0xa0d6 },
1987 { 0x06, 0xba00 },
1988 { 0x06, 0x0282 },
1989 { 0x06, 0x17fe },
1990 { 0x06, 0xfdfc },
1991 { 0x06, 0x05f8 },
1992 { 0x06, 0xe0f8 },
1993 { 0x06, 0x60e1 },
1994 { 0x06, 0xf861 },
1995 { 0x06, 0x6802 },
1996 { 0x06, 0xe4f8 },
1997 { 0x06, 0x60e5 },
1998 { 0x06, 0xf861 },
1999 { 0x06, 0xe0f8 },
2000 { 0x06, 0x48e1 },
2001 { 0x06, 0xf849 },
2002 { 0x06, 0x580f },
2003 { 0x06, 0x1e02 },
2004 { 0x06, 0xe4f8 },
2005 { 0x06, 0x48e5 },
2006 { 0x06, 0xf849 },
2007 { 0x06, 0xd000 },
2008 { 0x06, 0x0282 },
2009 { 0x06, 0x5bbf },
2010 { 0x06, 0x8350 },
2011 { 0x06, 0xef46 },
2012 { 0x06, 0xdc19 },
2013 { 0x06, 0xddd0 },
2014 { 0x06, 0x0102 },
2015 { 0x06, 0x825b },
2016 { 0x06, 0x0282 },
2017 { 0x06, 0x77e0 },
2018 { 0x06, 0xf860 },
2019 { 0x06, 0xe1f8 },
2020 { 0x06, 0x6158 },
2021 { 0x06, 0xfde4 },
2022 { 0x06, 0xf860 },
2023 { 0x06, 0xe5f8 },
2024 { 0x06, 0x61fc },
2025 { 0x06, 0x04f9 },
2026 { 0x06, 0xfafb },
2027 { 0x06, 0xc6bf },
2028 { 0x06, 0xf840 },
2029 { 0x06, 0xbe83 },
2030 { 0x06, 0x50a0 },
2031 { 0x06, 0x0101 },
2032 { 0x06, 0x071b },
2033 { 0x06, 0x89cf },
2034 { 0x06, 0xd208 },
2035 { 0x06, 0xebdb },
2036 { 0x06, 0x19b2 },
2037 { 0x06, 0xfbff },
2038 { 0x06, 0xfefd },
2039 { 0x06, 0x04f8 },
2040 { 0x06, 0xe0f8 },
2041 { 0x06, 0x48e1 },
2042 { 0x06, 0xf849 },
2043 { 0x06, 0x6808 },
2044 { 0x06, 0xe4f8 },
2045 { 0x06, 0x48e5 },
2046 { 0x06, 0xf849 },
2047 { 0x06, 0x58f7 },
2048 { 0x06, 0xe4f8 },
2049 { 0x06, 0x48e5 },
2050 { 0x06, 0xf849 },
2051 { 0x06, 0xfc04 },
2052 { 0x06, 0x4d20 },
2053 { 0x06, 0x0002 },
2054 { 0x06, 0x4e22 },
2055 { 0x06, 0x0002 },
2056 { 0x06, 0x4ddf },
2057 { 0x06, 0xff01 },
2058 { 0x06, 0x4edd },
2059 { 0x06, 0xff01 },
2060 { 0x05, 0x83d4 },
2061 { 0x06, 0x8000 },
2062 { 0x05, 0x83d8 },
2063 { 0x06, 0x8051 },
2064 { 0x02, 0x6010 },
2065 { 0x03, 0xdc00 },
2066 { 0x05, 0xfff6 },
2067 { 0x06, 0x00fc },
2068 { 0x1f, 0x0000 },
2069
2070 { 0x1f, 0x0000 },
2071 { 0x0d, 0xf880 },
2072 { 0x1f, 0x0000 }
2073 };
2074
2075 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2076
2077 mdio_write(ioaddr, 0x1f, 0x0002);
2078 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2079 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2080
2081 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2082
2083 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2084 struct phy_reg phy_reg_init[] = {
2085 { 0x1f, 0x0002 },
2086 { 0x05, 0x669a },
2087 { 0x1f, 0x0005 },
2088 { 0x05, 0x8330 },
2089 { 0x06, 0x669a },
2090 { 0x1f, 0x0002 }
2091 };
2092 int val;
2093
2094 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2095
2096 val = mdio_read(ioaddr, 0x0d);
2097
2098 if ((val & 0x00ff) != 0x006c) {
2099 u32 set[] = {
2100 0x0065, 0x0066, 0x0067, 0x0068,
2101 0x0069, 0x006a, 0x006b, 0x006c
2102 };
2103 int i;
2104
2105 mdio_write(ioaddr, 0x1f, 0x0002);
2106
2107 val &= 0xff00;
2108 for (i = 0; i < ARRAY_SIZE(set); i++)
2109 mdio_write(ioaddr, 0x0d, val | set[i]);
2110 }
2111 } else {
2112 struct phy_reg phy_reg_init[] = {
2113 { 0x1f, 0x0002 },
2114 { 0x05, 0x6662 },
2115 { 0x1f, 0x0005 },
2116 { 0x05, 0x8330 },
2117 { 0x06, 0x6662 }
2118 };
2119
2120 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2121 }
2122
2123 mdio_write(ioaddr, 0x1f, 0x0002);
2124 mdio_patch(ioaddr, 0x0d, 0x0300);
2125 mdio_patch(ioaddr, 0x0f, 0x0010);
2126
2127 mdio_write(ioaddr, 0x1f, 0x0002);
2128 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2129 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2130
2131 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2132 }
2133
2134 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2135 {
2136 static struct phy_reg phy_reg_init_0[] = {
2137 { 0x1f, 0x0001 },
2138 { 0x06, 0x4064 },
2139 { 0x07, 0x2863 },
2140 { 0x08, 0x059c },
2141 { 0x09, 0x26b4 },
2142 { 0x0a, 0x6a19 },
2143 { 0x0b, 0xdcc8 },
2144 { 0x10, 0xf06d },
2145 { 0x14, 0x7f68 },
2146 { 0x18, 0x7fd9 },
2147 { 0x1c, 0xf0ff },
2148 { 0x1d, 0x3d9c },
2149 { 0x1f, 0x0003 },
2150 { 0x12, 0xf49f },
2151 { 0x13, 0x070b },
2152 { 0x1a, 0x05ad },
2153 { 0x14, 0x94c0 },
2154
2155 { 0x1f, 0x0002 },
2156 { 0x06, 0x5561 },
2157 { 0x1f, 0x0005 },
2158 { 0x05, 0x8332 },
2159 { 0x06, 0x5561 }
2160 };
2161 static struct phy_reg phy_reg_init_1[] = {
2162 { 0x1f, 0x0005 },
2163 { 0x05, 0xffc2 },
2164 { 0x1f, 0x0005 },
2165 { 0x05, 0x8000 },
2166 { 0x06, 0xf8f9 },
2167 { 0x06, 0xfaee },
2168 { 0x06, 0xf8ea },
2169 { 0x06, 0x00ee },
2170 { 0x06, 0xf8eb },
2171 { 0x06, 0x00e2 },
2172 { 0x06, 0xf87c },
2173 { 0x06, 0xe3f8 },
2174 { 0x06, 0x7da5 },
2175 { 0x06, 0x1111 },
2176 { 0x06, 0x12d2 },
2177 { 0x06, 0x40d6 },
2178 { 0x06, 0x4444 },
2179 { 0x06, 0x0281 },
2180 { 0x06, 0xc6d2 },
2181 { 0x06, 0xa0d6 },
2182 { 0x06, 0xaaaa },
2183 { 0x06, 0x0281 },
2184 { 0x06, 0xc6ae },
2185 { 0x06, 0x0fa5 },
2186 { 0x06, 0x4444 },
2187 { 0x06, 0x02ae },
2188 { 0x06, 0x4da5 },
2189 { 0x06, 0xaaaa },
2190 { 0x06, 0x02ae },
2191 { 0x06, 0x47af },
2192 { 0x06, 0x81c2 },
2193 { 0x06, 0xee83 },
2194 { 0x06, 0x4e00 },
2195 { 0x06, 0xee83 },
2196 { 0x06, 0x4d0f },
2197 { 0x06, 0xee83 },
2198 { 0x06, 0x4c0f },
2199 { 0x06, 0xee83 },
2200 { 0x06, 0x4f00 },
2201 { 0x06, 0xee83 },
2202 { 0x06, 0x5100 },
2203 { 0x06, 0xee83 },
2204 { 0x06, 0x4aff },
2205 { 0x06, 0xee83 },
2206 { 0x06, 0x4bff },
2207 { 0x06, 0xe083 },
2208 { 0x06, 0x30e1 },
2209 { 0x06, 0x8331 },
2210 { 0x06, 0x58fe },
2211 { 0x06, 0xe4f8 },
2212 { 0x06, 0x8ae5 },
2213 { 0x06, 0xf88b },
2214 { 0x06, 0xe083 },
2215 { 0x06, 0x32e1 },
2216 { 0x06, 0x8333 },
2217 { 0x06, 0x590f },
2218 { 0x06, 0xe283 },
2219 { 0x06, 0x4d0c },
2220 { 0x06, 0x245a },
2221 { 0x06, 0xf01e },
2222 { 0x06, 0x12e4 },
2223 { 0x06, 0xf88c },
2224 { 0x06, 0xe5f8 },
2225 { 0x06, 0x8daf },
2226 { 0x06, 0x81c2 },
2227 { 0x06, 0xe083 },
2228 { 0x06, 0x4f10 },
2229 { 0x06, 0xe483 },
2230 { 0x06, 0x4fe0 },
2231 { 0x06, 0x834e },
2232 { 0x06, 0x7800 },
2233 { 0x06, 0x9f0a },
2234 { 0x06, 0xe083 },
2235 { 0x06, 0x4fa0 },
2236 { 0x06, 0x10a5 },
2237 { 0x06, 0xee83 },
2238 { 0x06, 0x4e01 },
2239 { 0x06, 0xe083 },
2240 { 0x06, 0x4e78 },
2241 { 0x06, 0x059e },
2242 { 0x06, 0x9ae0 },
2243 { 0x06, 0x834e },
2244 { 0x06, 0x7804 },
2245 { 0x06, 0x9e10 },
2246 { 0x06, 0xe083 },
2247 { 0x06, 0x4e78 },
2248 { 0x06, 0x039e },
2249 { 0x06, 0x0fe0 },
2250 { 0x06, 0x834e },
2251 { 0x06, 0x7801 },
2252 { 0x06, 0x9e05 },
2253 { 0x06, 0xae0c },
2254 { 0x06, 0xaf81 },
2255 { 0x06, 0xa7af },
2256 { 0x06, 0x8152 },
2257 { 0x06, 0xaf81 },
2258 { 0x06, 0x8baf },
2259 { 0x06, 0x81c2 },
2260 { 0x06, 0xee83 },
2261 { 0x06, 0x4800 },
2262 { 0x06, 0xee83 },
2263 { 0x06, 0x4900 },
2264 { 0x06, 0xe083 },
2265 { 0x06, 0x5110 },
2266 { 0x06, 0xe483 },
2267 { 0x06, 0x5158 },
2268 { 0x06, 0x019f },
2269 { 0x06, 0xead0 },
2270 { 0x06, 0x00d1 },
2271 { 0x06, 0x801f },
2272 { 0x06, 0x66e2 },
2273 { 0x06, 0xf8ea },
2274 { 0x06, 0xe3f8 },
2275 { 0x06, 0xeb5a },
2276 { 0x06, 0xf81e },
2277 { 0x06, 0x20e6 },
2278 { 0x06, 0xf8ea },
2279 { 0x06, 0xe5f8 },
2280 { 0x06, 0xebd3 },
2281 { 0x06, 0x02b3 },
2282 { 0x06, 0xfee2 },
2283 { 0x06, 0xf87c },
2284 { 0x06, 0xef32 },
2285 { 0x06, 0x5b80 },
2286 { 0x06, 0xe3f8 },
2287 { 0x06, 0x7d9e },
2288 { 0x06, 0x037d },
2289 { 0x06, 0xffff },
2290 { 0x06, 0x0d58 },
2291 { 0x06, 0x1c55 },
2292 { 0x06, 0x1a65 },
2293 { 0x06, 0x11a1 },
2294 { 0x06, 0x90d3 },
2295 { 0x06, 0xe283 },
2296 { 0x06, 0x48e3 },
2297 { 0x06, 0x8349 },
2298 { 0x06, 0x1b56 },
2299 { 0x06, 0xab08 },
2300 { 0x06, 0xef56 },
2301 { 0x06, 0xe683 },
2302 { 0x06, 0x48e7 },
2303 { 0x06, 0x8349 },
2304 { 0x06, 0x10d1 },
2305 { 0x06, 0x801f },
2306 { 0x06, 0x66a0 },
2307 { 0x06, 0x04b9 },
2308 { 0x06, 0xe283 },
2309 { 0x06, 0x48e3 },
2310 { 0x06, 0x8349 },
2311 { 0x06, 0xef65 },
2312 { 0x06, 0xe283 },
2313 { 0x06, 0x4ae3 },
2314 { 0x06, 0x834b },
2315 { 0x06, 0x1b56 },
2316 { 0x06, 0xaa0e },
2317 { 0x06, 0xef56 },
2318 { 0x06, 0xe683 },
2319 { 0x06, 0x4ae7 },
2320 { 0x06, 0x834b },
2321 { 0x06, 0xe283 },
2322 { 0x06, 0x4de6 },
2323 { 0x06, 0x834c },
2324 { 0x06, 0xe083 },
2325 { 0x06, 0x4da0 },
2326 { 0x06, 0x000c },
2327 { 0x06, 0xaf81 },
2328 { 0x06, 0x8be0 },
2329 { 0x06, 0x834d },
2330 { 0x06, 0x10e4 },
2331 { 0x06, 0x834d },
2332 { 0x06, 0xae04 },
2333 { 0x06, 0x80e4 },
2334 { 0x06, 0x834d },
2335 { 0x06, 0xe083 },
2336 { 0x06, 0x4e78 },
2337 { 0x06, 0x039e },
2338 { 0x06, 0x0be0 },
2339 { 0x06, 0x834e },
2340 { 0x06, 0x7804 },
2341 { 0x06, 0x9e04 },
2342 { 0x06, 0xee83 },
2343 { 0x06, 0x4e02 },
2344 { 0x06, 0xe083 },
2345 { 0x06, 0x32e1 },
2346 { 0x06, 0x8333 },
2347 { 0x06, 0x590f },
2348 { 0x06, 0xe283 },
2349 { 0x06, 0x4d0c },
2350 { 0x06, 0x245a },
2351 { 0x06, 0xf01e },
2352 { 0x06, 0x12e4 },
2353 { 0x06, 0xf88c },
2354 { 0x06, 0xe5f8 },
2355 { 0x06, 0x8de0 },
2356 { 0x06, 0x8330 },
2357 { 0x06, 0xe183 },
2358 { 0x06, 0x3168 },
2359 { 0x06, 0x01e4 },
2360 { 0x06, 0xf88a },
2361 { 0x06, 0xe5f8 },
2362 { 0x06, 0x8bae },
2363 { 0x06, 0x37ee },
2364 { 0x06, 0x834e },
2365 { 0x06, 0x03e0 },
2366 { 0x06, 0x834c },
2367 { 0x06, 0xe183 },
2368 { 0x06, 0x4d1b },
2369 { 0x06, 0x019e },
2370 { 0x06, 0x04aa },
2371 { 0x06, 0xa1ae },
2372 { 0x06, 0xa8ee },
2373 { 0x06, 0x834e },
2374 { 0x06, 0x04ee },
2375 { 0x06, 0x834f },
2376 { 0x06, 0x00ae },
2377 { 0x06, 0xabe0 },
2378 { 0x06, 0x834f },
2379 { 0x06, 0x7803 },
2380 { 0x06, 0x9f14 },
2381 { 0x06, 0xee83 },
2382 { 0x06, 0x4e05 },
2383 { 0x06, 0xd240 },
2384 { 0x06, 0xd655 },
2385 { 0x06, 0x5402 },
2386 { 0x06, 0x81c6 },
2387 { 0x06, 0xd2a0 },
2388 { 0x06, 0xd6ba },
2389 { 0x06, 0x0002 },
2390 { 0x06, 0x81c6 },
2391 { 0x06, 0xfefd },
2392 { 0x06, 0xfc05 },
2393 { 0x06, 0xf8e0 },
2394 { 0x06, 0xf860 },
2395 { 0x06, 0xe1f8 },
2396 { 0x06, 0x6168 },
2397 { 0x06, 0x02e4 },
2398 { 0x06, 0xf860 },
2399 { 0x06, 0xe5f8 },
2400 { 0x06, 0x61e0 },
2401 { 0x06, 0xf848 },
2402 { 0x06, 0xe1f8 },
2403 { 0x06, 0x4958 },
2404 { 0x06, 0x0f1e },
2405 { 0x06, 0x02e4 },
2406 { 0x06, 0xf848 },
2407 { 0x06, 0xe5f8 },
2408 { 0x06, 0x49d0 },
2409 { 0x06, 0x0002 },
2410 { 0x06, 0x820a },
2411 { 0x06, 0xbf83 },
2412 { 0x06, 0x50ef },
2413 { 0x06, 0x46dc },
2414 { 0x06, 0x19dd },
2415 { 0x06, 0xd001 },
2416 { 0x06, 0x0282 },
2417 { 0x06, 0x0a02 },
2418 { 0x06, 0x8226 },
2419 { 0x06, 0xe0f8 },
2420 { 0x06, 0x60e1 },
2421 { 0x06, 0xf861 },
2422 { 0x06, 0x58fd },
2423 { 0x06, 0xe4f8 },
2424 { 0x06, 0x60e5 },
2425 { 0x06, 0xf861 },
2426 { 0x06, 0xfc04 },
2427 { 0x06, 0xf9fa },
2428 { 0x06, 0xfbc6 },
2429 { 0x06, 0xbff8 },
2430 { 0x06, 0x40be },
2431 { 0x06, 0x8350 },
2432 { 0x06, 0xa001 },
2433 { 0x06, 0x0107 },
2434 { 0x06, 0x1b89 },
2435 { 0x06, 0xcfd2 },
2436 { 0x06, 0x08eb },
2437 { 0x06, 0xdb19 },
2438 { 0x06, 0xb2fb },
2439 { 0x06, 0xfffe },
2440 { 0x06, 0xfd04 },
2441 { 0x06, 0xf8e0 },
2442 { 0x06, 0xf848 },
2443 { 0x06, 0xe1f8 },
2444 { 0x06, 0x4968 },
2445 { 0x06, 0x08e4 },
2446 { 0x06, 0xf848 },
2447 { 0x06, 0xe5f8 },
2448 { 0x06, 0x4958 },
2449 { 0x06, 0xf7e4 },
2450 { 0x06, 0xf848 },
2451 { 0x06, 0xe5f8 },
2452 { 0x06, 0x49fc },
2453 { 0x06, 0x044d },
2454 { 0x06, 0x2000 },
2455 { 0x06, 0x024e },
2456 { 0x06, 0x2200 },
2457 { 0x06, 0x024d },
2458 { 0x06, 0xdfff },
2459 { 0x06, 0x014e },
2460 { 0x06, 0xddff },
2461 { 0x06, 0x0100 },
2462 { 0x05, 0x83d8 },
2463 { 0x06, 0x8000 },
2464 { 0x03, 0xdc00 },
2465 { 0x05, 0xfff6 },
2466 { 0x06, 0x00fc },
2467 { 0x1f, 0x0000 },
2468
2469 { 0x1f, 0x0000 },
2470 { 0x0d, 0xf880 },
2471 { 0x1f, 0x0000 }
2472 };
2473
2474 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2475
2476 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2477 struct phy_reg phy_reg_init[] = {
2478 { 0x1f, 0x0002 },
2479 { 0x05, 0x669a },
2480 { 0x1f, 0x0005 },
2481 { 0x05, 0x8330 },
2482 { 0x06, 0x669a },
2483
2484 { 0x1f, 0x0002 }
2485 };
2486 int val;
2487
2488 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2489
2490 val = mdio_read(ioaddr, 0x0d);
2491 if ((val & 0x00ff) != 0x006c) {
2492 u32 set[] = {
2493 0x0065, 0x0066, 0x0067, 0x0068,
2494 0x0069, 0x006a, 0x006b, 0x006c
2495 };
2496 int i;
2497
2498 mdio_write(ioaddr, 0x1f, 0x0002);
2499
2500 val &= 0xff00;
2501 for (i = 0; i < ARRAY_SIZE(set); i++)
2502 mdio_write(ioaddr, 0x0d, val | set[i]);
2503 }
2504 } else {
2505 struct phy_reg phy_reg_init[] = {
2506 { 0x1f, 0x0002 },
2507 { 0x05, 0x2642 },
2508 { 0x1f, 0x0005 },
2509 { 0x05, 0x8330 },
2510 { 0x06, 0x2642 }
2511 };
2512
2513 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2514 }
2515
2516 mdio_write(ioaddr, 0x1f, 0x0002);
2517 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2518 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2519
2520 mdio_write(ioaddr, 0x1f, 0x0001);
2521 mdio_write(ioaddr, 0x17, 0x0cc0);
2522
2523 mdio_write(ioaddr, 0x1f, 0x0002);
2524 mdio_patch(ioaddr, 0x0f, 0x0017);
2525
2526 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2527 }
2528
2529 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2530 {
2531 struct phy_reg phy_reg_init[] = {
2532 { 0x1f, 0x0002 },
2533 { 0x10, 0x0008 },
2534 { 0x0d, 0x006c },
2535
2536 { 0x1f, 0x0000 },
2537 { 0x0d, 0xf880 },
2538
2539 { 0x1f, 0x0001 },
2540 { 0x17, 0x0cc0 },
2541
2542 { 0x1f, 0x0001 },
2543 { 0x0b, 0xa4d8 },
2544 { 0x09, 0x281c },
2545 { 0x07, 0x2883 },
2546 { 0x0a, 0x6b35 },
2547 { 0x1d, 0x3da4 },
2548 { 0x1c, 0xeffd },
2549 { 0x14, 0x7f52 },
2550 { 0x18, 0x7fc6 },
2551 { 0x08, 0x0601 },
2552 { 0x06, 0x4063 },
2553 { 0x10, 0xf074 },
2554 { 0x1f, 0x0003 },
2555 { 0x13, 0x0789 },
2556 { 0x12, 0xf4bd },
2557 { 0x1a, 0x04fd },
2558 { 0x14, 0x84b0 },
2559 { 0x1f, 0x0000 },
2560 { 0x00, 0x9200 },
2561
2562 { 0x1f, 0x0005 },
2563 { 0x01, 0x0340 },
2564 { 0x1f, 0x0001 },
2565 { 0x04, 0x4000 },
2566 { 0x03, 0x1d21 },
2567 { 0x02, 0x0c32 },
2568 { 0x01, 0x0200 },
2569 { 0x00, 0x5554 },
2570 { 0x04, 0x4800 },
2571 { 0x04, 0x4000 },
2572 { 0x04, 0xf000 },
2573 { 0x03, 0xdf01 },
2574 { 0x02, 0xdf20 },
2575 { 0x01, 0x101a },
2576 { 0x00, 0xa0ff },
2577 { 0x04, 0xf800 },
2578 { 0x04, 0xf000 },
2579 { 0x1f, 0x0000 },
2580
2581 { 0x1f, 0x0007 },
2582 { 0x1e, 0x0023 },
2583 { 0x16, 0x0000 },
2584 { 0x1f, 0x0000 }
2585 };
2586
2587 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2588 }
2589
2590 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2591 {
2592 struct phy_reg phy_reg_init[] = {
2593 { 0x1f, 0x0003 },
2594 { 0x08, 0x441d },
2595 { 0x01, 0x9100 },
2596 { 0x1f, 0x0000 }
2597 };
2598
2599 mdio_write(ioaddr, 0x1f, 0x0000);
2600 mdio_patch(ioaddr, 0x11, 1 << 12);
2601 mdio_patch(ioaddr, 0x19, 1 << 13);
2602 mdio_patch(ioaddr, 0x10, 1 << 15);
2603
2604 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2605 }
2606
2607 static void rtl_hw_phy_config(struct net_device *dev)
2608 {
2609 struct rtl8169_private *tp = netdev_priv(dev);
2610 void __iomem *ioaddr = tp->mmio_addr;
2611
2612 rtl8169_print_mac_version(tp);
2613
2614 switch (tp->mac_version) {
2615 case RTL_GIGA_MAC_VER_01:
2616 break;
2617 case RTL_GIGA_MAC_VER_02:
2618 case RTL_GIGA_MAC_VER_03:
2619 rtl8169s_hw_phy_config(ioaddr);
2620 break;
2621 case RTL_GIGA_MAC_VER_04:
2622 rtl8169sb_hw_phy_config(ioaddr);
2623 break;
2624 case RTL_GIGA_MAC_VER_05:
2625 rtl8169scd_hw_phy_config(tp, ioaddr);
2626 break;
2627 case RTL_GIGA_MAC_VER_06:
2628 rtl8169sce_hw_phy_config(ioaddr);
2629 break;
2630 case RTL_GIGA_MAC_VER_07:
2631 case RTL_GIGA_MAC_VER_08:
2632 case RTL_GIGA_MAC_VER_09:
2633 rtl8102e_hw_phy_config(ioaddr);
2634 break;
2635 case RTL_GIGA_MAC_VER_11:
2636 rtl8168bb_hw_phy_config(ioaddr);
2637 break;
2638 case RTL_GIGA_MAC_VER_12:
2639 rtl8168bef_hw_phy_config(ioaddr);
2640 break;
2641 case RTL_GIGA_MAC_VER_17:
2642 rtl8168bef_hw_phy_config(ioaddr);
2643 break;
2644 case RTL_GIGA_MAC_VER_18:
2645 rtl8168cp_1_hw_phy_config(ioaddr);
2646 break;
2647 case RTL_GIGA_MAC_VER_19:
2648 rtl8168c_1_hw_phy_config(ioaddr);
2649 break;
2650 case RTL_GIGA_MAC_VER_20:
2651 rtl8168c_2_hw_phy_config(ioaddr);
2652 break;
2653 case RTL_GIGA_MAC_VER_21:
2654 rtl8168c_3_hw_phy_config(ioaddr);
2655 break;
2656 case RTL_GIGA_MAC_VER_22:
2657 rtl8168c_4_hw_phy_config(ioaddr);
2658 break;
2659 case RTL_GIGA_MAC_VER_23:
2660 case RTL_GIGA_MAC_VER_24:
2661 rtl8168cp_2_hw_phy_config(ioaddr);
2662 break;
2663 case RTL_GIGA_MAC_VER_25:
2664 rtl8168d_1_hw_phy_config(ioaddr);
2665 break;
2666 case RTL_GIGA_MAC_VER_26:
2667 rtl8168d_2_hw_phy_config(ioaddr);
2668 break;
2669 case RTL_GIGA_MAC_VER_27:
2670 rtl8168d_3_hw_phy_config(ioaddr);
2671 break;
2672
2673 default:
2674 break;
2675 }
2676 }
2677
2678 static void rtl8169_phy_timer(unsigned long __opaque)
2679 {
2680 struct net_device *dev = (struct net_device *)__opaque;
2681 struct rtl8169_private *tp = netdev_priv(dev);
2682 struct timer_list *timer = &tp->timer;
2683 void __iomem *ioaddr = tp->mmio_addr;
2684 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2685
2686 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2687
2688 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2689 return;
2690
2691 spin_lock_irq(&tp->lock);
2692
2693 if (tp->phy_reset_pending(ioaddr)) {
2694 /*
2695 * A busy loop could burn quite a few cycles on nowadays CPU.
2696 * Let's delay the execution of the timer for a few ticks.
2697 */
2698 timeout = HZ/10;
2699 goto out_mod_timer;
2700 }
2701
2702 if (tp->link_ok(ioaddr))
2703 goto out_unlock;
2704
2705 if (netif_msg_link(tp))
2706 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
2707
2708 tp->phy_reset_enable(ioaddr);
2709
2710 out_mod_timer:
2711 mod_timer(timer, jiffies + timeout);
2712 out_unlock:
2713 spin_unlock_irq(&tp->lock);
2714 }
2715
2716 static inline void rtl8169_delete_timer(struct net_device *dev)
2717 {
2718 struct rtl8169_private *tp = netdev_priv(dev);
2719 struct timer_list *timer = &tp->timer;
2720
2721 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2722 return;
2723
2724 del_timer_sync(timer);
2725 }
2726
2727 static inline void rtl8169_request_timer(struct net_device *dev)
2728 {
2729 struct rtl8169_private *tp = netdev_priv(dev);
2730 struct timer_list *timer = &tp->timer;
2731
2732 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2733 return;
2734
2735 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2736 }
2737
2738 #ifdef CONFIG_NET_POLL_CONTROLLER
2739 /*
2740 * Polling 'interrupt' - used by things like netconsole to send skbs
2741 * without having to re-enable interrupts. It's not called while
2742 * the interrupt routine is executing.
2743 */
2744 static void rtl8169_netpoll(struct net_device *dev)
2745 {
2746 struct rtl8169_private *tp = netdev_priv(dev);
2747 struct pci_dev *pdev = tp->pci_dev;
2748
2749 disable_irq(pdev->irq);
2750 rtl8169_interrupt(pdev->irq, dev);
2751 enable_irq(pdev->irq);
2752 }
2753 #endif
2754
2755 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2756 void __iomem *ioaddr)
2757 {
2758 iounmap(ioaddr);
2759 pci_release_regions(pdev);
2760 pci_disable_device(pdev);
2761 free_netdev(dev);
2762 }
2763
2764 static void rtl8169_phy_reset(struct net_device *dev,
2765 struct rtl8169_private *tp)
2766 {
2767 void __iomem *ioaddr = tp->mmio_addr;
2768 unsigned int i;
2769
2770 tp->phy_reset_enable(ioaddr);
2771 for (i = 0; i < 100; i++) {
2772 if (!tp->phy_reset_pending(ioaddr))
2773 return;
2774 msleep(1);
2775 }
2776 if (netif_msg_link(tp))
2777 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
2778 }
2779
2780 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2781 {
2782 void __iomem *ioaddr = tp->mmio_addr;
2783
2784 rtl_hw_phy_config(dev);
2785
2786 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2787 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2788 RTL_W8(0x82, 0x01);
2789 }
2790
2791 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2792
2793 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2794 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2795
2796 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2797 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2798 RTL_W8(0x82, 0x01);
2799 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2800 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2801 }
2802
2803 rtl8169_phy_reset(dev, tp);
2804
2805 /*
2806 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2807 * only 8101. Don't panic.
2808 */
2809 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2810
2811 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
2812 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
2813 }
2814
2815 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2816 {
2817 void __iomem *ioaddr = tp->mmio_addr;
2818 u32 high;
2819 u32 low;
2820
2821 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2822 high = addr[4] | (addr[5] << 8);
2823
2824 spin_lock_irq(&tp->lock);
2825
2826 RTL_W8(Cfg9346, Cfg9346_Unlock);
2827 RTL_W32(MAC0, low);
2828 RTL_W32(MAC4, high);
2829 RTL_W8(Cfg9346, Cfg9346_Lock);
2830
2831 spin_unlock_irq(&tp->lock);
2832 }
2833
2834 static int rtl_set_mac_address(struct net_device *dev, void *p)
2835 {
2836 struct rtl8169_private *tp = netdev_priv(dev);
2837 struct sockaddr *addr = p;
2838
2839 if (!is_valid_ether_addr(addr->sa_data))
2840 return -EADDRNOTAVAIL;
2841
2842 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2843
2844 rtl_rar_set(tp, dev->dev_addr);
2845
2846 return 0;
2847 }
2848
2849 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2850 {
2851 struct rtl8169_private *tp = netdev_priv(dev);
2852 struct mii_ioctl_data *data = if_mii(ifr);
2853
2854 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2855 }
2856
2857 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2858 {
2859 switch (cmd) {
2860 case SIOCGMIIPHY:
2861 data->phy_id = 32; /* Internal PHY */
2862 return 0;
2863
2864 case SIOCGMIIREG:
2865 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2866 return 0;
2867
2868 case SIOCSMIIREG:
2869 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2870 return 0;
2871 }
2872 return -EOPNOTSUPP;
2873 }
2874
2875 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2876 {
2877 return -EOPNOTSUPP;
2878 }
2879
2880 static const struct rtl_cfg_info {
2881 void (*hw_start)(struct net_device *);
2882 unsigned int region;
2883 unsigned int align;
2884 u16 intr_event;
2885 u16 napi_event;
2886 unsigned features;
2887 u8 default_ver;
2888 } rtl_cfg_infos [] = {
2889 [RTL_CFG_0] = {
2890 .hw_start = rtl_hw_start_8169,
2891 .region = 1,
2892 .align = 0,
2893 .intr_event = SYSErr | LinkChg | RxOverflow |
2894 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2895 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2896 .features = RTL_FEATURE_GMII,
2897 .default_ver = RTL_GIGA_MAC_VER_01,
2898 },
2899 [RTL_CFG_1] = {
2900 .hw_start = rtl_hw_start_8168,
2901 .region = 2,
2902 .align = 8,
2903 .intr_event = SYSErr | LinkChg | RxOverflow |
2904 TxErr | TxOK | RxOK | RxErr,
2905 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2906 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2907 .default_ver = RTL_GIGA_MAC_VER_11,
2908 },
2909 [RTL_CFG_2] = {
2910 .hw_start = rtl_hw_start_8101,
2911 .region = 2,
2912 .align = 8,
2913 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2914 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2915 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2916 .features = RTL_FEATURE_MSI,
2917 .default_ver = RTL_GIGA_MAC_VER_13,
2918 }
2919 };
2920
2921 /* Cfg9346_Unlock assumed. */
2922 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2923 const struct rtl_cfg_info *cfg)
2924 {
2925 unsigned msi = 0;
2926 u8 cfg2;
2927
2928 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2929 if (cfg->features & RTL_FEATURE_MSI) {
2930 if (pci_enable_msi(pdev)) {
2931 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2932 } else {
2933 cfg2 |= MSIEnable;
2934 msi = RTL_FEATURE_MSI;
2935 }
2936 }
2937 RTL_W8(Config2, cfg2);
2938 return msi;
2939 }
2940
2941 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2942 {
2943 if (tp->features & RTL_FEATURE_MSI) {
2944 pci_disable_msi(pdev);
2945 tp->features &= ~RTL_FEATURE_MSI;
2946 }
2947 }
2948
2949 static const struct net_device_ops rtl8169_netdev_ops = {
2950 .ndo_open = rtl8169_open,
2951 .ndo_stop = rtl8169_close,
2952 .ndo_get_stats = rtl8169_get_stats,
2953 .ndo_start_xmit = rtl8169_start_xmit,
2954 .ndo_tx_timeout = rtl8169_tx_timeout,
2955 .ndo_validate_addr = eth_validate_addr,
2956 .ndo_change_mtu = rtl8169_change_mtu,
2957 .ndo_set_mac_address = rtl_set_mac_address,
2958 .ndo_do_ioctl = rtl8169_ioctl,
2959 .ndo_set_multicast_list = rtl_set_rx_mode,
2960 #ifdef CONFIG_R8169_VLAN
2961 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2962 #endif
2963 #ifdef CONFIG_NET_POLL_CONTROLLER
2964 .ndo_poll_controller = rtl8169_netpoll,
2965 #endif
2966
2967 };
2968
2969 static int __devinit
2970 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2971 {
2972 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2973 const unsigned int region = cfg->region;
2974 struct rtl8169_private *tp;
2975 struct mii_if_info *mii;
2976 struct net_device *dev;
2977 void __iomem *ioaddr;
2978 unsigned int i;
2979 int rc;
2980
2981 if (netif_msg_drv(&debug)) {
2982 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2983 MODULENAME, RTL8169_VERSION);
2984 }
2985
2986 dev = alloc_etherdev(sizeof (*tp));
2987 if (!dev) {
2988 if (netif_msg_drv(&debug))
2989 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2990 rc = -ENOMEM;
2991 goto out;
2992 }
2993
2994 SET_NETDEV_DEV(dev, &pdev->dev);
2995 dev->netdev_ops = &rtl8169_netdev_ops;
2996 tp = netdev_priv(dev);
2997 tp->dev = dev;
2998 tp->pci_dev = pdev;
2999 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3000
3001 mii = &tp->mii;
3002 mii->dev = dev;
3003 mii->mdio_read = rtl_mdio_read;
3004 mii->mdio_write = rtl_mdio_write;
3005 mii->phy_id_mask = 0x1f;
3006 mii->reg_num_mask = 0x1f;
3007 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3008
3009 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3010 rc = pci_enable_device(pdev);
3011 if (rc < 0) {
3012 if (netif_msg_probe(tp))
3013 dev_err(&pdev->dev, "enable failure\n");
3014 goto err_out_free_dev_1;
3015 }
3016
3017 rc = pci_set_mwi(pdev);
3018 if (rc < 0)
3019 goto err_out_disable_2;
3020
3021 /* make sure PCI base addr 1 is MMIO */
3022 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3023 if (netif_msg_probe(tp)) {
3024 dev_err(&pdev->dev,
3025 "region #%d not an MMIO resource, aborting\n",
3026 region);
3027 }
3028 rc = -ENODEV;
3029 goto err_out_mwi_3;
3030 }
3031
3032 /* check for weird/broken PCI region reporting */
3033 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3034 if (netif_msg_probe(tp)) {
3035 dev_err(&pdev->dev,
3036 "Invalid PCI region size(s), aborting\n");
3037 }
3038 rc = -ENODEV;
3039 goto err_out_mwi_3;
3040 }
3041
3042 rc = pci_request_regions(pdev, MODULENAME);
3043 if (rc < 0) {
3044 if (netif_msg_probe(tp))
3045 dev_err(&pdev->dev, "could not request regions.\n");
3046 goto err_out_mwi_3;
3047 }
3048
3049 tp->cp_cmd = PCIMulRW | RxChkSum;
3050
3051 if ((sizeof(dma_addr_t) > 4) &&
3052 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3053 tp->cp_cmd |= PCIDAC;
3054 dev->features |= NETIF_F_HIGHDMA;
3055 } else {
3056 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3057 if (rc < 0) {
3058 if (netif_msg_probe(tp)) {
3059 dev_err(&pdev->dev,
3060 "DMA configuration failed.\n");
3061 }
3062 goto err_out_free_res_4;
3063 }
3064 }
3065
3066 /* ioremap MMIO region */
3067 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3068 if (!ioaddr) {
3069 if (netif_msg_probe(tp))
3070 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
3071 rc = -EIO;
3072 goto err_out_free_res_4;
3073 }
3074
3075 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3076 if (!tp->pcie_cap && netif_msg_probe(tp))
3077 dev_info(&pdev->dev, "no PCI Express capability\n");
3078
3079 RTL_W16(IntrMask, 0x0000);
3080
3081 /* Soft reset the chip. */
3082 RTL_W8(ChipCmd, CmdReset);
3083
3084 /* Check that the chip has finished the reset. */
3085 for (i = 0; i < 100; i++) {
3086 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3087 break;
3088 msleep_interruptible(1);
3089 }
3090
3091 RTL_W16(IntrStatus, 0xffff);
3092
3093 pci_set_master(pdev);
3094
3095 /* Identify chip attached to board */
3096 rtl8169_get_mac_version(tp, ioaddr);
3097
3098 /* Use appropriate default if unknown */
3099 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3100 if (netif_msg_probe(tp)) {
3101 dev_notice(&pdev->dev,
3102 "unknown MAC, using family default\n");
3103 }
3104 tp->mac_version = cfg->default_ver;
3105 }
3106
3107 rtl8169_print_mac_version(tp);
3108
3109 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3110 if (tp->mac_version == rtl_chip_info[i].mac_version)
3111 break;
3112 }
3113 if (i == ARRAY_SIZE(rtl_chip_info)) {
3114 dev_err(&pdev->dev,
3115 "driver bug, MAC version not found in rtl_chip_info\n");
3116 goto err_out_msi_5;
3117 }
3118 tp->chipset = i;
3119
3120 RTL_W8(Cfg9346, Cfg9346_Unlock);
3121 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3122 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3123 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3124 tp->features |= RTL_FEATURE_WOL;
3125 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3126 tp->features |= RTL_FEATURE_WOL;
3127 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3128 RTL_W8(Cfg9346, Cfg9346_Lock);
3129
3130 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3131 (RTL_R8(PHYstatus) & TBI_Enable)) {
3132 tp->set_speed = rtl8169_set_speed_tbi;
3133 tp->get_settings = rtl8169_gset_tbi;
3134 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3135 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3136 tp->link_ok = rtl8169_tbi_link_ok;
3137 tp->do_ioctl = rtl_tbi_ioctl;
3138
3139 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3140 } else {
3141 tp->set_speed = rtl8169_set_speed_xmii;
3142 tp->get_settings = rtl8169_gset_xmii;
3143 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3144 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3145 tp->link_ok = rtl8169_xmii_link_ok;
3146 tp->do_ioctl = rtl_xmii_ioctl;
3147 }
3148
3149 spin_lock_init(&tp->lock);
3150
3151 tp->mmio_addr = ioaddr;
3152
3153 /* Get MAC address */
3154 for (i = 0; i < MAC_ADDR_LEN; i++)
3155 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3156 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3157
3158 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3159 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3160 dev->irq = pdev->irq;
3161 dev->base_addr = (unsigned long) ioaddr;
3162
3163 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3164
3165 #ifdef CONFIG_R8169_VLAN
3166 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3167 #endif
3168
3169 tp->intr_mask = 0xffff;
3170 tp->align = cfg->align;
3171 tp->hw_start = cfg->hw_start;
3172 tp->intr_event = cfg->intr_event;
3173 tp->napi_event = cfg->napi_event;
3174
3175 init_timer(&tp->timer);
3176 tp->timer.data = (unsigned long) dev;
3177 tp->timer.function = rtl8169_phy_timer;
3178
3179 rc = register_netdev(dev);
3180 if (rc < 0)
3181 goto err_out_msi_5;
3182
3183 pci_set_drvdata(pdev, dev);
3184
3185 if (netif_msg_probe(tp)) {
3186 u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff;
3187
3188 printk(KERN_INFO "%s: %s at 0x%lx, "
3189 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
3190 "XID %08x IRQ %d\n",
3191 dev->name,
3192 rtl_chip_info[tp->chipset].name,
3193 dev->base_addr,
3194 dev->dev_addr[0], dev->dev_addr[1],
3195 dev->dev_addr[2], dev->dev_addr[3],
3196 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
3197 }
3198
3199 rtl8169_init_phy(dev, tp);
3200 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3201
3202 out:
3203 return rc;
3204
3205 err_out_msi_5:
3206 rtl_disable_msi(pdev, tp);
3207 iounmap(ioaddr);
3208 err_out_free_res_4:
3209 pci_release_regions(pdev);
3210 err_out_mwi_3:
3211 pci_clear_mwi(pdev);
3212 err_out_disable_2:
3213 pci_disable_device(pdev);
3214 err_out_free_dev_1:
3215 free_netdev(dev);
3216 goto out;
3217 }
3218
3219 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3220 {
3221 struct net_device *dev = pci_get_drvdata(pdev);
3222 struct rtl8169_private *tp = netdev_priv(dev);
3223
3224 flush_scheduled_work();
3225
3226 unregister_netdev(dev);
3227 rtl_disable_msi(pdev, tp);
3228 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3229 pci_set_drvdata(pdev, NULL);
3230 }
3231
3232 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3233 struct net_device *dev)
3234 {
3235 unsigned int mtu = dev->mtu;
3236
3237 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
3238 }
3239
3240 static int rtl8169_open(struct net_device *dev)
3241 {
3242 struct rtl8169_private *tp = netdev_priv(dev);
3243 struct pci_dev *pdev = tp->pci_dev;
3244 int retval = -ENOMEM;
3245
3246
3247 rtl8169_set_rxbufsize(tp, dev);
3248
3249 /*
3250 * Rx and Tx desscriptors needs 256 bytes alignment.
3251 * pci_alloc_consistent provides more.
3252 */
3253 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3254 &tp->TxPhyAddr);
3255 if (!tp->TxDescArray)
3256 goto out;
3257
3258 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3259 &tp->RxPhyAddr);
3260 if (!tp->RxDescArray)
3261 goto err_free_tx_0;
3262
3263 retval = rtl8169_init_ring(dev);
3264 if (retval < 0)
3265 goto err_free_rx_1;
3266
3267 INIT_DELAYED_WORK(&tp->task, NULL);
3268
3269 smp_mb();
3270
3271 retval = request_irq(dev->irq, rtl8169_interrupt,
3272 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3273 dev->name, dev);
3274 if (retval < 0)
3275 goto err_release_ring_2;
3276
3277 napi_enable(&tp->napi);
3278
3279 rtl_hw_start(dev);
3280
3281 rtl8169_request_timer(dev);
3282
3283 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3284 out:
3285 return retval;
3286
3287 err_release_ring_2:
3288 rtl8169_rx_clear(tp);
3289 err_free_rx_1:
3290 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3291 tp->RxPhyAddr);
3292 err_free_tx_0:
3293 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3294 tp->TxPhyAddr);
3295 goto out;
3296 }
3297
3298 static void rtl8169_hw_reset(void __iomem *ioaddr)
3299 {
3300 /* Disable interrupts */
3301 rtl8169_irq_mask_and_ack(ioaddr);
3302
3303 /* Reset the chipset */
3304 RTL_W8(ChipCmd, CmdReset);
3305
3306 /* PCI commit */
3307 RTL_R8(ChipCmd);
3308 }
3309
3310 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3311 {
3312 void __iomem *ioaddr = tp->mmio_addr;
3313 u32 cfg = rtl8169_rx_config;
3314
3315 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3316 RTL_W32(RxConfig, cfg);
3317
3318 /* Set DMA burst size and Interframe Gap Time */
3319 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3320 (InterFrameGap << TxInterFrameGapShift));
3321 }
3322
3323 static void rtl_hw_start(struct net_device *dev)
3324 {
3325 struct rtl8169_private *tp = netdev_priv(dev);
3326 void __iomem *ioaddr = tp->mmio_addr;
3327 unsigned int i;
3328
3329 /* Soft reset the chip. */
3330 RTL_W8(ChipCmd, CmdReset);
3331
3332 /* Check that the chip has finished the reset. */
3333 for (i = 0; i < 100; i++) {
3334 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3335 break;
3336 msleep_interruptible(1);
3337 }
3338
3339 tp->hw_start(dev);
3340
3341 netif_start_queue(dev);
3342 }
3343
3344
3345 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3346 void __iomem *ioaddr)
3347 {
3348 /*
3349 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3350 * register to be written before TxDescAddrLow to work.
3351 * Switching from MMIO to I/O access fixes the issue as well.
3352 */
3353 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3354 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3355 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3356 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3357 }
3358
3359 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3360 {
3361 u16 cmd;
3362
3363 cmd = RTL_R16(CPlusCmd);
3364 RTL_W16(CPlusCmd, cmd);
3365 return cmd;
3366 }
3367
3368 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3369 {
3370 /* Low hurts. Let's disable the filtering. */
3371 RTL_W16(RxMaxSize, rx_buf_sz);
3372 }
3373
3374 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3375 {
3376 struct {
3377 u32 mac_version;
3378 u32 clk;
3379 u32 val;
3380 } cfg2_info [] = {
3381 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3382 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3383 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3384 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3385 }, *p = cfg2_info;
3386 unsigned int i;
3387 u32 clk;
3388
3389 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3390 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3391 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3392 RTL_W32(0x7c, p->val);
3393 break;
3394 }
3395 }
3396 }
3397
3398 static void rtl_hw_start_8169(struct net_device *dev)
3399 {
3400 struct rtl8169_private *tp = netdev_priv(dev);
3401 void __iomem *ioaddr = tp->mmio_addr;
3402 struct pci_dev *pdev = tp->pci_dev;
3403
3404 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3405 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3406 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3407 }
3408
3409 RTL_W8(Cfg9346, Cfg9346_Unlock);
3410 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3411 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3412 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3413 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3414 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3415
3416 RTL_W8(EarlyTxThres, EarlyTxThld);
3417
3418 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3419
3420 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3421 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3422 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3423 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3424 rtl_set_rx_tx_config_registers(tp);
3425
3426 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3427
3428 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3429 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3430 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3431 "Bit-3 and bit-14 MUST be 1\n");
3432 tp->cp_cmd |= (1 << 14);
3433 }
3434
3435 RTL_W16(CPlusCmd, tp->cp_cmd);
3436
3437 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3438
3439 /*
3440 * Undocumented corner. Supposedly:
3441 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3442 */
3443 RTL_W16(IntrMitigate, 0x0000);
3444
3445 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3446
3447 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3448 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3449 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3450 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3451 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3452 rtl_set_rx_tx_config_registers(tp);
3453 }
3454
3455 RTL_W8(Cfg9346, Cfg9346_Lock);
3456
3457 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3458 RTL_R8(IntrMask);
3459
3460 RTL_W32(RxMissed, 0);
3461
3462 rtl_set_rx_mode(dev);
3463
3464 /* no early-rx interrupts */
3465 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3466
3467 /* Enable all known interrupts by setting the interrupt mask. */
3468 RTL_W16(IntrMask, tp->intr_event);
3469 }
3470
3471 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3472 {
3473 struct net_device *dev = pci_get_drvdata(pdev);
3474 struct rtl8169_private *tp = netdev_priv(dev);
3475 int cap = tp->pcie_cap;
3476
3477 if (cap) {
3478 u16 ctl;
3479
3480 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3481 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3482 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3483 }
3484 }
3485
3486 static void rtl_csi_access_enable(void __iomem *ioaddr)
3487 {
3488 u32 csi;
3489
3490 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3491 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3492 }
3493
3494 struct ephy_info {
3495 unsigned int offset;
3496 u16 mask;
3497 u16 bits;
3498 };
3499
3500 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
3501 {
3502 u16 w;
3503
3504 while (len-- > 0) {
3505 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3506 rtl_ephy_write(ioaddr, e->offset, w);
3507 e++;
3508 }
3509 }
3510
3511 static void rtl_disable_clock_request(struct pci_dev *pdev)
3512 {
3513 struct net_device *dev = pci_get_drvdata(pdev);
3514 struct rtl8169_private *tp = netdev_priv(dev);
3515 int cap = tp->pcie_cap;
3516
3517 if (cap) {
3518 u16 ctl;
3519
3520 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3521 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3522 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3523 }
3524 }
3525
3526 #define R8168_CPCMD_QUIRK_MASK (\
3527 EnableBist | \
3528 Mac_dbgo_oe | \
3529 Force_half_dup | \
3530 Force_rxflow_en | \
3531 Force_txflow_en | \
3532 Cxpl_dbg_sel | \
3533 ASF | \
3534 PktCntrDisable | \
3535 Mac_dbgo_sel)
3536
3537 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3538 {
3539 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3540
3541 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3542
3543 rtl_tx_performance_tweak(pdev,
3544 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3545 }
3546
3547 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3548 {
3549 rtl_hw_start_8168bb(ioaddr, pdev);
3550
3551 RTL_W8(EarlyTxThres, EarlyTxThld);
3552
3553 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3554 }
3555
3556 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3557 {
3558 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3559
3560 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3561
3562 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3563
3564 rtl_disable_clock_request(pdev);
3565
3566 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3567 }
3568
3569 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3570 {
3571 static struct ephy_info e_info_8168cp[] = {
3572 { 0x01, 0, 0x0001 },
3573 { 0x02, 0x0800, 0x1000 },
3574 { 0x03, 0, 0x0042 },
3575 { 0x06, 0x0080, 0x0000 },
3576 { 0x07, 0, 0x2000 }
3577 };
3578
3579 rtl_csi_access_enable(ioaddr);
3580
3581 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3582
3583 __rtl_hw_start_8168cp(ioaddr, pdev);
3584 }
3585
3586 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3587 {
3588 rtl_csi_access_enable(ioaddr);
3589
3590 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3591
3592 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3593
3594 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3595 }
3596
3597 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3598 {
3599 rtl_csi_access_enable(ioaddr);
3600
3601 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3602
3603 /* Magic. */
3604 RTL_W8(DBG_REG, 0x20);
3605
3606 RTL_W8(EarlyTxThres, EarlyTxThld);
3607
3608 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3609
3610 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3611 }
3612
3613 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3614 {
3615 static struct ephy_info e_info_8168c_1[] = {
3616 { 0x02, 0x0800, 0x1000 },
3617 { 0x03, 0, 0x0002 },
3618 { 0x06, 0x0080, 0x0000 }
3619 };
3620
3621 rtl_csi_access_enable(ioaddr);
3622
3623 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3624
3625 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3626
3627 __rtl_hw_start_8168cp(ioaddr, pdev);
3628 }
3629
3630 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3631 {
3632 static struct ephy_info e_info_8168c_2[] = {
3633 { 0x01, 0, 0x0001 },
3634 { 0x03, 0x0400, 0x0220 }
3635 };
3636
3637 rtl_csi_access_enable(ioaddr);
3638
3639 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3640
3641 __rtl_hw_start_8168cp(ioaddr, pdev);
3642 }
3643
3644 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3645 {
3646 rtl_hw_start_8168c_2(ioaddr, pdev);
3647 }
3648
3649 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3650 {
3651 rtl_csi_access_enable(ioaddr);
3652
3653 __rtl_hw_start_8168cp(ioaddr, pdev);
3654 }
3655
3656 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3657 {
3658 rtl_csi_access_enable(ioaddr);
3659
3660 rtl_disable_clock_request(pdev);
3661
3662 RTL_W8(EarlyTxThres, EarlyTxThld);
3663
3664 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3665
3666 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3667 }
3668
3669 static void rtl_hw_start_8168(struct net_device *dev)
3670 {
3671 struct rtl8169_private *tp = netdev_priv(dev);
3672 void __iomem *ioaddr = tp->mmio_addr;
3673 struct pci_dev *pdev = tp->pci_dev;
3674
3675 RTL_W8(Cfg9346, Cfg9346_Unlock);
3676
3677 RTL_W8(EarlyTxThres, EarlyTxThld);
3678
3679 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3680
3681 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3682
3683 RTL_W16(CPlusCmd, tp->cp_cmd);
3684
3685 RTL_W16(IntrMitigate, 0x5151);
3686
3687 /* Work around for RxFIFO overflow. */
3688 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3689 tp->intr_event |= RxFIFOOver | PCSTimeout;
3690 tp->intr_event &= ~RxOverflow;
3691 }
3692
3693 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3694
3695 rtl_set_rx_mode(dev);
3696
3697 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3698 (InterFrameGap << TxInterFrameGapShift));
3699
3700 RTL_R8(IntrMask);
3701
3702 switch (tp->mac_version) {
3703 case RTL_GIGA_MAC_VER_11:
3704 rtl_hw_start_8168bb(ioaddr, pdev);
3705 break;
3706
3707 case RTL_GIGA_MAC_VER_12:
3708 case RTL_GIGA_MAC_VER_17:
3709 rtl_hw_start_8168bef(ioaddr, pdev);
3710 break;
3711
3712 case RTL_GIGA_MAC_VER_18:
3713 rtl_hw_start_8168cp_1(ioaddr, pdev);
3714 break;
3715
3716 case RTL_GIGA_MAC_VER_19:
3717 rtl_hw_start_8168c_1(ioaddr, pdev);
3718 break;
3719
3720 case RTL_GIGA_MAC_VER_20:
3721 rtl_hw_start_8168c_2(ioaddr, pdev);
3722 break;
3723
3724 case RTL_GIGA_MAC_VER_21:
3725 rtl_hw_start_8168c_3(ioaddr, pdev);
3726 break;
3727
3728 case RTL_GIGA_MAC_VER_22:
3729 rtl_hw_start_8168c_4(ioaddr, pdev);
3730 break;
3731
3732 case RTL_GIGA_MAC_VER_23:
3733 rtl_hw_start_8168cp_2(ioaddr, pdev);
3734 break;
3735
3736 case RTL_GIGA_MAC_VER_24:
3737 rtl_hw_start_8168cp_3(ioaddr, pdev);
3738 break;
3739
3740 case RTL_GIGA_MAC_VER_25:
3741 case RTL_GIGA_MAC_VER_26:
3742 case RTL_GIGA_MAC_VER_27:
3743 rtl_hw_start_8168d(ioaddr, pdev);
3744 break;
3745
3746 default:
3747 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3748 dev->name, tp->mac_version);
3749 break;
3750 }
3751
3752 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3753
3754 RTL_W8(Cfg9346, Cfg9346_Lock);
3755
3756 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3757
3758 RTL_W16(IntrMask, tp->intr_event);
3759 }
3760
3761 #define R810X_CPCMD_QUIRK_MASK (\
3762 EnableBist | \
3763 Mac_dbgo_oe | \
3764 Force_half_dup | \
3765 Force_rxflow_en | \
3766 Force_txflow_en | \
3767 Cxpl_dbg_sel | \
3768 ASF | \
3769 PktCntrDisable | \
3770 PCIDAC | \
3771 PCIMulRW)
3772
3773 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3774 {
3775 static struct ephy_info e_info_8102e_1[] = {
3776 { 0x01, 0, 0x6e65 },
3777 { 0x02, 0, 0x091f },
3778 { 0x03, 0, 0xc2f9 },
3779 { 0x06, 0, 0xafb5 },
3780 { 0x07, 0, 0x0e00 },
3781 { 0x19, 0, 0xec80 },
3782 { 0x01, 0, 0x2e65 },
3783 { 0x01, 0, 0x6e65 }
3784 };
3785 u8 cfg1;
3786
3787 rtl_csi_access_enable(ioaddr);
3788
3789 RTL_W8(DBG_REG, FIX_NAK_1);
3790
3791 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3792
3793 RTL_W8(Config1,
3794 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3795 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3796
3797 cfg1 = RTL_R8(Config1);
3798 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3799 RTL_W8(Config1, cfg1 & ~LEDS0);
3800
3801 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3802
3803 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3804 }
3805
3806 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3807 {
3808 rtl_csi_access_enable(ioaddr);
3809
3810 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3811
3812 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3813 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3814
3815 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3816 }
3817
3818 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3819 {
3820 rtl_hw_start_8102e_2(ioaddr, pdev);
3821
3822 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3823 }
3824
3825 static void rtl_hw_start_8101(struct net_device *dev)
3826 {
3827 struct rtl8169_private *tp = netdev_priv(dev);
3828 void __iomem *ioaddr = tp->mmio_addr;
3829 struct pci_dev *pdev = tp->pci_dev;
3830
3831 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3832 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3833 int cap = tp->pcie_cap;
3834
3835 if (cap) {
3836 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3837 PCI_EXP_DEVCTL_NOSNOOP_EN);
3838 }
3839 }
3840
3841 switch (tp->mac_version) {
3842 case RTL_GIGA_MAC_VER_07:
3843 rtl_hw_start_8102e_1(ioaddr, pdev);
3844 break;
3845
3846 case RTL_GIGA_MAC_VER_08:
3847 rtl_hw_start_8102e_3(ioaddr, pdev);
3848 break;
3849
3850 case RTL_GIGA_MAC_VER_09:
3851 rtl_hw_start_8102e_2(ioaddr, pdev);
3852 break;
3853 }
3854
3855 RTL_W8(Cfg9346, Cfg9346_Unlock);
3856
3857 RTL_W8(EarlyTxThres, EarlyTxThld);
3858
3859 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3860
3861 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3862
3863 RTL_W16(CPlusCmd, tp->cp_cmd);
3864
3865 RTL_W16(IntrMitigate, 0x0000);
3866
3867 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3868
3869 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3870 rtl_set_rx_tx_config_registers(tp);
3871
3872 RTL_W8(Cfg9346, Cfg9346_Lock);
3873
3874 RTL_R8(IntrMask);
3875
3876 rtl_set_rx_mode(dev);
3877
3878 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3879
3880 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3881
3882 RTL_W16(IntrMask, tp->intr_event);
3883 }
3884
3885 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3886 {
3887 struct rtl8169_private *tp = netdev_priv(dev);
3888 int ret = 0;
3889
3890 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3891 return -EINVAL;
3892
3893 dev->mtu = new_mtu;
3894
3895 if (!netif_running(dev))
3896 goto out;
3897
3898 rtl8169_down(dev);
3899
3900 rtl8169_set_rxbufsize(tp, dev);
3901
3902 ret = rtl8169_init_ring(dev);
3903 if (ret < 0)
3904 goto out;
3905
3906 napi_enable(&tp->napi);
3907
3908 rtl_hw_start(dev);
3909
3910 rtl8169_request_timer(dev);
3911
3912 out:
3913 return ret;
3914 }
3915
3916 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3917 {
3918 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3919 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3920 }
3921
3922 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3923 struct sk_buff **sk_buff, struct RxDesc *desc)
3924 {
3925 struct pci_dev *pdev = tp->pci_dev;
3926
3927 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3928 PCI_DMA_FROMDEVICE);
3929 dev_kfree_skb(*sk_buff);
3930 *sk_buff = NULL;
3931 rtl8169_make_unusable_by_asic(desc);
3932 }
3933
3934 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3935 {
3936 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3937
3938 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3939 }
3940
3941 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3942 u32 rx_buf_sz)
3943 {
3944 desc->addr = cpu_to_le64(mapping);
3945 wmb();
3946 rtl8169_mark_to_asic(desc, rx_buf_sz);
3947 }
3948
3949 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3950 struct net_device *dev,
3951 struct RxDesc *desc, int rx_buf_sz,
3952 unsigned int align)
3953 {
3954 struct sk_buff *skb;
3955 dma_addr_t mapping;
3956 unsigned int pad;
3957
3958 pad = align ? align : NET_IP_ALIGN;
3959
3960 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
3961 if (!skb)
3962 goto err_out;
3963
3964 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
3965
3966 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
3967 PCI_DMA_FROMDEVICE);
3968
3969 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3970 out:
3971 return skb;
3972
3973 err_out:
3974 rtl8169_make_unusable_by_asic(desc);
3975 goto out;
3976 }
3977
3978 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3979 {
3980 unsigned int i;
3981
3982 for (i = 0; i < NUM_RX_DESC; i++) {
3983 if (tp->Rx_skbuff[i]) {
3984 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3985 tp->RxDescArray + i);
3986 }
3987 }
3988 }
3989
3990 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3991 u32 start, u32 end)
3992 {
3993 u32 cur;
3994
3995 for (cur = start; end - cur != 0; cur++) {
3996 struct sk_buff *skb;
3997 unsigned int i = cur % NUM_RX_DESC;
3998
3999 WARN_ON((s32)(end - cur) < 0);
4000
4001 if (tp->Rx_skbuff[i])
4002 continue;
4003
4004 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4005 tp->RxDescArray + i,
4006 tp->rx_buf_sz, tp->align);
4007 if (!skb)
4008 break;
4009
4010 tp->Rx_skbuff[i] = skb;
4011 }
4012 return cur - start;
4013 }
4014
4015 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4016 {
4017 desc->opts1 |= cpu_to_le32(RingEnd);
4018 }
4019
4020 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4021 {
4022 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4023 }
4024
4025 static int rtl8169_init_ring(struct net_device *dev)
4026 {
4027 struct rtl8169_private *tp = netdev_priv(dev);
4028
4029 rtl8169_init_ring_indexes(tp);
4030
4031 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4032 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4033
4034 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4035 goto err_out;
4036
4037 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4038
4039 return 0;
4040
4041 err_out:
4042 rtl8169_rx_clear(tp);
4043 return -ENOMEM;
4044 }
4045
4046 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4047 struct TxDesc *desc)
4048 {
4049 unsigned int len = tx_skb->len;
4050
4051 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4052 desc->opts1 = 0x00;
4053 desc->opts2 = 0x00;
4054 desc->addr = 0x00;
4055 tx_skb->len = 0;
4056 }
4057
4058 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4059 {
4060 unsigned int i;
4061
4062 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4063 unsigned int entry = i % NUM_TX_DESC;
4064 struct ring_info *tx_skb = tp->tx_skb + entry;
4065 unsigned int len = tx_skb->len;
4066
4067 if (len) {
4068 struct sk_buff *skb = tx_skb->skb;
4069
4070 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4071 tp->TxDescArray + entry);
4072 if (skb) {
4073 dev_kfree_skb(skb);
4074 tx_skb->skb = NULL;
4075 }
4076 tp->dev->stats.tx_dropped++;
4077 }
4078 }
4079 tp->cur_tx = tp->dirty_tx = 0;
4080 }
4081
4082 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4083 {
4084 struct rtl8169_private *tp = netdev_priv(dev);
4085
4086 PREPARE_DELAYED_WORK(&tp->task, task);
4087 schedule_delayed_work(&tp->task, 4);
4088 }
4089
4090 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4091 {
4092 struct rtl8169_private *tp = netdev_priv(dev);
4093 void __iomem *ioaddr = tp->mmio_addr;
4094
4095 synchronize_irq(dev->irq);
4096
4097 /* Wait for any pending NAPI task to complete */
4098 napi_disable(&tp->napi);
4099
4100 rtl8169_irq_mask_and_ack(ioaddr);
4101
4102 tp->intr_mask = 0xffff;
4103 RTL_W16(IntrMask, tp->intr_event);
4104 napi_enable(&tp->napi);
4105 }
4106
4107 static void rtl8169_reinit_task(struct work_struct *work)
4108 {
4109 struct rtl8169_private *tp =
4110 container_of(work, struct rtl8169_private, task.work);
4111 struct net_device *dev = tp->dev;
4112 int ret;
4113
4114 rtnl_lock();
4115
4116 if (!netif_running(dev))
4117 goto out_unlock;
4118
4119 rtl8169_wait_for_quiescence(dev);
4120 rtl8169_close(dev);
4121
4122 ret = rtl8169_open(dev);
4123 if (unlikely(ret < 0)) {
4124 if (net_ratelimit() && netif_msg_drv(tp)) {
4125 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
4126 " Rescheduling.\n", dev->name, ret);
4127 }
4128 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4129 }
4130
4131 out_unlock:
4132 rtnl_unlock();
4133 }
4134
4135 static void rtl8169_reset_task(struct work_struct *work)
4136 {
4137 struct rtl8169_private *tp =
4138 container_of(work, struct rtl8169_private, task.work);
4139 struct net_device *dev = tp->dev;
4140
4141 rtnl_lock();
4142
4143 if (!netif_running(dev))
4144 goto out_unlock;
4145
4146 rtl8169_wait_for_quiescence(dev);
4147
4148 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4149 rtl8169_tx_clear(tp);
4150
4151 if (tp->dirty_rx == tp->cur_rx) {
4152 rtl8169_init_ring_indexes(tp);
4153 rtl_hw_start(dev);
4154 netif_wake_queue(dev);
4155 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4156 } else {
4157 if (net_ratelimit() && netif_msg_intr(tp)) {
4158 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
4159 dev->name);
4160 }
4161 rtl8169_schedule_work(dev, rtl8169_reset_task);
4162 }
4163
4164 out_unlock:
4165 rtnl_unlock();
4166 }
4167
4168 static void rtl8169_tx_timeout(struct net_device *dev)
4169 {
4170 struct rtl8169_private *tp = netdev_priv(dev);
4171
4172 rtl8169_hw_reset(tp->mmio_addr);
4173
4174 /* Let's wait a bit while any (async) irq lands on */
4175 rtl8169_schedule_work(dev, rtl8169_reset_task);
4176 }
4177
4178 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4179 u32 opts1)
4180 {
4181 struct skb_shared_info *info = skb_shinfo(skb);
4182 unsigned int cur_frag, entry;
4183 struct TxDesc * uninitialized_var(txd);
4184
4185 entry = tp->cur_tx;
4186 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4187 skb_frag_t *frag = info->frags + cur_frag;
4188 dma_addr_t mapping;
4189 u32 status, len;
4190 void *addr;
4191
4192 entry = (entry + 1) % NUM_TX_DESC;
4193
4194 txd = tp->TxDescArray + entry;
4195 len = frag->size;
4196 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4197 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4198
4199 /* anti gcc 2.95.3 bugware (sic) */
4200 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4201
4202 txd->opts1 = cpu_to_le32(status);
4203 txd->addr = cpu_to_le64(mapping);
4204
4205 tp->tx_skb[entry].len = len;
4206 }
4207
4208 if (cur_frag) {
4209 tp->tx_skb[entry].skb = skb;
4210 txd->opts1 |= cpu_to_le32(LastFrag);
4211 }
4212
4213 return cur_frag;
4214 }
4215
4216 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4217 {
4218 if (dev->features & NETIF_F_TSO) {
4219 u32 mss = skb_shinfo(skb)->gso_size;
4220
4221 if (mss)
4222 return LargeSend | ((mss & MSSMask) << MSSShift);
4223 }
4224 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4225 const struct iphdr *ip = ip_hdr(skb);
4226
4227 if (ip->protocol == IPPROTO_TCP)
4228 return IPCS | TCPCS;
4229 else if (ip->protocol == IPPROTO_UDP)
4230 return IPCS | UDPCS;
4231 WARN_ON(1); /* we need a WARN() */
4232 }
4233 return 0;
4234 }
4235
4236 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4237 struct net_device *dev)
4238 {
4239 struct rtl8169_private *tp = netdev_priv(dev);
4240 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4241 struct TxDesc *txd = tp->TxDescArray + entry;
4242 void __iomem *ioaddr = tp->mmio_addr;
4243 dma_addr_t mapping;
4244 u32 status, len;
4245 u32 opts1;
4246
4247 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4248 if (netif_msg_drv(tp)) {
4249 printk(KERN_ERR
4250 "%s: BUG! Tx Ring full when queue awake!\n",
4251 dev->name);
4252 }
4253 goto err_stop;
4254 }
4255
4256 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4257 goto err_stop;
4258
4259 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4260
4261 frags = rtl8169_xmit_frags(tp, skb, opts1);
4262 if (frags) {
4263 len = skb_headlen(skb);
4264 opts1 |= FirstFrag;
4265 } else {
4266 len = skb->len;
4267 opts1 |= FirstFrag | LastFrag;
4268 tp->tx_skb[entry].skb = skb;
4269 }
4270
4271 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4272
4273 tp->tx_skb[entry].len = len;
4274 txd->addr = cpu_to_le64(mapping);
4275 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4276
4277 wmb();
4278
4279 /* anti gcc 2.95.3 bugware (sic) */
4280 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4281 txd->opts1 = cpu_to_le32(status);
4282
4283 tp->cur_tx += frags + 1;
4284
4285 smp_wmb();
4286
4287 RTL_W8(TxPoll, NPQ); /* set polling bit */
4288
4289 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4290 netif_stop_queue(dev);
4291 smp_rmb();
4292 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4293 netif_wake_queue(dev);
4294 }
4295
4296 return NETDEV_TX_OK;
4297
4298 err_stop:
4299 netif_stop_queue(dev);
4300 dev->stats.tx_dropped++;
4301 return NETDEV_TX_BUSY;
4302 }
4303
4304 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4305 {
4306 struct rtl8169_private *tp = netdev_priv(dev);
4307 struct pci_dev *pdev = tp->pci_dev;
4308 void __iomem *ioaddr = tp->mmio_addr;
4309 u16 pci_status, pci_cmd;
4310
4311 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4312 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4313
4314 if (netif_msg_intr(tp)) {
4315 printk(KERN_ERR
4316 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
4317 dev->name, pci_cmd, pci_status);
4318 }
4319
4320 /*
4321 * The recovery sequence below admits a very elaborated explanation:
4322 * - it seems to work;
4323 * - I did not see what else could be done;
4324 * - it makes iop3xx happy.
4325 *
4326 * Feel free to adjust to your needs.
4327 */
4328 if (pdev->broken_parity_status)
4329 pci_cmd &= ~PCI_COMMAND_PARITY;
4330 else
4331 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4332
4333 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4334
4335 pci_write_config_word(pdev, PCI_STATUS,
4336 pci_status & (PCI_STATUS_DETECTED_PARITY |
4337 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4338 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4339
4340 /* The infamous DAC f*ckup only happens at boot time */
4341 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4342 if (netif_msg_intr(tp))
4343 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
4344 tp->cp_cmd &= ~PCIDAC;
4345 RTL_W16(CPlusCmd, tp->cp_cmd);
4346 dev->features &= ~NETIF_F_HIGHDMA;
4347 }
4348
4349 rtl8169_hw_reset(ioaddr);
4350
4351 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4352 }
4353
4354 static void rtl8169_tx_interrupt(struct net_device *dev,
4355 struct rtl8169_private *tp,
4356 void __iomem *ioaddr)
4357 {
4358 unsigned int dirty_tx, tx_left;
4359
4360 dirty_tx = tp->dirty_tx;
4361 smp_rmb();
4362 tx_left = tp->cur_tx - dirty_tx;
4363
4364 while (tx_left > 0) {
4365 unsigned int entry = dirty_tx % NUM_TX_DESC;
4366 struct ring_info *tx_skb = tp->tx_skb + entry;
4367 u32 len = tx_skb->len;
4368 u32 status;
4369
4370 rmb();
4371 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4372 if (status & DescOwn)
4373 break;
4374
4375 dev->stats.tx_bytes += len;
4376 dev->stats.tx_packets++;
4377
4378 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4379
4380 if (status & LastFrag) {
4381 dev_kfree_skb(tx_skb->skb);
4382 tx_skb->skb = NULL;
4383 }
4384 dirty_tx++;
4385 tx_left--;
4386 }
4387
4388 if (tp->dirty_tx != dirty_tx) {
4389 tp->dirty_tx = dirty_tx;
4390 smp_wmb();
4391 if (netif_queue_stopped(dev) &&
4392 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4393 netif_wake_queue(dev);
4394 }
4395 /*
4396 * 8168 hack: TxPoll requests are lost when the Tx packets are
4397 * too close. Let's kick an extra TxPoll request when a burst
4398 * of start_xmit activity is detected (if it is not detected,
4399 * it is slow enough). -- FR
4400 */
4401 smp_rmb();
4402 if (tp->cur_tx != dirty_tx)
4403 RTL_W8(TxPoll, NPQ);
4404 }
4405 }
4406
4407 static inline int rtl8169_fragmented_frame(u32 status)
4408 {
4409 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4410 }
4411
4412 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4413 {
4414 u32 opts1 = le32_to_cpu(desc->opts1);
4415 u32 status = opts1 & RxProtoMask;
4416
4417 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4418 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4419 ((status == RxProtoIP) && !(opts1 & IPFail)))
4420 skb->ip_summed = CHECKSUM_UNNECESSARY;
4421 else
4422 skb->ip_summed = CHECKSUM_NONE;
4423 }
4424
4425 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4426 struct rtl8169_private *tp, int pkt_size,
4427 dma_addr_t addr)
4428 {
4429 struct sk_buff *skb;
4430 bool done = false;
4431
4432 if (pkt_size >= rx_copybreak)
4433 goto out;
4434
4435 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
4436 if (!skb)
4437 goto out;
4438
4439 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4440 PCI_DMA_FROMDEVICE);
4441 skb_reserve(skb, NET_IP_ALIGN);
4442 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4443 *sk_buff = skb;
4444 done = true;
4445 out:
4446 return done;
4447 }
4448
4449 static int rtl8169_rx_interrupt(struct net_device *dev,
4450 struct rtl8169_private *tp,
4451 void __iomem *ioaddr, u32 budget)
4452 {
4453 unsigned int cur_rx, rx_left;
4454 unsigned int delta, count;
4455
4456 cur_rx = tp->cur_rx;
4457 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4458 rx_left = min(rx_left, budget);
4459
4460 for (; rx_left > 0; rx_left--, cur_rx++) {
4461 unsigned int entry = cur_rx % NUM_RX_DESC;
4462 struct RxDesc *desc = tp->RxDescArray + entry;
4463 u32 status;
4464
4465 rmb();
4466 status = le32_to_cpu(desc->opts1);
4467
4468 if (status & DescOwn)
4469 break;
4470 if (unlikely(status & RxRES)) {
4471 if (netif_msg_rx_err(tp)) {
4472 printk(KERN_INFO
4473 "%s: Rx ERROR. status = %08x\n",
4474 dev->name, status);
4475 }
4476 dev->stats.rx_errors++;
4477 if (status & (RxRWT | RxRUNT))
4478 dev->stats.rx_length_errors++;
4479 if (status & RxCRC)
4480 dev->stats.rx_crc_errors++;
4481 if (status & RxFOVF) {
4482 rtl8169_schedule_work(dev, rtl8169_reset_task);
4483 dev->stats.rx_fifo_errors++;
4484 }
4485 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4486 } else {
4487 struct sk_buff *skb = tp->Rx_skbuff[entry];
4488 dma_addr_t addr = le64_to_cpu(desc->addr);
4489 int pkt_size = (status & 0x00001FFF) - 4;
4490 struct pci_dev *pdev = tp->pci_dev;
4491
4492 /*
4493 * The driver does not support incoming fragmented
4494 * frames. They are seen as a symptom of over-mtu
4495 * sized frames.
4496 */
4497 if (unlikely(rtl8169_fragmented_frame(status))) {
4498 dev->stats.rx_dropped++;
4499 dev->stats.rx_length_errors++;
4500 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4501 continue;
4502 }
4503
4504 rtl8169_rx_csum(skb, desc);
4505
4506 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4507 pci_dma_sync_single_for_device(pdev, addr,
4508 pkt_size, PCI_DMA_FROMDEVICE);
4509 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4510 } else {
4511 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4512 PCI_DMA_FROMDEVICE);
4513 tp->Rx_skbuff[entry] = NULL;
4514 }
4515
4516 skb_put(skb, pkt_size);
4517 skb->protocol = eth_type_trans(skb, dev);
4518
4519 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
4520 netif_receive_skb(skb);
4521
4522 dev->stats.rx_bytes += pkt_size;
4523 dev->stats.rx_packets++;
4524 }
4525
4526 /* Work around for AMD plateform. */
4527 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4528 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4529 desc->opts2 = 0;
4530 cur_rx++;
4531 }
4532 }
4533
4534 count = cur_rx - tp->cur_rx;
4535 tp->cur_rx = cur_rx;
4536
4537 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4538 if (!delta && count && netif_msg_intr(tp))
4539 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
4540 tp->dirty_rx += delta;
4541
4542 /*
4543 * FIXME: until there is periodic timer to try and refill the ring,
4544 * a temporary shortage may definitely kill the Rx process.
4545 * - disable the asic to try and avoid an overflow and kick it again
4546 * after refill ?
4547 * - how do others driver handle this condition (Uh oh...).
4548 */
4549 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
4550 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
4551
4552 return count;
4553 }
4554
4555 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4556 {
4557 struct net_device *dev = dev_instance;
4558 struct rtl8169_private *tp = netdev_priv(dev);
4559 void __iomem *ioaddr = tp->mmio_addr;
4560 int handled = 0;
4561 int status;
4562
4563 /* loop handling interrupts until we have no new ones or
4564 * we hit a invalid/hotplug case.
4565 */
4566 status = RTL_R16(IntrStatus);
4567 while (status && status != 0xffff) {
4568 handled = 1;
4569
4570 /* Handle all of the error cases first. These will reset
4571 * the chip, so just exit the loop.
4572 */
4573 if (unlikely(!netif_running(dev))) {
4574 rtl8169_asic_down(ioaddr);
4575 break;
4576 }
4577
4578 /* Work around for rx fifo overflow */
4579 if (unlikely(status & RxFIFOOver) &&
4580 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4581 netif_stop_queue(dev);
4582 rtl8169_tx_timeout(dev);
4583 break;
4584 }
4585
4586 if (unlikely(status & SYSErr)) {
4587 rtl8169_pcierr_interrupt(dev);
4588 break;
4589 }
4590
4591 if (status & LinkChg)
4592 rtl8169_check_link_status(dev, tp, ioaddr);
4593
4594 /* We need to see the lastest version of tp->intr_mask to
4595 * avoid ignoring an MSI interrupt and having to wait for
4596 * another event which may never come.
4597 */
4598 smp_rmb();
4599 if (status & tp->intr_mask & tp->napi_event) {
4600 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4601 tp->intr_mask = ~tp->napi_event;
4602
4603 if (likely(napi_schedule_prep(&tp->napi)))
4604 __napi_schedule(&tp->napi);
4605 else if (netif_msg_intr(tp)) {
4606 printk(KERN_INFO "%s: interrupt %04x in poll\n",
4607 dev->name, status);
4608 }
4609 }
4610
4611 /* We only get a new MSI interrupt when all active irq
4612 * sources on the chip have been acknowledged. So, ack
4613 * everything we've seen and check if new sources have become
4614 * active to avoid blocking all interrupts from the chip.
4615 */
4616 RTL_W16(IntrStatus,
4617 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4618 status = RTL_R16(IntrStatus);
4619 }
4620
4621 return IRQ_RETVAL(handled);
4622 }
4623
4624 static int rtl8169_poll(struct napi_struct *napi, int budget)
4625 {
4626 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4627 struct net_device *dev = tp->dev;
4628 void __iomem *ioaddr = tp->mmio_addr;
4629 int work_done;
4630
4631 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4632 rtl8169_tx_interrupt(dev, tp, ioaddr);
4633
4634 if (work_done < budget) {
4635 napi_complete(napi);
4636
4637 /* We need for force the visibility of tp->intr_mask
4638 * for other CPUs, as we can loose an MSI interrupt
4639 * and potentially wait for a retransmit timeout if we don't.
4640 * The posted write to IntrMask is safe, as it will
4641 * eventually make it to the chip and we won't loose anything
4642 * until it does.
4643 */
4644 tp->intr_mask = 0xffff;
4645 smp_wmb();
4646 RTL_W16(IntrMask, tp->intr_event);
4647 }
4648
4649 return work_done;
4650 }
4651
4652 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4653 {
4654 struct rtl8169_private *tp = netdev_priv(dev);
4655
4656 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4657 return;
4658
4659 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4660 RTL_W32(RxMissed, 0);
4661 }
4662
4663 static void rtl8169_down(struct net_device *dev)
4664 {
4665 struct rtl8169_private *tp = netdev_priv(dev);
4666 void __iomem *ioaddr = tp->mmio_addr;
4667 unsigned int intrmask;
4668
4669 rtl8169_delete_timer(dev);
4670
4671 netif_stop_queue(dev);
4672
4673 napi_disable(&tp->napi);
4674
4675 core_down:
4676 spin_lock_irq(&tp->lock);
4677
4678 rtl8169_asic_down(ioaddr);
4679
4680 rtl8169_rx_missed(dev, ioaddr);
4681
4682 spin_unlock_irq(&tp->lock);
4683
4684 synchronize_irq(dev->irq);
4685
4686 /* Give a racing hard_start_xmit a few cycles to complete. */
4687 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4688
4689 /*
4690 * And now for the 50k$ question: are IRQ disabled or not ?
4691 *
4692 * Two paths lead here:
4693 * 1) dev->close
4694 * -> netif_running() is available to sync the current code and the
4695 * IRQ handler. See rtl8169_interrupt for details.
4696 * 2) dev->change_mtu
4697 * -> rtl8169_poll can not be issued again and re-enable the
4698 * interruptions. Let's simply issue the IRQ down sequence again.
4699 *
4700 * No loop if hotpluged or major error (0xffff).
4701 */
4702 intrmask = RTL_R16(IntrMask);
4703 if (intrmask && (intrmask != 0xffff))
4704 goto core_down;
4705
4706 rtl8169_tx_clear(tp);
4707
4708 rtl8169_rx_clear(tp);
4709 }
4710
4711 static int rtl8169_close(struct net_device *dev)
4712 {
4713 struct rtl8169_private *tp = netdev_priv(dev);
4714 struct pci_dev *pdev = tp->pci_dev;
4715
4716 /* update counters before going down */
4717 rtl8169_update_counters(dev);
4718
4719 rtl8169_down(dev);
4720
4721 free_irq(dev->irq, dev);
4722
4723 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4724 tp->RxPhyAddr);
4725 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4726 tp->TxPhyAddr);
4727 tp->TxDescArray = NULL;
4728 tp->RxDescArray = NULL;
4729
4730 return 0;
4731 }
4732
4733 static void rtl_set_rx_mode(struct net_device *dev)
4734 {
4735 struct rtl8169_private *tp = netdev_priv(dev);
4736 void __iomem *ioaddr = tp->mmio_addr;
4737 unsigned long flags;
4738 u32 mc_filter[2]; /* Multicast hash filter */
4739 int rx_mode;
4740 u32 tmp = 0;
4741
4742 if (dev->flags & IFF_PROMISC) {
4743 /* Unconditionally log net taps. */
4744 if (netif_msg_link(tp)) {
4745 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
4746 dev->name);
4747 }
4748 rx_mode =
4749 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4750 AcceptAllPhys;
4751 mc_filter[1] = mc_filter[0] = 0xffffffff;
4752 } else if ((dev->mc_count > multicast_filter_limit)
4753 || (dev->flags & IFF_ALLMULTI)) {
4754 /* Too many to filter perfectly -- accept all multicasts. */
4755 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4756 mc_filter[1] = mc_filter[0] = 0xffffffff;
4757 } else {
4758 struct dev_mc_list *mclist;
4759 unsigned int i;
4760
4761 rx_mode = AcceptBroadcast | AcceptMyPhys;
4762 mc_filter[1] = mc_filter[0] = 0;
4763 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
4764 i++, mclist = mclist->next) {
4765 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4766 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4767 rx_mode |= AcceptMulticast;
4768 }
4769 }
4770
4771 spin_lock_irqsave(&tp->lock, flags);
4772
4773 tmp = rtl8169_rx_config | rx_mode |
4774 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4775
4776 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4777 u32 data = mc_filter[0];
4778
4779 mc_filter[0] = swab32(mc_filter[1]);
4780 mc_filter[1] = swab32(data);
4781 }
4782
4783 RTL_W32(MAR0 + 0, mc_filter[0]);
4784 RTL_W32(MAR0 + 4, mc_filter[1]);
4785
4786 RTL_W32(RxConfig, tmp);
4787
4788 spin_unlock_irqrestore(&tp->lock, flags);
4789 }
4790
4791 /**
4792 * rtl8169_get_stats - Get rtl8169 read/write statistics
4793 * @dev: The Ethernet Device to get statistics for
4794 *
4795 * Get TX/RX statistics for rtl8169
4796 */
4797 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4798 {
4799 struct rtl8169_private *tp = netdev_priv(dev);
4800 void __iomem *ioaddr = tp->mmio_addr;
4801 unsigned long flags;
4802
4803 if (netif_running(dev)) {
4804 spin_lock_irqsave(&tp->lock, flags);
4805 rtl8169_rx_missed(dev, ioaddr);
4806 spin_unlock_irqrestore(&tp->lock, flags);
4807 }
4808
4809 return &dev->stats;
4810 }
4811
4812 static void rtl8169_net_suspend(struct net_device *dev)
4813 {
4814 if (!netif_running(dev))
4815 return;
4816
4817 netif_device_detach(dev);
4818 netif_stop_queue(dev);
4819 }
4820
4821 #ifdef CONFIG_PM
4822
4823 static int rtl8169_suspend(struct device *device)
4824 {
4825 struct pci_dev *pdev = to_pci_dev(device);
4826 struct net_device *dev = pci_get_drvdata(pdev);
4827
4828 rtl8169_net_suspend(dev);
4829
4830 return 0;
4831 }
4832
4833 static int rtl8169_resume(struct device *device)
4834 {
4835 struct pci_dev *pdev = to_pci_dev(device);
4836 struct net_device *dev = pci_get_drvdata(pdev);
4837
4838 if (!netif_running(dev))
4839 goto out;
4840
4841 netif_device_attach(dev);
4842
4843 rtl8169_schedule_work(dev, rtl8169_reset_task);
4844 out:
4845 return 0;
4846 }
4847
4848 static struct dev_pm_ops rtl8169_pm_ops = {
4849 .suspend = rtl8169_suspend,
4850 .resume = rtl8169_resume,
4851 .freeze = rtl8169_suspend,
4852 .thaw = rtl8169_resume,
4853 .poweroff = rtl8169_suspend,
4854 .restore = rtl8169_resume,
4855 };
4856
4857 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4858
4859 #else /* !CONFIG_PM */
4860
4861 #define RTL8169_PM_OPS NULL
4862
4863 #endif /* !CONFIG_PM */
4864
4865 static void rtl_shutdown(struct pci_dev *pdev)
4866 {
4867 struct net_device *dev = pci_get_drvdata(pdev);
4868 struct rtl8169_private *tp = netdev_priv(dev);
4869 void __iomem *ioaddr = tp->mmio_addr;
4870
4871 rtl8169_net_suspend(dev);
4872
4873 spin_lock_irq(&tp->lock);
4874
4875 rtl8169_asic_down(ioaddr);
4876
4877 spin_unlock_irq(&tp->lock);
4878
4879 if (system_state == SYSTEM_POWER_OFF) {
4880 /* WoL fails with some 8168 when the receiver is disabled. */
4881 if (tp->features & RTL_FEATURE_WOL) {
4882 pci_clear_master(pdev);
4883
4884 RTL_W8(ChipCmd, CmdRxEnb);
4885 /* PCI commit */
4886 RTL_R8(ChipCmd);
4887 }
4888
4889 pci_wake_from_d3(pdev, true);
4890 pci_set_power_state(pdev, PCI_D3hot);
4891 }
4892 }
4893
4894 static struct pci_driver rtl8169_pci_driver = {
4895 .name = MODULENAME,
4896 .id_table = rtl8169_pci_tbl,
4897 .probe = rtl8169_init_one,
4898 .remove = __devexit_p(rtl8169_remove_one),
4899 .shutdown = rtl_shutdown,
4900 .driver.pm = RTL8169_PM_OPS,
4901 };
4902
4903 static int __init rtl8169_init_module(void)
4904 {
4905 return pci_register_driver(&rtl8169_pci_driver);
4906 }
4907
4908 static void __exit rtl8169_cleanup_module(void)
4909 {
4910 pci_unregister_driver(&rtl8169_pci_driver);
4911 }
4912
4913 module_init(rtl8169_init_module);
4914 module_exit(rtl8169_cleanup_module);
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