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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / sh_eth.c
blobf49d0800c1d103c70bdb37f59cba9f00047b5285
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
32 #include <linux/io.h>
33
34 #include "sh_eth.h"
35
36 /* There is CPU dependent code */
37 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
38 #define SH_ETH_RESET_DEFAULT 1
39 static void sh_eth_set_duplex(struct net_device *ndev)
40 {
41 struct sh_eth_private *mdp = netdev_priv(ndev);
42 u32 ioaddr = ndev->base_addr;
43
44 if (mdp->duplex) /* Full */
45 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
46 else /* Half */
47 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
48 }
49
50 static void sh_eth_set_rate(struct net_device *ndev)
51 {
52 struct sh_eth_private *mdp = netdev_priv(ndev);
53 u32 ioaddr = ndev->base_addr;
54
55 switch (mdp->speed) {
56 case 10: /* 10BASE */
57 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
58 break;
59 case 100:/* 100BASE */
60 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
61 break;
62 default:
63 break;
64 }
65 }
66
67 /* SH7724 */
68 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
69 .set_duplex = sh_eth_set_duplex,
70 .set_rate = sh_eth_set_rate,
71
72 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
73 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
74 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
75
76 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
77 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
78 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
79 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
80
81 .apr = 1,
82 .mpr = 1,
83 .tpauser = 1,
84 .hw_swap = 1,
85 };
86
87 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
88 #define SH_ETH_HAS_TSU 1
89 static void sh_eth_chip_reset(struct net_device *ndev)
90 {
91 /* reset device */
92 ctrl_outl(ARSTR_ARSTR, ARSTR);
93 mdelay(1);
94 }
95
96 static void sh_eth_reset(struct net_device *ndev)
97 {
98 u32 ioaddr = ndev->base_addr;
99 int cnt = 100;
100
101 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
102 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
103 while (cnt > 0) {
104 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
105 break;
106 mdelay(1);
107 cnt--;
108 }
109 if (cnt < 0)
110 printk(KERN_ERR "Device reset fail\n");
111
112 /* Table Init */
113 ctrl_outl(0x0, ioaddr + TDLAR);
114 ctrl_outl(0x0, ioaddr + TDFAR);
115 ctrl_outl(0x0, ioaddr + TDFXR);
116 ctrl_outl(0x0, ioaddr + TDFFR);
117 ctrl_outl(0x0, ioaddr + RDLAR);
118 ctrl_outl(0x0, ioaddr + RDFAR);
119 ctrl_outl(0x0, ioaddr + RDFXR);
120 ctrl_outl(0x0, ioaddr + RDFFR);
121 }
122
123 static void sh_eth_set_duplex(struct net_device *ndev)
124 {
125 struct sh_eth_private *mdp = netdev_priv(ndev);
126 u32 ioaddr = ndev->base_addr;
127
128 if (mdp->duplex) /* Full */
129 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
130 else /* Half */
131 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
132 }
133
134 static void sh_eth_set_rate(struct net_device *ndev)
135 {
136 struct sh_eth_private *mdp = netdev_priv(ndev);
137 u32 ioaddr = ndev->base_addr;
138
139 switch (mdp->speed) {
140 case 10: /* 10BASE */
141 ctrl_outl(GECMR_10, ioaddr + GECMR);
142 break;
143 case 100:/* 100BASE */
144 ctrl_outl(GECMR_100, ioaddr + GECMR);
145 break;
146 case 1000: /* 1000BASE */
147 ctrl_outl(GECMR_1000, ioaddr + GECMR);
148 break;
149 default:
150 break;
151 }
152 }
153
154 /* sh7763 */
155 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
156 .chip_reset = sh_eth_chip_reset,
157 .set_duplex = sh_eth_set_duplex,
158 .set_rate = sh_eth_set_rate,
159
160 .ecsr_value = ECSR_ICD | ECSR_MPD,
161 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
162 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
163
164 .tx_check = EESR_TC1 | EESR_FTC,
165 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
166 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
167 EESR_ECI,
168 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
169 EESR_TFE,
170
171 .apr = 1,
172 .mpr = 1,
173 .tpauser = 1,
174 .bculr = 1,
175 .hw_swap = 1,
176 .rpadir = 1,
177 .no_trimd = 1,
178 .no_ade = 1,
179 };
180
181 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
182 #define SH_ETH_RESET_DEFAULT 1
183 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
184 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
185
186 .apr = 1,
187 .mpr = 1,
188 .tpauser = 1,
189 .hw_swap = 1,
190 };
191 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
192 #define SH_ETH_RESET_DEFAULT 1
193 #define SH_ETH_HAS_TSU 1
194 static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
195 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
196 };
197 #endif
198
199 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
200 {
201 if (!cd->ecsr_value)
202 cd->ecsr_value = DEFAULT_ECSR_INIT;
203
204 if (!cd->ecsipr_value)
205 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
206
207 if (!cd->fcftr_value)
208 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
209 DEFAULT_FIFO_F_D_RFD;
210
211 if (!cd->fdr_value)
212 cd->fdr_value = DEFAULT_FDR_INIT;
213
214 if (!cd->rmcr_value)
215 cd->rmcr_value = DEFAULT_RMCR_VALUE;
216
217 if (!cd->tx_check)
218 cd->tx_check = DEFAULT_TX_CHECK;
219
220 if (!cd->eesr_err_check)
221 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
222
223 if (!cd->tx_error_check)
224 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
225 }
226
227 #if defined(SH_ETH_RESET_DEFAULT)
228 /* Chip Reset */
229 static void sh_eth_reset(struct net_device *ndev)
230 {
231 u32 ioaddr = ndev->base_addr;
232
233 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
234 mdelay(3);
235 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
236 }
237 #endif
238
239 #if defined(CONFIG_CPU_SH4)
240 static void sh_eth_set_receive_align(struct sk_buff *skb)
241 {
242 int reserve;
243
244 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
245 if (reserve)
246 skb_reserve(skb, reserve);
247 }
248 #else
249 static void sh_eth_set_receive_align(struct sk_buff *skb)
250 {
251 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
252 }
253 #endif
254
255
256 /* CPU <-> EDMAC endian convert */
257 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
258 {
259 switch (mdp->edmac_endian) {
260 case EDMAC_LITTLE_ENDIAN:
261 return cpu_to_le32(x);
262 case EDMAC_BIG_ENDIAN:
263 return cpu_to_be32(x);
264 }
265 return x;
266 }
267
268 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
269 {
270 switch (mdp->edmac_endian) {
271 case EDMAC_LITTLE_ENDIAN:
272 return le32_to_cpu(x);
273 case EDMAC_BIG_ENDIAN:
274 return be32_to_cpu(x);
275 }
276 return x;
277 }
278
279 /*
280 * Program the hardware MAC address from dev->dev_addr.
281 */
282 static void update_mac_address(struct net_device *ndev)
283 {
284 u32 ioaddr = ndev->base_addr;
285
286 ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
287 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
288 ioaddr + MAHR);
289 ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
290 ioaddr + MALR);
291 }
292
293 /*
294 * Get MAC address from SuperH MAC address register
295 *
296 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
297 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
298 * When you want use this device, you must set MAC address in bootloader.
299 *
300 */
301 static void read_mac_address(struct net_device *ndev)
302 {
303 u32 ioaddr = ndev->base_addr;
304
305 ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
306 ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
307 ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
308 ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
309 ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
310 ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
311 }
312
313 struct bb_info {
314 struct mdiobb_ctrl ctrl;
315 u32 addr;
316 u32 mmd_msk;/* MMD */
317 u32 mdo_msk;
318 u32 mdi_msk;
319 u32 mdc_msk;
320 };
321
322 /* PHY bit set */
323 static void bb_set(u32 addr, u32 msk)
324 {
325 ctrl_outl(ctrl_inl(addr) | msk, addr);
326 }
327
328 /* PHY bit clear */
329 static void bb_clr(u32 addr, u32 msk)
330 {
331 ctrl_outl((ctrl_inl(addr) & ~msk), addr);
332 }
333
334 /* PHY bit read */
335 static int bb_read(u32 addr, u32 msk)
336 {
337 return (ctrl_inl(addr) & msk) != 0;
338 }
339
340 /* Data I/O pin control */
341 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
342 {
343 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
344 if (bit)
345 bb_set(bitbang->addr, bitbang->mmd_msk);
346 else
347 bb_clr(bitbang->addr, bitbang->mmd_msk);
348 }
349
350 /* Set bit data*/
351 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
352 {
353 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
354
355 if (bit)
356 bb_set(bitbang->addr, bitbang->mdo_msk);
357 else
358 bb_clr(bitbang->addr, bitbang->mdo_msk);
359 }
360
361 /* Get bit data*/
362 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
363 {
364 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
365 return bb_read(bitbang->addr, bitbang->mdi_msk);
366 }
367
368 /* MDC pin control */
369 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
370 {
371 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
372
373 if (bit)
374 bb_set(bitbang->addr, bitbang->mdc_msk);
375 else
376 bb_clr(bitbang->addr, bitbang->mdc_msk);
377 }
378
379 /* mdio bus control struct */
380 static struct mdiobb_ops bb_ops = {
381 .owner = THIS_MODULE,
382 .set_mdc = sh_mdc_ctrl,
383 .set_mdio_dir = sh_mmd_ctrl,
384 .set_mdio_data = sh_set_mdio,
385 .get_mdio_data = sh_get_mdio,
386 };
387
388 /* free skb and descriptor buffer */
389 static void sh_eth_ring_free(struct net_device *ndev)
390 {
391 struct sh_eth_private *mdp = netdev_priv(ndev);
392 int i;
393
394 /* Free Rx skb ringbuffer */
395 if (mdp->rx_skbuff) {
396 for (i = 0; i < RX_RING_SIZE; i++) {
397 if (mdp->rx_skbuff[i])
398 dev_kfree_skb(mdp->rx_skbuff[i]);
399 }
400 }
401 kfree(mdp->rx_skbuff);
402
403 /* Free Tx skb ringbuffer */
404 if (mdp->tx_skbuff) {
405 for (i = 0; i < TX_RING_SIZE; i++) {
406 if (mdp->tx_skbuff[i])
407 dev_kfree_skb(mdp->tx_skbuff[i]);
408 }
409 }
410 kfree(mdp->tx_skbuff);
411 }
412
413 /* format skb and descriptor buffer */
414 static void sh_eth_ring_format(struct net_device *ndev)
415 {
416 u32 ioaddr = ndev->base_addr;
417 struct sh_eth_private *mdp = netdev_priv(ndev);
418 int i;
419 struct sk_buff *skb;
420 struct sh_eth_rxdesc *rxdesc = NULL;
421 struct sh_eth_txdesc *txdesc = NULL;
422 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
423 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
424
425 mdp->cur_rx = mdp->cur_tx = 0;
426 mdp->dirty_rx = mdp->dirty_tx = 0;
427
428 memset(mdp->rx_ring, 0, rx_ringsize);
429
430 /* build Rx ring buffer */
431 for (i = 0; i < RX_RING_SIZE; i++) {
432 /* skb */
433 mdp->rx_skbuff[i] = NULL;
434 skb = dev_alloc_skb(mdp->rx_buf_sz);
435 mdp->rx_skbuff[i] = skb;
436 if (skb == NULL)
437 break;
438 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
439 DMA_FROM_DEVICE);
440 skb->dev = ndev; /* Mark as being used by this device. */
441 sh_eth_set_receive_align(skb);
442
443 /* RX descriptor */
444 rxdesc = &mdp->rx_ring[i];
445 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
446 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
447
448 /* The size of the buffer is 16 byte boundary. */
449 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
450 /* Rx descriptor address set */
451 if (i == 0) {
452 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR);
453 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
454 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR);
455 #endif
456 }
457 }
458
459 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
460
461 /* Mark the last entry as wrapping the ring. */
462 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
463
464 memset(mdp->tx_ring, 0, tx_ringsize);
465
466 /* build Tx ring buffer */
467 for (i = 0; i < TX_RING_SIZE; i++) {
468 mdp->tx_skbuff[i] = NULL;
469 txdesc = &mdp->tx_ring[i];
470 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
471 txdesc->buffer_length = 0;
472 if (i == 0) {
473 /* Tx descriptor address set */
474 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR);
475 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
476 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR);
477 #endif
478 }
479 }
480
481 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
482 }
483
484 /* Get skb and descriptor buffer */
485 static int sh_eth_ring_init(struct net_device *ndev)
486 {
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488 int rx_ringsize, tx_ringsize, ret = 0;
489
490 /*
491 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
492 * card needs room to do 8 byte alignment, +2 so we can reserve
493 * the first 2 bytes, and +16 gets room for the status word from the
494 * card.
495 */
496 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
497 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
498
499 /* Allocate RX and TX skb rings */
500 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
501 GFP_KERNEL);
502 if (!mdp->rx_skbuff) {
503 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
504 ret = -ENOMEM;
505 return ret;
506 }
507
508 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
509 GFP_KERNEL);
510 if (!mdp->tx_skbuff) {
511 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
512 ret = -ENOMEM;
513 goto skb_ring_free;
514 }
515
516 /* Allocate all Rx descriptors. */
517 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
518 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
519 GFP_KERNEL);
520
521 if (!mdp->rx_ring) {
522 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
523 rx_ringsize);
524 ret = -ENOMEM;
525 goto desc_ring_free;
526 }
527
528 mdp->dirty_rx = 0;
529
530 /* Allocate all Tx descriptors. */
531 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
532 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
533 GFP_KERNEL);
534 if (!mdp->tx_ring) {
535 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
536 tx_ringsize);
537 ret = -ENOMEM;
538 goto desc_ring_free;
539 }
540 return ret;
541
542 desc_ring_free:
543 /* free DMA buffer */
544 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
545
546 skb_ring_free:
547 /* Free Rx and Tx skb ring buffer */
548 sh_eth_ring_free(ndev);
549
550 return ret;
551 }
552
553 static int sh_eth_dev_init(struct net_device *ndev)
554 {
555 int ret = 0;
556 struct sh_eth_private *mdp = netdev_priv(ndev);
557 u32 ioaddr = ndev->base_addr;
558 u_int32_t rx_int_var, tx_int_var;
559 u32 val;
560
561 /* Soft Reset */
562 sh_eth_reset(ndev);
563
564 /* Descriptor format */
565 sh_eth_ring_format(ndev);
566 if (mdp->cd->rpadir)
567 ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
568
569 /* all sh_eth int mask */
570 ctrl_outl(0, ioaddr + EESIPR);
571
572 #if defined(__LITTLE_ENDIAN__)
573 if (mdp->cd->hw_swap)
574 ctrl_outl(EDMR_EL, ioaddr + EDMR);
575 else
576 #endif
577 ctrl_outl(0, ioaddr + EDMR);
578
579 /* FIFO size set */
580 ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
581 ctrl_outl(0, ioaddr + TFTR);
582
583 /* Frame recv control */
584 ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
585
586 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
587 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
588 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
589
590 if (mdp->cd->bculr)
591 ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */
592
593 ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
594
595 if (!mdp->cd->no_trimd)
596 ctrl_outl(0, ioaddr + TRIMD);
597
598 /* Recv frame limit set register */
599 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
600
601 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
602 ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
603
604 /* PAUSE Prohibition */
605 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
606 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
607
608 ctrl_outl(val, ioaddr + ECMR);
609
610 if (mdp->cd->set_rate)
611 mdp->cd->set_rate(ndev);
612
613 /* E-MAC Status Register clear */
614 ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
615
616 /* E-MAC Interrupt Enable register */
617 ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
618
619 /* Set MAC address */
620 update_mac_address(ndev);
621
622 /* mask reset */
623 if (mdp->cd->apr)
624 ctrl_outl(APR_AP, ioaddr + APR);
625 if (mdp->cd->mpr)
626 ctrl_outl(MPR_MP, ioaddr + MPR);
627 if (mdp->cd->tpauser)
628 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
629
630 /* Setting the Rx mode will start the Rx process. */
631 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
632
633 netif_start_queue(ndev);
634
635 return ret;
636 }
637
638 /* free Tx skb function */
639 static int sh_eth_txfree(struct net_device *ndev)
640 {
641 struct sh_eth_private *mdp = netdev_priv(ndev);
642 struct sh_eth_txdesc *txdesc;
643 int freeNum = 0;
644 int entry = 0;
645
646 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
647 entry = mdp->dirty_tx % TX_RING_SIZE;
648 txdesc = &mdp->tx_ring[entry];
649 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
650 break;
651 /* Free the original skb. */
652 if (mdp->tx_skbuff[entry]) {
653 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
654 mdp->tx_skbuff[entry] = NULL;
655 freeNum++;
656 }
657 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
658 if (entry >= TX_RING_SIZE - 1)
659 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
660
661 mdp->stats.tx_packets++;
662 mdp->stats.tx_bytes += txdesc->buffer_length;
663 }
664 return freeNum;
665 }
666
667 /* Packet receive function */
668 static int sh_eth_rx(struct net_device *ndev)
669 {
670 struct sh_eth_private *mdp = netdev_priv(ndev);
671 struct sh_eth_rxdesc *rxdesc;
672
673 int entry = mdp->cur_rx % RX_RING_SIZE;
674 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
675 struct sk_buff *skb;
676 u16 pkt_len = 0;
677 u32 desc_status;
678
679 rxdesc = &mdp->rx_ring[entry];
680 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
681 desc_status = edmac_to_cpu(mdp, rxdesc->status);
682 pkt_len = rxdesc->frame_length;
683
684 if (--boguscnt < 0)
685 break;
686
687 if (!(desc_status & RDFEND))
688 mdp->stats.rx_length_errors++;
689
690 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
691 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
692 mdp->stats.rx_errors++;
693 if (desc_status & RD_RFS1)
694 mdp->stats.rx_crc_errors++;
695 if (desc_status & RD_RFS2)
696 mdp->stats.rx_frame_errors++;
697 if (desc_status & RD_RFS3)
698 mdp->stats.rx_length_errors++;
699 if (desc_status & RD_RFS4)
700 mdp->stats.rx_length_errors++;
701 if (desc_status & RD_RFS6)
702 mdp->stats.rx_missed_errors++;
703 if (desc_status & RD_RFS10)
704 mdp->stats.rx_over_errors++;
705 } else {
706 if (!mdp->cd->hw_swap)
707 sh_eth_soft_swap(
708 phys_to_virt(ALIGN(rxdesc->addr, 4)),
709 pkt_len + 2);
710 skb = mdp->rx_skbuff[entry];
711 mdp->rx_skbuff[entry] = NULL;
712 skb_put(skb, pkt_len);
713 skb->protocol = eth_type_trans(skb, ndev);
714 netif_rx(skb);
715 mdp->stats.rx_packets++;
716 mdp->stats.rx_bytes += pkt_len;
717 }
718 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
719 entry = (++mdp->cur_rx) % RX_RING_SIZE;
720 rxdesc = &mdp->rx_ring[entry];
721 }
722
723 /* Refill the Rx ring buffers. */
724 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
725 entry = mdp->dirty_rx % RX_RING_SIZE;
726 rxdesc = &mdp->rx_ring[entry];
727 /* The size of the buffer is 16 byte boundary. */
728 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
729
730 if (mdp->rx_skbuff[entry] == NULL) {
731 skb = dev_alloc_skb(mdp->rx_buf_sz);
732 mdp->rx_skbuff[entry] = skb;
733 if (skb == NULL)
734 break; /* Better luck next round. */
735 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
736 DMA_FROM_DEVICE);
737 skb->dev = ndev;
738 sh_eth_set_receive_align(skb);
739
740 skb->ip_summed = CHECKSUM_NONE;
741 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
742 }
743 if (entry >= RX_RING_SIZE - 1)
744 rxdesc->status |=
745 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
746 else
747 rxdesc->status |=
748 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
749 }
750
751 /* Restart Rx engine if stopped. */
752 /* If we don't need to check status, don't. -KDU */
753 if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
754 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
755
756 return 0;
757 }
758
759 /* error control function */
760 static void sh_eth_error(struct net_device *ndev, int intr_status)
761 {
762 struct sh_eth_private *mdp = netdev_priv(ndev);
763 u32 ioaddr = ndev->base_addr;
764 u32 felic_stat;
765 u32 link_stat;
766 u32 mask;
767
768 if (intr_status & EESR_ECI) {
769 felic_stat = ctrl_inl(ioaddr + ECSR);
770 ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
771 if (felic_stat & ECSR_ICD)
772 mdp->stats.tx_carrier_errors++;
773 if (felic_stat & ECSR_LCHNG) {
774 /* Link Changed */
775 if (mdp->cd->no_psr || mdp->no_ether_link) {
776 if (mdp->link == PHY_DOWN)
777 link_stat = 0;
778 else
779 link_stat = PHY_ST_LINK;
780 } else {
781 link_stat = (ctrl_inl(ioaddr + PSR));
782 if (mdp->ether_link_active_low)
783 link_stat = ~link_stat;
784 }
785 if (!(link_stat & PHY_ST_LINK)) {
786 /* Link Down : disable tx and rx */
787 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
788 ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
789 } else {
790 /* Link Up */
791 ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
792 ~DMAC_M_ECI, ioaddr + EESIPR);
793 /*clear int */
794 ctrl_outl(ctrl_inl(ioaddr + ECSR),
795 ioaddr + ECSR);
796 ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
797 DMAC_M_ECI, ioaddr + EESIPR);
798 /* enable tx and rx */
799 ctrl_outl(ctrl_inl(ioaddr + ECMR) |
800 (ECMR_RE | ECMR_TE), ioaddr + ECMR);
801 }
802 }
803 }
804
805 if (intr_status & EESR_TWB) {
806 /* Write buck end. unused write back interrupt */
807 if (intr_status & EESR_TABT) /* Transmit Abort int */
808 mdp->stats.tx_aborted_errors++;
809 }
810
811 if (intr_status & EESR_RABT) {
812 /* Receive Abort int */
813 if (intr_status & EESR_RFRMER) {
814 /* Receive Frame Overflow int */
815 mdp->stats.rx_frame_errors++;
816 dev_err(&ndev->dev, "Receive Frame Overflow\n");
817 }
818 }
819
820 if (!mdp->cd->no_ade) {
821 if (intr_status & EESR_ADE && intr_status & EESR_TDE &&
822 intr_status & EESR_TFE)
823 mdp->stats.tx_fifo_errors++;
824 }
825
826 if (intr_status & EESR_RDE) {
827 /* Receive Descriptor Empty int */
828 mdp->stats.rx_over_errors++;
829
830 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
831 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
832 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
833 }
834 if (intr_status & EESR_RFE) {
835 /* Receive FIFO Overflow int */
836 mdp->stats.rx_fifo_errors++;
837 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
838 }
839
840 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
841 if (mdp->cd->no_ade)
842 mask &= ~EESR_ADE;
843 if (intr_status & mask) {
844 /* Tx error */
845 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
846 /* dmesg */
847 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
848 intr_status, mdp->cur_tx);
849 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
850 mdp->dirty_tx, (u32) ndev->state, edtrr);
851 /* dirty buffer free */
852 sh_eth_txfree(ndev);
853
854 /* SH7712 BUG */
855 if (edtrr ^ EDTRR_TRNS) {
856 /* tx dma start */
857 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
858 }
859 /* wakeup */
860 netif_wake_queue(ndev);
861 }
862 }
863
864 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
865 {
866 struct net_device *ndev = netdev;
867 struct sh_eth_private *mdp = netdev_priv(ndev);
868 struct sh_eth_cpu_data *cd = mdp->cd;
869 irqreturn_t ret = IRQ_NONE;
870 u32 ioaddr, intr_status = 0;
871
872 ioaddr = ndev->base_addr;
873 spin_lock(&mdp->lock);
874
875 /* Get interrpt stat */
876 intr_status = ctrl_inl(ioaddr + EESR);
877 /* Clear interrupt */
878 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
879 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
880 cd->tx_check | cd->eesr_err_check)) {
881 ctrl_outl(intr_status, ioaddr + EESR);
882 ret = IRQ_HANDLED;
883 } else
884 goto other_irq;
885
886 if (intr_status & (EESR_FRC | /* Frame recv*/
887 EESR_RMAF | /* Multi cast address recv*/
888 EESR_RRF | /* Bit frame recv */
889 EESR_RTLF | /* Long frame recv*/
890 EESR_RTSF | /* short frame recv */
891 EESR_PRE | /* PHY-LSI recv error */
892 EESR_CERF)){ /* recv frame CRC error */
893 sh_eth_rx(ndev);
894 }
895
896 /* Tx Check */
897 if (intr_status & cd->tx_check) {
898 sh_eth_txfree(ndev);
899 netif_wake_queue(ndev);
900 }
901
902 if (intr_status & cd->eesr_err_check)
903 sh_eth_error(ndev, intr_status);
904
905 other_irq:
906 spin_unlock(&mdp->lock);
907
908 return ret;
909 }
910
911 static void sh_eth_timer(unsigned long data)
912 {
913 struct net_device *ndev = (struct net_device *)data;
914 struct sh_eth_private *mdp = netdev_priv(ndev);
915
916 mod_timer(&mdp->timer, jiffies + (10 * HZ));
917 }
918
919 /* PHY state control function */
920 static void sh_eth_adjust_link(struct net_device *ndev)
921 {
922 struct sh_eth_private *mdp = netdev_priv(ndev);
923 struct phy_device *phydev = mdp->phydev;
924 u32 ioaddr = ndev->base_addr;
925 int new_state = 0;
926
927 if (phydev->link != PHY_DOWN) {
928 if (phydev->duplex != mdp->duplex) {
929 new_state = 1;
930 mdp->duplex = phydev->duplex;
931 if (mdp->cd->set_duplex)
932 mdp->cd->set_duplex(ndev);
933 }
934
935 if (phydev->speed != mdp->speed) {
936 new_state = 1;
937 mdp->speed = phydev->speed;
938 if (mdp->cd->set_rate)
939 mdp->cd->set_rate(ndev);
940 }
941 if (mdp->link == PHY_DOWN) {
942 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
943 | ECMR_DM, ioaddr + ECMR);
944 new_state = 1;
945 mdp->link = phydev->link;
946 }
947 } else if (mdp->link) {
948 new_state = 1;
949 mdp->link = PHY_DOWN;
950 mdp->speed = 0;
951 mdp->duplex = -1;
952 }
953
954 if (new_state)
955 phy_print_status(phydev);
956 }
957
958 /* PHY init function */
959 static int sh_eth_phy_init(struct net_device *ndev)
960 {
961 struct sh_eth_private *mdp = netdev_priv(ndev);
962 char phy_id[MII_BUS_ID_SIZE + 3];
963 struct phy_device *phydev = NULL;
964
965 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
966 mdp->mii_bus->id , mdp->phy_id);
967
968 mdp->link = PHY_DOWN;
969 mdp->speed = 0;
970 mdp->duplex = -1;
971
972 /* Try connect to PHY */
973 phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link,
974 0, PHY_INTERFACE_MODE_MII);
975 if (IS_ERR(phydev)) {
976 dev_err(&ndev->dev, "phy_connect failed\n");
977 return PTR_ERR(phydev);
978 }
979
980 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
981 phydev->addr, phydev->drv->name);
982
983 mdp->phydev = phydev;
984
985 return 0;
986 }
987
988 /* PHY control start function */
989 static int sh_eth_phy_start(struct net_device *ndev)
990 {
991 struct sh_eth_private *mdp = netdev_priv(ndev);
992 int ret;
993
994 ret = sh_eth_phy_init(ndev);
995 if (ret)
996 return ret;
997
998 /* reset phy - this also wakes it from PDOWN */
999 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1000 phy_start(mdp->phydev);
1001
1002 return 0;
1003 }
1004
1005 /* network device open function */
1006 static int sh_eth_open(struct net_device *ndev)
1007 {
1008 int ret = 0;
1009 struct sh_eth_private *mdp = netdev_priv(ndev);
1010
1011 ret = request_irq(ndev->irq, &sh_eth_interrupt,
1012 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764)
1013 IRQF_SHARED,
1014 #else
1015 0,
1016 #endif
1017 ndev->name, ndev);
1018 if (ret) {
1019 dev_err(&ndev->dev, "Can not assign IRQ number\n");
1020 return ret;
1021 }
1022
1023 /* Descriptor set */
1024 ret = sh_eth_ring_init(ndev);
1025 if (ret)
1026 goto out_free_irq;
1027
1028 /* device init */
1029 ret = sh_eth_dev_init(ndev);
1030 if (ret)
1031 goto out_free_irq;
1032
1033 /* PHY control start*/
1034 ret = sh_eth_phy_start(ndev);
1035 if (ret)
1036 goto out_free_irq;
1037
1038 /* Set the timer to check for link beat. */
1039 init_timer(&mdp->timer);
1040 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1041 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
1042
1043 return ret;
1044
1045 out_free_irq:
1046 free_irq(ndev->irq, ndev);
1047 return ret;
1048 }
1049
1050 /* Timeout function */
1051 static void sh_eth_tx_timeout(struct net_device *ndev)
1052 {
1053 struct sh_eth_private *mdp = netdev_priv(ndev);
1054 u32 ioaddr = ndev->base_addr;
1055 struct sh_eth_rxdesc *rxdesc;
1056 int i;
1057
1058 netif_stop_queue(ndev);
1059
1060 /* worning message out. */
1061 printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
1062 " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
1063
1064 /* tx_errors count up */
1065 mdp->stats.tx_errors++;
1066
1067 /* timer off */
1068 del_timer_sync(&mdp->timer);
1069
1070 /* Free all the skbuffs in the Rx queue. */
1071 for (i = 0; i < RX_RING_SIZE; i++) {
1072 rxdesc = &mdp->rx_ring[i];
1073 rxdesc->status = 0;
1074 rxdesc->addr = 0xBADF00D0;
1075 if (mdp->rx_skbuff[i])
1076 dev_kfree_skb(mdp->rx_skbuff[i]);
1077 mdp->rx_skbuff[i] = NULL;
1078 }
1079 for (i = 0; i < TX_RING_SIZE; i++) {
1080 if (mdp->tx_skbuff[i])
1081 dev_kfree_skb(mdp->tx_skbuff[i]);
1082 mdp->tx_skbuff[i] = NULL;
1083 }
1084
1085 /* device init */
1086 sh_eth_dev_init(ndev);
1087
1088 /* timer on */
1089 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1090 add_timer(&mdp->timer);
1091 }
1092
1093 /* Packet transmit function */
1094 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1095 {
1096 struct sh_eth_private *mdp = netdev_priv(ndev);
1097 struct sh_eth_txdesc *txdesc;
1098 u32 entry;
1099 unsigned long flags;
1100
1101 spin_lock_irqsave(&mdp->lock, flags);
1102 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1103 if (!sh_eth_txfree(ndev)) {
1104 netif_stop_queue(ndev);
1105 spin_unlock_irqrestore(&mdp->lock, flags);
1106 return NETDEV_TX_BUSY;
1107 }
1108 }
1109 spin_unlock_irqrestore(&mdp->lock, flags);
1110
1111 entry = mdp->cur_tx % TX_RING_SIZE;
1112 mdp->tx_skbuff[entry] = skb;
1113 txdesc = &mdp->tx_ring[entry];
1114 txdesc->addr = virt_to_phys(skb->data);
1115 /* soft swap. */
1116 if (!mdp->cd->hw_swap)
1117 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1118 skb->len + 2);
1119 /* write back */
1120 __flush_purge_region(skb->data, skb->len);
1121 if (skb->len < ETHERSMALL)
1122 txdesc->buffer_length = ETHERSMALL;
1123 else
1124 txdesc->buffer_length = skb->len;
1125
1126 if (entry >= TX_RING_SIZE - 1)
1127 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
1128 else
1129 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
1130
1131 mdp->cur_tx++;
1132
1133 if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
1134 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
1135
1136 ndev->trans_start = jiffies;
1137
1138 return NETDEV_TX_OK;
1139 }
1140
1141 /* device close function */
1142 static int sh_eth_close(struct net_device *ndev)
1143 {
1144 struct sh_eth_private *mdp = netdev_priv(ndev);
1145 u32 ioaddr = ndev->base_addr;
1146 int ringsize;
1147
1148 netif_stop_queue(ndev);
1149
1150 /* Disable interrupts by clearing the interrupt mask. */
1151 ctrl_outl(0x0000, ioaddr + EESIPR);
1152
1153 /* Stop the chip's Tx and Rx processes. */
1154 ctrl_outl(0, ioaddr + EDTRR);
1155 ctrl_outl(0, ioaddr + EDRRR);
1156
1157 /* PHY Disconnect */
1158 if (mdp->phydev) {
1159 phy_stop(mdp->phydev);
1160 phy_disconnect(mdp->phydev);
1161 }
1162
1163 free_irq(ndev->irq, ndev);
1164
1165 del_timer_sync(&mdp->timer);
1166
1167 /* Free all the skbuffs in the Rx queue. */
1168 sh_eth_ring_free(ndev);
1169
1170 /* free DMA buffer */
1171 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1172 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1173
1174 /* free DMA buffer */
1175 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1176 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1177
1178 return 0;
1179 }
1180
1181 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1182 {
1183 struct sh_eth_private *mdp = netdev_priv(ndev);
1184 u32 ioaddr = ndev->base_addr;
1185
1186 mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
1187 ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
1188 mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
1189 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
1190 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
1191 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
1192 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1193 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
1194 ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
1195 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
1196 ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
1197 #else
1198 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
1199 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
1200 #endif
1201 return &mdp->stats;
1202 }
1203
1204 /* ioctl to device funciotn*/
1205 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1206 int cmd)
1207 {
1208 struct sh_eth_private *mdp = netdev_priv(ndev);
1209 struct phy_device *phydev = mdp->phydev;
1210
1211 if (!netif_running(ndev))
1212 return -EINVAL;
1213
1214 if (!phydev)
1215 return -ENODEV;
1216
1217 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
1218 }
1219
1220 #if defined(SH_ETH_HAS_TSU)
1221 /* Multicast reception directions set */
1222 static void sh_eth_set_multicast_list(struct net_device *ndev)
1223 {
1224 u32 ioaddr = ndev->base_addr;
1225
1226 if (ndev->flags & IFF_PROMISC) {
1227 /* Set promiscuous. */
1228 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
1229 ioaddr + ECMR);
1230 } else {
1231 /* Normal, unicast/broadcast-only mode. */
1232 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
1233 ioaddr + ECMR);
1234 }
1235 }
1236
1237 /* SuperH's TSU register init function */
1238 static void sh_eth_tsu_init(u32 ioaddr)
1239 {
1240 ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
1241 ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
1242 ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
1243 ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
1244 ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
1245 ctrl_outl(0, ioaddr + TSU_PRISL0);
1246 ctrl_outl(0, ioaddr + TSU_PRISL1);
1247 ctrl_outl(0, ioaddr + TSU_FWSL0);
1248 ctrl_outl(0, ioaddr + TSU_FWSL1);
1249 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
1250 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1251 ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1252 ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1253 #else
1254 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
1255 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
1256 #endif
1257 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
1258 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
1259 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
1260 ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
1261 ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
1262 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1263 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
1264 }
1265 #endif /* SH_ETH_HAS_TSU */
1266
1267 /* MDIO bus release function */
1268 static int sh_mdio_release(struct net_device *ndev)
1269 {
1270 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1271
1272 /* unregister mdio bus */
1273 mdiobus_unregister(bus);
1274
1275 /* remove mdio bus info from net_device */
1276 dev_set_drvdata(&ndev->dev, NULL);
1277
1278 /* free bitbang info */
1279 free_mdio_bitbang(bus);
1280
1281 return 0;
1282 }
1283
1284 /* MDIO bus init function */
1285 static int sh_mdio_init(struct net_device *ndev, int id)
1286 {
1287 int ret, i;
1288 struct bb_info *bitbang;
1289 struct sh_eth_private *mdp = netdev_priv(ndev);
1290
1291 /* create bit control struct for PHY */
1292 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1293 if (!bitbang) {
1294 ret = -ENOMEM;
1295 goto out;
1296 }
1297
1298 /* bitbang init */
1299 bitbang->addr = ndev->base_addr + PIR;
1300 bitbang->mdi_msk = 0x08;
1301 bitbang->mdo_msk = 0x04;
1302 bitbang->mmd_msk = 0x02;/* MMD */
1303 bitbang->mdc_msk = 0x01;
1304 bitbang->ctrl.ops = &bb_ops;
1305
1306 /* MII contorller setting */
1307 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1308 if (!mdp->mii_bus) {
1309 ret = -ENOMEM;
1310 goto out_free_bitbang;
1311 }
1312
1313 /* Hook up MII support for ethtool */
1314 mdp->mii_bus->name = "sh_mii";
1315 mdp->mii_bus->parent = &ndev->dev;
1316 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
1317
1318 /* PHY IRQ */
1319 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1320 if (!mdp->mii_bus->irq) {
1321 ret = -ENOMEM;
1322 goto out_free_bus;
1323 }
1324
1325 for (i = 0; i < PHY_MAX_ADDR; i++)
1326 mdp->mii_bus->irq[i] = PHY_POLL;
1327
1328 /* regist mdio bus */
1329 ret = mdiobus_register(mdp->mii_bus);
1330 if (ret)
1331 goto out_free_irq;
1332
1333 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1334
1335 return 0;
1336
1337 out_free_irq:
1338 kfree(mdp->mii_bus->irq);
1339
1340 out_free_bus:
1341 free_mdio_bitbang(mdp->mii_bus);
1342
1343 out_free_bitbang:
1344 kfree(bitbang);
1345
1346 out:
1347 return ret;
1348 }
1349
1350 static const struct net_device_ops sh_eth_netdev_ops = {
1351 .ndo_open = sh_eth_open,
1352 .ndo_stop = sh_eth_close,
1353 .ndo_start_xmit = sh_eth_start_xmit,
1354 .ndo_get_stats = sh_eth_get_stats,
1355 #if defined(SH_ETH_HAS_TSU)
1356 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1357 #endif
1358 .ndo_tx_timeout = sh_eth_tx_timeout,
1359 .ndo_do_ioctl = sh_eth_do_ioctl,
1360 .ndo_validate_addr = eth_validate_addr,
1361 .ndo_set_mac_address = eth_mac_addr,
1362 .ndo_change_mtu = eth_change_mtu,
1363 };
1364
1365 static int sh_eth_drv_probe(struct platform_device *pdev)
1366 {
1367 int ret, i, devno = 0;
1368 struct resource *res;
1369 struct net_device *ndev = NULL;
1370 struct sh_eth_private *mdp;
1371 struct sh_eth_plat_data *pd;
1372
1373 /* get base addr */
1374 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1375 if (unlikely(res == NULL)) {
1376 dev_err(&pdev->dev, "invalid resource\n");
1377 ret = -EINVAL;
1378 goto out;
1379 }
1380
1381 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1382 if (!ndev) {
1383 dev_err(&pdev->dev, "Could not allocate device.\n");
1384 ret = -ENOMEM;
1385 goto out;
1386 }
1387
1388 /* The sh Ether-specific entries in the device structure. */
1389 ndev->base_addr = res->start;
1390 devno = pdev->id;
1391 if (devno < 0)
1392 devno = 0;
1393
1394 ndev->dma = -1;
1395 ret = platform_get_irq(pdev, 0);
1396 if (ret < 0) {
1397 ret = -ENODEV;
1398 goto out_release;
1399 }
1400 ndev->irq = ret;
1401
1402 SET_NETDEV_DEV(ndev, &pdev->dev);
1403
1404 /* Fill in the fields of the device structure with ethernet values. */
1405 ether_setup(ndev);
1406
1407 mdp = netdev_priv(ndev);
1408 spin_lock_init(&mdp->lock);
1409
1410 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1411 /* get PHY ID */
1412 mdp->phy_id = pd->phy;
1413 /* EDMAC endian */
1414 mdp->edmac_endian = pd->edmac_endian;
1415 mdp->no_ether_link = pd->no_ether_link;
1416 mdp->ether_link_active_low = pd->ether_link_active_low;
1417
1418 /* set cpu data */
1419 mdp->cd = &sh_eth_my_cpu_data;
1420 sh_eth_set_default_cpu_data(mdp->cd);
1421
1422 /* set function */
1423 ndev->netdev_ops = &sh_eth_netdev_ops;
1424 ndev->watchdog_timeo = TX_TIMEOUT;
1425
1426 mdp->post_rx = POST_RX >> (devno << 1);
1427 mdp->post_fw = POST_FW >> (devno << 1);
1428
1429 /* read and set MAC address */
1430 read_mac_address(ndev);
1431
1432 /* First device only init */
1433 if (!devno) {
1434 if (mdp->cd->chip_reset)
1435 mdp->cd->chip_reset(ndev);
1436
1437 #if defined(SH_ETH_HAS_TSU)
1438 /* TSU init (Init only)*/
1439 sh_eth_tsu_init(SH_TSU_ADDR);
1440 #endif
1441 }
1442
1443 /* network device register */
1444 ret = register_netdev(ndev);
1445 if (ret)
1446 goto out_release;
1447
1448 /* mdio bus init */
1449 ret = sh_mdio_init(ndev, pdev->id);
1450 if (ret)
1451 goto out_unregister;
1452
1453 /* pritnt device infomation */
1454 pr_info("Base address at 0x%x, ",
1455 (u32)ndev->base_addr);
1456
1457 for (i = 0; i < 5; i++)
1458 printk("%02X:", ndev->dev_addr[i]);
1459 printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
1460
1461 platform_set_drvdata(pdev, ndev);
1462
1463 return ret;
1464
1465 out_unregister:
1466 unregister_netdev(ndev);
1467
1468 out_release:
1469 /* net_dev free */
1470 if (ndev)
1471 free_netdev(ndev);
1472
1473 out:
1474 return ret;
1475 }
1476
1477 static int sh_eth_drv_remove(struct platform_device *pdev)
1478 {
1479 struct net_device *ndev = platform_get_drvdata(pdev);
1480
1481 sh_mdio_release(ndev);
1482 unregister_netdev(ndev);
1483 flush_scheduled_work();
1484
1485 free_netdev(ndev);
1486 platform_set_drvdata(pdev, NULL);
1487
1488 return 0;
1489 }
1490
1491 static struct platform_driver sh_eth_driver = {
1492 .probe = sh_eth_drv_probe,
1493 .remove = sh_eth_drv_remove,
1494 .driver = {
1495 .name = CARDNAME,
1496 },
1497 };
1498
1499 static int __init sh_eth_init(void)
1500 {
1501 return platform_driver_register(&sh_eth_driver);
1502 }
1503
1504 static void __exit sh_eth_cleanup(void)
1505 {
1506 platform_driver_unregister(&sh_eth_driver);
1507 }
1508
1509 module_init(sh_eth_init);
1510 module_exit(sh_eth_cleanup);
1511
1512 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1513 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1514 MODULE_LICENSE("GPL v2");
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