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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / sundance.c
blobe13685a570f401b0276c7db0691eff20b5024fe3
1 /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
2 /*
3 Written 1999-2000 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/sundance.html
19 [link no longer provides useful info -jgarzik]
20 Archives of the mailing list are still available at
21 http://www.beowulf.org/pipermail/netdrivers/
22
23 */
24
25 #define DRV_NAME "sundance"
26 #define DRV_VERSION "1.2"
27 #define DRV_RELDATE "11-Sep-2006"
28
29
30 /* The user-configurable values.
31 These may be modified when a driver module is loaded.*/
32 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
33 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
34 Typical is a 64 element hash table based on the Ethernet CRC. */
35 static const int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
38 Setting to > 1518 effectively disables this feature.
39 This chip can receive into offset buffers, so the Alpha does not
40 need a copy-align. */
41 static int rx_copybreak;
42 static int flowctrl=1;
43
44 /* media[] specifies the media type the NIC operates at.
45 autosense Autosensing active media.
46 10mbps_hd 10Mbps half duplex.
47 10mbps_fd 10Mbps full duplex.
48 100mbps_hd 100Mbps half duplex.
49 100mbps_fd 100Mbps full duplex.
50 0 Autosensing active media.
51 1 10Mbps half duplex.
52 2 10Mbps full duplex.
53 3 100Mbps half duplex.
54 4 100Mbps full duplex.
55 */
56 #define MAX_UNITS 8
57 static char *media[MAX_UNITS];
58
59
60 /* Operational parameters that are set at compile time. */
61
62 /* Keep the ring sizes a power of two for compile efficiency.
63 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
64 Making the Tx ring too large decreases the effectiveness of channel
65 bonding and packet priority, and more than 128 requires modifying the
66 Tx error recovery.
67 Large receive rings merely waste memory. */
68 #define TX_RING_SIZE 32
69 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */
70 #define RX_RING_SIZE 64
71 #define RX_BUDGET 32
72 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
73 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
74
75 /* Operational parameters that usually are not changed. */
76 /* Time in jiffies before concluding the transmitter is hung. */
77 #define TX_TIMEOUT (4*HZ)
78 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
79
80 /* Include files, designed to support most kernel versions 2.0.0 and later. */
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/string.h>
84 #include <linux/timer.h>
85 #include <linux/errno.h>
86 #include <linux/ioport.h>
87 #include <linux/slab.h>
88 #include <linux/interrupt.h>
89 #include <linux/pci.h>
90 #include <linux/netdevice.h>
91 #include <linux/etherdevice.h>
92 #include <linux/skbuff.h>
93 #include <linux/init.h>
94 #include <linux/bitops.h>
95 #include <asm/uaccess.h>
96 #include <asm/processor.h> /* Processor type for cache alignment. */
97 #include <asm/io.h>
98 #include <linux/delay.h>
99 #include <linux/spinlock.h>
100 #ifndef _COMPAT_WITH_OLD_KERNEL
101 #include <linux/crc32.h>
102 #include <linux/ethtool.h>
103 #include <linux/mii.h>
104 #else
105 #include "crc32.h"
106 #include "ethtool.h"
107 #include "mii.h"
108 #include "compat.h"
109 #endif
110
111 /* These identify the driver base version and may not be removed. */
112 static const char version[] __devinitconst =
113 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE
114 " Written by Donald Becker\n";
115
116 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
117 MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
118 MODULE_LICENSE("GPL");
119
120 module_param(debug, int, 0);
121 module_param(rx_copybreak, int, 0);
122 module_param_array(media, charp, NULL, 0);
123 module_param(flowctrl, int, 0);
124 MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)");
125 MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames");
126 MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]");
127
128 /*
129 Theory of Operation
130
131 I. Board Compatibility
132
133 This driver is designed for the Sundance Technologies "Alta" ST201 chip.
134
135 II. Board-specific settings
136
137 III. Driver operation
138
139 IIIa. Ring buffers
140
141 This driver uses two statically allocated fixed-size descriptor lists
142 formed into rings by a branch from the final descriptor to the beginning of
143 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
144 Some chips explicitly use only 2^N sized rings, while others use a
145 'next descriptor' pointer that the driver forms into rings.
146
147 IIIb/c. Transmit/Receive Structure
148
149 This driver uses a zero-copy receive and transmit scheme.
150 The driver allocates full frame size skbuffs for the Rx ring buffers at
151 open() time and passes the skb->data field to the chip as receive data
152 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
153 a fresh skbuff is allocated and the frame is copied to the new skbuff.
154 When the incoming frame is larger, the skbuff is passed directly up the
155 protocol stack. Buffers consumed this way are replaced by newly allocated
156 skbuffs in a later phase of receives.
157
158 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
159 using a full-sized skbuff for small frames vs. the copying costs of larger
160 frames. New boards are typically used in generously configured machines
161 and the underfilled buffers have negligible impact compared to the benefit of
162 a single allocation size, so the default value of zero results in never
163 copying packets. When copying is done, the cost is usually mitigated by using
164 a combined copy/checksum routine. Copying also preloads the cache, which is
165 most useful with small frames.
166
167 A subtle aspect of the operation is that the IP header at offset 14 in an
168 ethernet frame isn't longword aligned for further processing.
169 Unaligned buffers are permitted by the Sundance hardware, so
170 frames are received into the skbuff at an offset of "+2", 16-byte aligning
171 the IP header.
172
173 IIId. Synchronization
174
175 The driver runs as two independent, single-threaded flows of control. One
176 is the send-packet routine, which enforces single-threaded use by the
177 dev->tbusy flag. The other thread is the interrupt handler, which is single
178 threaded by the hardware and interrupt handling software.
179
180 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
181 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
182 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
183 the 'lp->tx_full' flag.
184
185 The interrupt handler has exclusive control over the Rx ring and records stats
186 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
187 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
188 clears both the tx_full and tbusy flags.
189
190 IV. Notes
191
192 IVb. References
193
194 The Sundance ST201 datasheet, preliminary version.
195 The Kendin KS8723 datasheet, preliminary version.
196 The ICplus IP100 datasheet, preliminary version.
197 http://www.scyld.com/expert/100mbps.html
198 http://www.scyld.com/expert/NWay.html
199
200 IVc. Errata
201
202 */
203
204 /* Work-around for Kendin chip bugs. */
205 #ifndef CONFIG_SUNDANCE_MMIO
206 #define USE_IO_OPS 1
207 #endif
208
209 static const struct pci_device_id sundance_pci_tbl[] = {
210 { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
211 { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
212 { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
213 { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
214 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
215 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
216 { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
217 { }
218 };
219 MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
220
221 enum {
222 netdev_io_size = 128
223 };
224
225 struct pci_id_info {
226 const char *name;
227 };
228 static const struct pci_id_info pci_id_tbl[] __devinitdata = {
229 {"D-Link DFE-550TX FAST Ethernet Adapter"},
230 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
231 {"D-Link DFE-580TX 4 port Server Adapter"},
232 {"D-Link DFE-530TXS FAST Ethernet Adapter"},
233 {"D-Link DL10050-based FAST Ethernet Adapter"},
234 {"Sundance Technology Alta"},
235 {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
236 { } /* terminate list. */
237 };
238
239 /* This driver was written to use PCI memory space, however x86-oriented
240 hardware often uses I/O space accesses. */
241
242 /* Offsets to the device registers.
243 Unlike software-only systems, device drivers interact with complex hardware.
244 It's not useful to define symbolic names for every register bit in the
245 device. The name can only partially document the semantics and make
246 the driver longer and more difficult to read.
247 In general, only the important configuration values or bits changed
248 multiple times should be defined symbolically.
249 */
250 enum alta_offsets {
251 DMACtrl = 0x00,
252 TxListPtr = 0x04,
253 TxDMABurstThresh = 0x08,
254 TxDMAUrgentThresh = 0x09,
255 TxDMAPollPeriod = 0x0a,
256 RxDMAStatus = 0x0c,
257 RxListPtr = 0x10,
258 DebugCtrl0 = 0x1a,
259 DebugCtrl1 = 0x1c,
260 RxDMABurstThresh = 0x14,
261 RxDMAUrgentThresh = 0x15,
262 RxDMAPollPeriod = 0x16,
263 LEDCtrl = 0x1a,
264 ASICCtrl = 0x30,
265 EEData = 0x34,
266 EECtrl = 0x36,
267 FlashAddr = 0x40,
268 FlashData = 0x44,
269 TxStatus = 0x46,
270 TxFrameId = 0x47,
271 DownCounter = 0x18,
272 IntrClear = 0x4a,
273 IntrEnable = 0x4c,
274 IntrStatus = 0x4e,
275 MACCtrl0 = 0x50,
276 MACCtrl1 = 0x52,
277 StationAddr = 0x54,
278 MaxFrameSize = 0x5A,
279 RxMode = 0x5c,
280 MIICtrl = 0x5e,
281 MulticastFilter0 = 0x60,
282 MulticastFilter1 = 0x64,
283 RxOctetsLow = 0x68,
284 RxOctetsHigh = 0x6a,
285 TxOctetsLow = 0x6c,
286 TxOctetsHigh = 0x6e,
287 TxFramesOK = 0x70,
288 RxFramesOK = 0x72,
289 StatsCarrierError = 0x74,
290 StatsLateColl = 0x75,
291 StatsMultiColl = 0x76,
292 StatsOneColl = 0x77,
293 StatsTxDefer = 0x78,
294 RxMissed = 0x79,
295 StatsTxXSDefer = 0x7a,
296 StatsTxAbort = 0x7b,
297 StatsBcastTx = 0x7c,
298 StatsBcastRx = 0x7d,
299 StatsMcastTx = 0x7e,
300 StatsMcastRx = 0x7f,
301 /* Aliased and bogus values! */
302 RxStatus = 0x0c,
303 };
304 enum ASICCtrl_HiWord_bit {
305 GlobalReset = 0x0001,
306 RxReset = 0x0002,
307 TxReset = 0x0004,
308 DMAReset = 0x0008,
309 FIFOReset = 0x0010,
310 NetworkReset = 0x0020,
311 HostReset = 0x0040,
312 ResetBusy = 0x0400,
313 };
314
315 /* Bits in the interrupt status/mask registers. */
316 enum intr_status_bits {
317 IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
318 IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
319 IntrDrvRqst=0x0040,
320 StatsMax=0x0080, LinkChange=0x0100,
321 IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
322 };
323
324 /* Bits in the RxMode register. */
325 enum rx_mode_bits {
326 AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
327 AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
328 };
329 /* Bits in MACCtrl. */
330 enum mac_ctrl0_bits {
331 EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
332 EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
333 };
334 enum mac_ctrl1_bits {
335 StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
336 TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
337 RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
338 };
339
340 /* The Rx and Tx buffer descriptors. */
341 /* Note that using only 32 bit fields simplifies conversion to big-endian
342 architectures. */
343 struct netdev_desc {
344 __le32 next_desc;
345 __le32 status;
346 struct desc_frag { __le32 addr, length; } frag[1];
347 };
348
349 /* Bits in netdev_desc.status */
350 enum desc_status_bits {
351 DescOwn=0x8000,
352 DescEndPacket=0x4000,
353 DescEndRing=0x2000,
354 LastFrag=0x80000000,
355 DescIntrOnTx=0x8000,
356 DescIntrOnDMADone=0x80000000,
357 DisableAlign = 0x00000001,
358 };
359
360 #define PRIV_ALIGN 15 /* Required alignment mask */
361 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
362 within the structure. */
363 #define MII_CNT 4
364 struct netdev_private {
365 /* Descriptor rings first for alignment. */
366 struct netdev_desc *rx_ring;
367 struct netdev_desc *tx_ring;
368 struct sk_buff* rx_skbuff[RX_RING_SIZE];
369 struct sk_buff* tx_skbuff[TX_RING_SIZE];
370 dma_addr_t tx_ring_dma;
371 dma_addr_t rx_ring_dma;
372 struct timer_list timer; /* Media monitoring timer. */
373 /* Frequently used values: keep some adjacent for cache effect. */
374 spinlock_t lock;
375 spinlock_t rx_lock; /* Group with Tx control cache line. */
376 int msg_enable;
377 int chip_id;
378 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
379 unsigned int rx_buf_sz; /* Based on MTU+slack. */
380 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
381 unsigned int cur_tx, dirty_tx;
382 /* These values are keep track of the transceiver/media in use. */
383 unsigned int flowctrl:1;
384 unsigned int default_port:4; /* Last dev->if_port value. */
385 unsigned int an_enable:1;
386 unsigned int speed;
387 struct tasklet_struct rx_tasklet;
388 struct tasklet_struct tx_tasklet;
389 int budget;
390 int cur_task;
391 /* Multicast and receive mode. */
392 spinlock_t mcastlock; /* SMP lock multicast updates. */
393 u16 mcast_filter[4];
394 /* MII transceiver section. */
395 struct mii_if_info mii_if;
396 int mii_preamble_required;
397 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
398 struct pci_dev *pci_dev;
399 void __iomem *base;
400 };
401
402 /* The station address location in the EEPROM. */
403 #define EEPROM_SA_OFFSET 0x10
404 #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
405 IntrDrvRqst | IntrTxDone | StatsMax | \
406 LinkChange)
407
408 static int change_mtu(struct net_device *dev, int new_mtu);
409 static int eeprom_read(void __iomem *ioaddr, int location);
410 static int mdio_read(struct net_device *dev, int phy_id, int location);
411 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
412 static int mdio_wait_link(struct net_device *dev, int wait);
413 static int netdev_open(struct net_device *dev);
414 static void check_duplex(struct net_device *dev);
415 static void netdev_timer(unsigned long data);
416 static void tx_timeout(struct net_device *dev);
417 static void init_ring(struct net_device *dev);
418 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
419 static int reset_tx (struct net_device *dev);
420 static irqreturn_t intr_handler(int irq, void *dev_instance);
421 static void rx_poll(unsigned long data);
422 static void tx_poll(unsigned long data);
423 static void refill_rx (struct net_device *dev);
424 static void netdev_error(struct net_device *dev, int intr_status);
425 static void netdev_error(struct net_device *dev, int intr_status);
426 static void set_rx_mode(struct net_device *dev);
427 static int __set_mac_addr(struct net_device *dev);
428 static struct net_device_stats *get_stats(struct net_device *dev);
429 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
430 static int netdev_close(struct net_device *dev);
431 static const struct ethtool_ops ethtool_ops;
432
433 static void sundance_reset(struct net_device *dev, unsigned long reset_cmd)
434 {
435 struct netdev_private *np = netdev_priv(dev);
436 void __iomem *ioaddr = np->base + ASICCtrl;
437 int countdown;
438
439 /* ST201 documentation states ASICCtrl is a 32bit register */
440 iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr);
441 /* ST201 documentation states reset can take up to 1 ms */
442 countdown = 10 + 1;
443 while (ioread32 (ioaddr) & (ResetBusy << 16)) {
444 if (--countdown == 0) {
445 printk(KERN_WARNING "%s : reset not completed !!\n", dev->name);
446 break;
447 }
448 udelay(100);
449 }
450 }
451
452 static const struct net_device_ops netdev_ops = {
453 .ndo_open = netdev_open,
454 .ndo_stop = netdev_close,
455 .ndo_start_xmit = start_tx,
456 .ndo_get_stats = get_stats,
457 .ndo_set_multicast_list = set_rx_mode,
458 .ndo_do_ioctl = netdev_ioctl,
459 .ndo_tx_timeout = tx_timeout,
460 .ndo_change_mtu = change_mtu,
461 .ndo_set_mac_address = eth_mac_addr,
462 .ndo_validate_addr = eth_validate_addr,
463 };
464
465 static int __devinit sundance_probe1 (struct pci_dev *pdev,
466 const struct pci_device_id *ent)
467 {
468 struct net_device *dev;
469 struct netdev_private *np;
470 static int card_idx;
471 int chip_idx = ent->driver_data;
472 int irq;
473 int i;
474 void __iomem *ioaddr;
475 u16 mii_ctl;
476 void *ring_space;
477 dma_addr_t ring_dma;
478 #ifdef USE_IO_OPS
479 int bar = 0;
480 #else
481 int bar = 1;
482 #endif
483 int phy, phy_end, phy_idx = 0;
484
485 /* when built into the kernel, we only print version if device is found */
486 #ifndef MODULE
487 static int printed_version;
488 if (!printed_version++)
489 printk(version);
490 #endif
491
492 if (pci_enable_device(pdev))
493 return -EIO;
494 pci_set_master(pdev);
495
496 irq = pdev->irq;
497
498 dev = alloc_etherdev(sizeof(*np));
499 if (!dev)
500 return -ENOMEM;
501 SET_NETDEV_DEV(dev, &pdev->dev);
502
503 if (pci_request_regions(pdev, DRV_NAME))
504 goto err_out_netdev;
505
506 ioaddr = pci_iomap(pdev, bar, netdev_io_size);
507 if (!ioaddr)
508 goto err_out_res;
509
510 for (i = 0; i < 3; i++)
511 ((__le16 *)dev->dev_addr)[i] =
512 cpu_to_le16(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
513 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
514
515 dev->base_addr = (unsigned long)ioaddr;
516 dev->irq = irq;
517
518 np = netdev_priv(dev);
519 np->base = ioaddr;
520 np->pci_dev = pdev;
521 np->chip_id = chip_idx;
522 np->msg_enable = (1 << debug) - 1;
523 spin_lock_init(&np->lock);
524 tasklet_init(&np->rx_tasklet, rx_poll, (unsigned long)dev);
525 tasklet_init(&np->tx_tasklet, tx_poll, (unsigned long)dev);
526
527 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
528 if (!ring_space)
529 goto err_out_cleardev;
530 np->tx_ring = (struct netdev_desc *)ring_space;
531 np->tx_ring_dma = ring_dma;
532
533 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
534 if (!ring_space)
535 goto err_out_unmap_tx;
536 np->rx_ring = (struct netdev_desc *)ring_space;
537 np->rx_ring_dma = ring_dma;
538
539 np->mii_if.dev = dev;
540 np->mii_if.mdio_read = mdio_read;
541 np->mii_if.mdio_write = mdio_write;
542 np->mii_if.phy_id_mask = 0x1f;
543 np->mii_if.reg_num_mask = 0x1f;
544
545 /* The chip-specific entries in the device structure. */
546 dev->netdev_ops = &netdev_ops;
547 SET_ETHTOOL_OPS(dev, &ethtool_ops);
548 dev->watchdog_timeo = TX_TIMEOUT;
549
550 pci_set_drvdata(pdev, dev);
551
552 i = register_netdev(dev);
553 if (i)
554 goto err_out_unmap_rx;
555
556 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
557 dev->name, pci_id_tbl[chip_idx].name, ioaddr,
558 dev->dev_addr, irq);
559
560 np->phys[0] = 1; /* Default setting */
561 np->mii_preamble_required++;
562
563 /*
564 * It seems some phys doesn't deal well with address 0 being accessed
565 * first
566 */
567 if (sundance_pci_tbl[np->chip_id].device == 0x0200) {
568 phy = 0;
569 phy_end = 31;
570 } else {
571 phy = 1;
572 phy_end = 32; /* wraps to zero, due to 'phy & 0x1f' */
573 }
574 for (; phy <= phy_end && phy_idx < MII_CNT; phy++) {
575 int phyx = phy & 0x1f;
576 int mii_status = mdio_read(dev, phyx, MII_BMSR);
577 if (mii_status != 0xffff && mii_status != 0x0000) {
578 np->phys[phy_idx++] = phyx;
579 np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE);
580 if ((mii_status & 0x0040) == 0)
581 np->mii_preamble_required++;
582 printk(KERN_INFO "%s: MII PHY found at address %d, status "
583 "0x%4.4x advertising %4.4x.\n",
584 dev->name, phyx, mii_status, np->mii_if.advertising);
585 }
586 }
587 np->mii_preamble_required--;
588
589 if (phy_idx == 0) {
590 printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n",
591 dev->name, ioread32(ioaddr + ASICCtrl));
592 goto err_out_unregister;
593 }
594
595 np->mii_if.phy_id = np->phys[0];
596
597 /* Parse override configuration */
598 np->an_enable = 1;
599 if (card_idx < MAX_UNITS) {
600 if (media[card_idx] != NULL) {
601 np->an_enable = 0;
602 if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
603 strcmp (media[card_idx], "4") == 0) {
604 np->speed = 100;
605 np->mii_if.full_duplex = 1;
606 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
607 || strcmp (media[card_idx], "3") == 0) {
608 np->speed = 100;
609 np->mii_if.full_duplex = 0;
610 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
611 strcmp (media[card_idx], "2") == 0) {
612 np->speed = 10;
613 np->mii_if.full_duplex = 1;
614 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
615 strcmp (media[card_idx], "1") == 0) {
616 np->speed = 10;
617 np->mii_if.full_duplex = 0;
618 } else {
619 np->an_enable = 1;
620 }
621 }
622 if (flowctrl == 1)
623 np->flowctrl = 1;
624 }
625
626 /* Fibre PHY? */
627 if (ioread32 (ioaddr + ASICCtrl) & 0x80) {
628 /* Default 100Mbps Full */
629 if (np->an_enable) {
630 np->speed = 100;
631 np->mii_if.full_duplex = 1;
632 np->an_enable = 0;
633 }
634 }
635 /* Reset PHY */
636 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
637 mdelay (300);
638 /* If flow control enabled, we need to advertise it.*/
639 if (np->flowctrl)
640 mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400);
641 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
642 /* Force media type */
643 if (!np->an_enable) {
644 mii_ctl = 0;
645 mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0;
646 mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
647 mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
648 printk (KERN_INFO "Override speed=%d, %s duplex\n",
649 np->speed, np->mii_if.full_duplex ? "Full" : "Half");
650
651 }
652
653 /* Perhaps move the reset here? */
654 /* Reset the chip to erase previous misconfiguration. */
655 if (netif_msg_hw(np))
656 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
657 sundance_reset(dev, 0x00ff << 16);
658 if (netif_msg_hw(np))
659 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
660
661 card_idx++;
662 return 0;
663
664 err_out_unregister:
665 unregister_netdev(dev);
666 err_out_unmap_rx:
667 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
668 err_out_unmap_tx:
669 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
670 err_out_cleardev:
671 pci_set_drvdata(pdev, NULL);
672 pci_iounmap(pdev, ioaddr);
673 err_out_res:
674 pci_release_regions(pdev);
675 err_out_netdev:
676 free_netdev (dev);
677 return -ENODEV;
678 }
679
680 static int change_mtu(struct net_device *dev, int new_mtu)
681 {
682 if ((new_mtu < 68) || (new_mtu > 8191)) /* Set by RxDMAFrameLen */
683 return -EINVAL;
684 if (netif_running(dev))
685 return -EBUSY;
686 dev->mtu = new_mtu;
687 return 0;
688 }
689
690 #define eeprom_delay(ee_addr) ioread32(ee_addr)
691 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
692 static int __devinit eeprom_read(void __iomem *ioaddr, int location)
693 {
694 int boguscnt = 10000; /* Typical 1900 ticks. */
695 iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl);
696 do {
697 eeprom_delay(ioaddr + EECtrl);
698 if (! (ioread16(ioaddr + EECtrl) & 0x8000)) {
699 return ioread16(ioaddr + EEData);
700 }
701 } while (--boguscnt > 0);
702 return 0;
703 }
704
705 /* MII transceiver control section.
706 Read and write the MII registers using software-generated serial
707 MDIO protocol. See the MII specifications or DP83840A data sheet
708 for details.
709
710 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
711 met by back-to-back 33Mhz PCI cycles. */
712 #define mdio_delay() ioread8(mdio_addr)
713
714 enum mii_reg_bits {
715 MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
716 };
717 #define MDIO_EnbIn (0)
718 #define MDIO_WRITE0 (MDIO_EnbOutput)
719 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
720
721 /* Generate the preamble required for initial synchronization and
722 a few older transceivers. */
723 static void mdio_sync(void __iomem *mdio_addr)
724 {
725 int bits = 32;
726
727 /* Establish sync by sending at least 32 logic ones. */
728 while (--bits >= 0) {
729 iowrite8(MDIO_WRITE1, mdio_addr);
730 mdio_delay();
731 iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
732 mdio_delay();
733 }
734 }
735
736 static int mdio_read(struct net_device *dev, int phy_id, int location)
737 {
738 struct netdev_private *np = netdev_priv(dev);
739 void __iomem *mdio_addr = np->base + MIICtrl;
740 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
741 int i, retval = 0;
742
743 if (np->mii_preamble_required)
744 mdio_sync(mdio_addr);
745
746 /* Shift the read command bits out. */
747 for (i = 15; i >= 0; i--) {
748 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
749
750 iowrite8(dataval, mdio_addr);
751 mdio_delay();
752 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
753 mdio_delay();
754 }
755 /* Read the two transition, 16 data, and wire-idle bits. */
756 for (i = 19; i > 0; i--) {
757 iowrite8(MDIO_EnbIn, mdio_addr);
758 mdio_delay();
759 retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0);
760 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
761 mdio_delay();
762 }
763 return (retval>>1) & 0xffff;
764 }
765
766 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
767 {
768 struct netdev_private *np = netdev_priv(dev);
769 void __iomem *mdio_addr = np->base + MIICtrl;
770 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
771 int i;
772
773 if (np->mii_preamble_required)
774 mdio_sync(mdio_addr);
775
776 /* Shift the command bits out. */
777 for (i = 31; i >= 0; i--) {
778 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
779
780 iowrite8(dataval, mdio_addr);
781 mdio_delay();
782 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
783 mdio_delay();
784 }
785 /* Clear out extra bits. */
786 for (i = 2; i > 0; i--) {
787 iowrite8(MDIO_EnbIn, mdio_addr);
788 mdio_delay();
789 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
790 mdio_delay();
791 }
792 return;
793 }
794
795 static int mdio_wait_link(struct net_device *dev, int wait)
796 {
797 int bmsr;
798 int phy_id;
799 struct netdev_private *np;
800
801 np = netdev_priv(dev);
802 phy_id = np->phys[0];
803
804 do {
805 bmsr = mdio_read(dev, phy_id, MII_BMSR);
806 if (bmsr & 0x0004)
807 return 0;
808 mdelay(1);
809 } while (--wait > 0);
810 return -1;
811 }
812
813 static int netdev_open(struct net_device *dev)
814 {
815 struct netdev_private *np = netdev_priv(dev);
816 void __iomem *ioaddr = np->base;
817 unsigned long flags;
818 int i;
819
820 /* Do we need to reset the chip??? */
821
822 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
823 if (i)
824 return i;
825
826 if (netif_msg_ifup(np))
827 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
828 dev->name, dev->irq);
829 init_ring(dev);
830
831 iowrite32(np->rx_ring_dma, ioaddr + RxListPtr);
832 /* The Tx list pointer is written as packets are queued. */
833
834 /* Initialize other registers. */
835 __set_mac_addr(dev);
836 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
837 iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize);
838 #else
839 iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize);
840 #endif
841 if (dev->mtu > 2047)
842 iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl);
843
844 /* Configure the PCI bus bursts and FIFO thresholds. */
845
846 if (dev->if_port == 0)
847 dev->if_port = np->default_port;
848
849 spin_lock_init(&np->mcastlock);
850
851 set_rx_mode(dev);
852 iowrite16(0, ioaddr + IntrEnable);
853 iowrite16(0, ioaddr + DownCounter);
854 /* Set the chip to poll every N*320nsec. */
855 iowrite8(100, ioaddr + RxDMAPollPeriod);
856 iowrite8(127, ioaddr + TxDMAPollPeriod);
857 /* Fix DFE-580TX packet drop issue */
858 if (np->pci_dev->revision >= 0x14)
859 iowrite8(0x01, ioaddr + DebugCtrl1);
860 netif_start_queue(dev);
861
862 spin_lock_irqsave(&np->lock, flags);
863 reset_tx(dev);
864 spin_unlock_irqrestore(&np->lock, flags);
865
866 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
867
868 if (netif_msg_ifup(np))
869 printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
870 "MAC Control %x, %4.4x %4.4x.\n",
871 dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus),
872 ioread32(ioaddr + MACCtrl0),
873 ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0));
874
875 /* Set the timer to check for link beat. */
876 init_timer(&np->timer);
877 np->timer.expires = jiffies + 3*HZ;
878 np->timer.data = (unsigned long)dev;
879 np->timer.function = &netdev_timer; /* timer handler */
880 add_timer(&np->timer);
881
882 /* Enable interrupts by setting the interrupt mask. */
883 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
884
885 return 0;
886 }
887
888 static void check_duplex(struct net_device *dev)
889 {
890 struct netdev_private *np = netdev_priv(dev);
891 void __iomem *ioaddr = np->base;
892 int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
893 int negotiated = mii_lpa & np->mii_if.advertising;
894 int duplex;
895
896 /* Force media */
897 if (!np->an_enable || mii_lpa == 0xffff) {
898 if (np->mii_if.full_duplex)
899 iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex,
900 ioaddr + MACCtrl0);
901 return;
902 }
903
904 /* Autonegotiation */
905 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
906 if (np->mii_if.full_duplex != duplex) {
907 np->mii_if.full_duplex = duplex;
908 if (netif_msg_link(np))
909 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
910 "negotiated capability %4.4x.\n", dev->name,
911 duplex ? "full" : "half", np->phys[0], negotiated);
912 iowrite16(ioread16(ioaddr + MACCtrl0) | (duplex ? 0x20 : 0), ioaddr + MACCtrl0);
913 }
914 }
915
916 static void netdev_timer(unsigned long data)
917 {
918 struct net_device *dev = (struct net_device *)data;
919 struct netdev_private *np = netdev_priv(dev);
920 void __iomem *ioaddr = np->base;
921 int next_tick = 10*HZ;
922
923 if (netif_msg_timer(np)) {
924 printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
925 "Tx %x Rx %x.\n",
926 dev->name, ioread16(ioaddr + IntrEnable),
927 ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
928 }
929 check_duplex(dev);
930 np->timer.expires = jiffies + next_tick;
931 add_timer(&np->timer);
932 }
933
934 static void tx_timeout(struct net_device *dev)
935 {
936 struct netdev_private *np = netdev_priv(dev);
937 void __iomem *ioaddr = np->base;
938 unsigned long flag;
939
940 netif_stop_queue(dev);
941 tasklet_disable(&np->tx_tasklet);
942 iowrite16(0, ioaddr + IntrEnable);
943 printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x "
944 "TxFrameId %2.2x,"
945 " resetting...\n", dev->name, ioread8(ioaddr + TxStatus),
946 ioread8(ioaddr + TxFrameId));
947
948 {
949 int i;
950 for (i=0; i<TX_RING_SIZE; i++) {
951 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
952 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
953 le32_to_cpu(np->tx_ring[i].next_desc),
954 le32_to_cpu(np->tx_ring[i].status),
955 (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff,
956 le32_to_cpu(np->tx_ring[i].frag[0].addr),
957 le32_to_cpu(np->tx_ring[i].frag[0].length));
958 }
959 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
960 ioread32(np->base + TxListPtr),
961 netif_queue_stopped(dev));
962 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
963 np->cur_tx, np->cur_tx % TX_RING_SIZE,
964 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
965 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
966 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
967 }
968 spin_lock_irqsave(&np->lock, flag);
969
970 /* Stop and restart the chip's Tx processes . */
971 reset_tx(dev);
972 spin_unlock_irqrestore(&np->lock, flag);
973
974 dev->if_port = 0;
975
976 dev->trans_start = jiffies;
977 dev->stats.tx_errors++;
978 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
979 netif_wake_queue(dev);
980 }
981 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
982 tasklet_enable(&np->tx_tasklet);
983 }
984
985
986 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
987 static void init_ring(struct net_device *dev)
988 {
989 struct netdev_private *np = netdev_priv(dev);
990 int i;
991
992 np->cur_rx = np->cur_tx = 0;
993 np->dirty_rx = np->dirty_tx = 0;
994 np->cur_task = 0;
995
996 np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16);
997
998 /* Initialize all Rx descriptors. */
999 for (i = 0; i < RX_RING_SIZE; i++) {
1000 np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma +
1001 ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring));
1002 np->rx_ring[i].status = 0;
1003 np->rx_ring[i].frag[0].length = 0;
1004 np->rx_skbuff[i] = NULL;
1005 }
1006
1007 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1008 for (i = 0; i < RX_RING_SIZE; i++) {
1009 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1010 np->rx_skbuff[i] = skb;
1011 if (skb == NULL)
1012 break;
1013 skb->dev = dev; /* Mark as being used by this device. */
1014 skb_reserve(skb, 2); /* 16 byte align the IP header. */
1015 np->rx_ring[i].frag[0].addr = cpu_to_le32(
1016 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz,
1017 PCI_DMA_FROMDEVICE));
1018 np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
1019 }
1020 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1021
1022 for (i = 0; i < TX_RING_SIZE; i++) {
1023 np->tx_skbuff[i] = NULL;
1024 np->tx_ring[i].status = 0;
1025 }
1026 return;
1027 }
1028
1029 static void tx_poll (unsigned long data)
1030 {
1031 struct net_device *dev = (struct net_device *)data;
1032 struct netdev_private *np = netdev_priv(dev);
1033 unsigned head = np->cur_task % TX_RING_SIZE;
1034 struct netdev_desc *txdesc =
1035 &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE];
1036
1037 /* Chain the next pointer */
1038 for (; np->cur_tx - np->cur_task > 0; np->cur_task++) {
1039 int entry = np->cur_task % TX_RING_SIZE;
1040 txdesc = &np->tx_ring[entry];
1041 if (np->last_tx) {
1042 np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma +
1043 entry*sizeof(struct netdev_desc));
1044 }
1045 np->last_tx = txdesc;
1046 }
1047 /* Indicate the latest descriptor of tx ring */
1048 txdesc->status |= cpu_to_le32(DescIntrOnTx);
1049
1050 if (ioread32 (np->base + TxListPtr) == 0)
1051 iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc),
1052 np->base + TxListPtr);
1053 return;
1054 }
1055
1056 static netdev_tx_t
1057 start_tx (struct sk_buff *skb, struct net_device *dev)
1058 {
1059 struct netdev_private *np = netdev_priv(dev);
1060 struct netdev_desc *txdesc;
1061 unsigned entry;
1062
1063 /* Calculate the next Tx descriptor entry. */
1064 entry = np->cur_tx % TX_RING_SIZE;
1065 np->tx_skbuff[entry] = skb;
1066 txdesc = &np->tx_ring[entry];
1067
1068 txdesc->next_desc = 0;
1069 txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign);
1070 txdesc->frag[0].addr = cpu_to_le32 (pci_map_single (np->pci_dev, skb->data,
1071 skb->len,
1072 PCI_DMA_TODEVICE));
1073 txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag);
1074
1075 /* Increment cur_tx before tasklet_schedule() */
1076 np->cur_tx++;
1077 mb();
1078 /* Schedule a tx_poll() task */
1079 tasklet_schedule(&np->tx_tasklet);
1080
1081 /* On some architectures: explicitly flush cache lines here. */
1082 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1
1083 && !netif_queue_stopped(dev)) {
1084 /* do nothing */
1085 } else {
1086 netif_stop_queue (dev);
1087 }
1088 dev->trans_start = jiffies;
1089 if (netif_msg_tx_queued(np)) {
1090 printk (KERN_DEBUG
1091 "%s: Transmit frame #%d queued in slot %d.\n",
1092 dev->name, np->cur_tx, entry);
1093 }
1094 return NETDEV_TX_OK;
1095 }
1096
1097 /* Reset hardware tx and free all of tx buffers */
1098 static int
1099 reset_tx (struct net_device *dev)
1100 {
1101 struct netdev_private *np = netdev_priv(dev);
1102 void __iomem *ioaddr = np->base;
1103 struct sk_buff *skb;
1104 int i;
1105 int irq = in_interrupt();
1106
1107 /* Reset tx logic, TxListPtr will be cleaned */
1108 iowrite16 (TxDisable, ioaddr + MACCtrl1);
1109 sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
1110
1111 /* free all tx skbuff */
1112 for (i = 0; i < TX_RING_SIZE; i++) {
1113 np->tx_ring[i].next_desc = 0;
1114
1115 skb = np->tx_skbuff[i];
1116 if (skb) {
1117 pci_unmap_single(np->pci_dev,
1118 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1119 skb->len, PCI_DMA_TODEVICE);
1120 if (irq)
1121 dev_kfree_skb_irq (skb);
1122 else
1123 dev_kfree_skb (skb);
1124 np->tx_skbuff[i] = NULL;
1125 dev->stats.tx_dropped++;
1126 }
1127 }
1128 np->cur_tx = np->dirty_tx = 0;
1129 np->cur_task = 0;
1130
1131 np->last_tx = NULL;
1132 iowrite8(127, ioaddr + TxDMAPollPeriod);
1133
1134 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
1135 return 0;
1136 }
1137
1138 /* The interrupt handler cleans up after the Tx thread,
1139 and schedule a Rx thread work */
1140 static irqreturn_t intr_handler(int irq, void *dev_instance)
1141 {
1142 struct net_device *dev = (struct net_device *)dev_instance;
1143 struct netdev_private *np = netdev_priv(dev);
1144 void __iomem *ioaddr = np->base;
1145 int hw_frame_id;
1146 int tx_cnt;
1147 int tx_status;
1148 int handled = 0;
1149 int i;
1150
1151
1152 do {
1153 int intr_status = ioread16(ioaddr + IntrStatus);
1154 iowrite16(intr_status, ioaddr + IntrStatus);
1155
1156 if (netif_msg_intr(np))
1157 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1158 dev->name, intr_status);
1159
1160 if (!(intr_status & DEFAULT_INTR))
1161 break;
1162
1163 handled = 1;
1164
1165 if (intr_status & (IntrRxDMADone)) {
1166 iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
1167 ioaddr + IntrEnable);
1168 if (np->budget < 0)
1169 np->budget = RX_BUDGET;
1170 tasklet_schedule(&np->rx_tasklet);
1171 }
1172 if (intr_status & (IntrTxDone | IntrDrvRqst)) {
1173 tx_status = ioread16 (ioaddr + TxStatus);
1174 for (tx_cnt=32; tx_status & 0x80; --tx_cnt) {
1175 if (netif_msg_tx_done(np))
1176 printk
1177 ("%s: Transmit status is %2.2x.\n",
1178 dev->name, tx_status);
1179 if (tx_status & 0x1e) {
1180 if (netif_msg_tx_err(np))
1181 printk("%s: Transmit error status %4.4x.\n",
1182 dev->name, tx_status);
1183 dev->stats.tx_errors++;
1184 if (tx_status & 0x10)
1185 dev->stats.tx_fifo_errors++;
1186 if (tx_status & 0x08)
1187 dev->stats.collisions++;
1188 if (tx_status & 0x04)
1189 dev->stats.tx_fifo_errors++;
1190 if (tx_status & 0x02)
1191 dev->stats.tx_window_errors++;
1192
1193 /*
1194 ** This reset has been verified on
1195 ** DFE-580TX boards ! phdm@macqel.be.
1196 */
1197 if (tx_status & 0x10) { /* TxUnderrun */
1198 /* Restart Tx FIFO and transmitter */
1199 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
1200 /* No need to reset the Tx pointer here */
1201 }
1202 /* Restart the Tx. Need to make sure tx enabled */
1203 i = 10;
1204 do {
1205 iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
1206 if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
1207 break;
1208 mdelay(1);
1209 } while (--i);
1210 }
1211 /* Yup, this is a documentation bug. It cost me *hours*. */
1212 iowrite16 (0, ioaddr + TxStatus);
1213 if (tx_cnt < 0) {
1214 iowrite32(5000, ioaddr + DownCounter);
1215 break;
1216 }
1217 tx_status = ioread16 (ioaddr + TxStatus);
1218 }
1219 hw_frame_id = (tx_status >> 8) & 0xff;
1220 } else {
1221 hw_frame_id = ioread8(ioaddr + TxFrameId);
1222 }
1223
1224 if (np->pci_dev->revision >= 0x14) {
1225 spin_lock(&np->lock);
1226 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1227 int entry = np->dirty_tx % TX_RING_SIZE;
1228 struct sk_buff *skb;
1229 int sw_frame_id;
1230 sw_frame_id = (le32_to_cpu(
1231 np->tx_ring[entry].status) >> 2) & 0xff;
1232 if (sw_frame_id == hw_frame_id &&
1233 !(le32_to_cpu(np->tx_ring[entry].status)
1234 & 0x00010000))
1235 break;
1236 if (sw_frame_id == (hw_frame_id + 1) %
1237 TX_RING_SIZE)
1238 break;
1239 skb = np->tx_skbuff[entry];
1240 /* Free the original skb. */
1241 pci_unmap_single(np->pci_dev,
1242 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
1243 skb->len, PCI_DMA_TODEVICE);
1244 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1245 np->tx_skbuff[entry] = NULL;
1246 np->tx_ring[entry].frag[0].addr = 0;
1247 np->tx_ring[entry].frag[0].length = 0;
1248 }
1249 spin_unlock(&np->lock);
1250 } else {
1251 spin_lock(&np->lock);
1252 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1253 int entry = np->dirty_tx % TX_RING_SIZE;
1254 struct sk_buff *skb;
1255 if (!(le32_to_cpu(np->tx_ring[entry].status)
1256 & 0x00010000))
1257 break;
1258 skb = np->tx_skbuff[entry];
1259 /* Free the original skb. */
1260 pci_unmap_single(np->pci_dev,
1261 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
1262 skb->len, PCI_DMA_TODEVICE);
1263 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1264 np->tx_skbuff[entry] = NULL;
1265 np->tx_ring[entry].frag[0].addr = 0;
1266 np->tx_ring[entry].frag[0].length = 0;
1267 }
1268 spin_unlock(&np->lock);
1269 }
1270
1271 if (netif_queue_stopped(dev) &&
1272 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1273 /* The ring is no longer full, clear busy flag. */
1274 netif_wake_queue (dev);
1275 }
1276 /* Abnormal error summary/uncommon events handlers. */
1277 if (intr_status & (IntrPCIErr | LinkChange | StatsMax))
1278 netdev_error(dev, intr_status);
1279 } while (0);
1280 if (netif_msg_intr(np))
1281 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1282 dev->name, ioread16(ioaddr + IntrStatus));
1283 return IRQ_RETVAL(handled);
1284 }
1285
1286 static void rx_poll(unsigned long data)
1287 {
1288 struct net_device *dev = (struct net_device *)data;
1289 struct netdev_private *np = netdev_priv(dev);
1290 int entry = np->cur_rx % RX_RING_SIZE;
1291 int boguscnt = np->budget;
1292 void __iomem *ioaddr = np->base;
1293 int received = 0;
1294
1295 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1296 while (1) {
1297 struct netdev_desc *desc = &(np->rx_ring[entry]);
1298 u32 frame_status = le32_to_cpu(desc->status);
1299 int pkt_len;
1300
1301 if (--boguscnt < 0) {
1302 goto not_done;
1303 }
1304 if (!(frame_status & DescOwn))
1305 break;
1306 pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
1307 if (netif_msg_rx_status(np))
1308 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1309 frame_status);
1310 if (frame_status & 0x001f4000) {
1311 /* There was a error. */
1312 if (netif_msg_rx_err(np))
1313 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
1314 frame_status);
1315 dev->stats.rx_errors++;
1316 if (frame_status & 0x00100000)
1317 dev->stats.rx_length_errors++;
1318 if (frame_status & 0x00010000)
1319 dev->stats.rx_fifo_errors++;
1320 if (frame_status & 0x00060000)
1321 dev->stats.rx_frame_errors++;
1322 if (frame_status & 0x00080000)
1323 dev->stats.rx_crc_errors++;
1324 if (frame_status & 0x00100000) {
1325 printk(KERN_WARNING "%s: Oversized Ethernet frame,"
1326 " status %8.8x.\n",
1327 dev->name, frame_status);
1328 }
1329 } else {
1330 struct sk_buff *skb;
1331 #ifndef final_version
1332 if (netif_msg_rx_status(np))
1333 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1334 ", bogus_cnt %d.\n",
1335 pkt_len, boguscnt);
1336 #endif
1337 /* Check if the packet is long enough to accept without copying
1338 to a minimally-sized skbuff. */
1339 if (pkt_len < rx_copybreak
1340 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1341 skb_reserve(skb, 2); /* 16 byte align the IP header */
1342 pci_dma_sync_single_for_cpu(np->pci_dev,
1343 le32_to_cpu(desc->frag[0].addr),
1344 np->rx_buf_sz,
1345 PCI_DMA_FROMDEVICE);
1346
1347 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1348 pci_dma_sync_single_for_device(np->pci_dev,
1349 le32_to_cpu(desc->frag[0].addr),
1350 np->rx_buf_sz,
1351 PCI_DMA_FROMDEVICE);
1352 skb_put(skb, pkt_len);
1353 } else {
1354 pci_unmap_single(np->pci_dev,
1355 le32_to_cpu(desc->frag[0].addr),
1356 np->rx_buf_sz,
1357 PCI_DMA_FROMDEVICE);
1358 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1359 np->rx_skbuff[entry] = NULL;
1360 }
1361 skb->protocol = eth_type_trans(skb, dev);
1362 /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
1363 netif_rx(skb);
1364 }
1365 entry = (entry + 1) % RX_RING_SIZE;
1366 received++;
1367 }
1368 np->cur_rx = entry;
1369 refill_rx (dev);
1370 np->budget -= received;
1371 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
1372 return;
1373
1374 not_done:
1375 np->cur_rx = entry;
1376 refill_rx (dev);
1377 if (!received)
1378 received = 1;
1379 np->budget -= received;
1380 if (np->budget <= 0)
1381 np->budget = RX_BUDGET;
1382 tasklet_schedule(&np->rx_tasklet);
1383 return;
1384 }
1385
1386 static void refill_rx (struct net_device *dev)
1387 {
1388 struct netdev_private *np = netdev_priv(dev);
1389 int entry;
1390 int cnt = 0;
1391
1392 /* Refill the Rx ring buffers. */
1393 for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0;
1394 np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) {
1395 struct sk_buff *skb;
1396 entry = np->dirty_rx % RX_RING_SIZE;
1397 if (np->rx_skbuff[entry] == NULL) {
1398 skb = dev_alloc_skb(np->rx_buf_sz);
1399 np->rx_skbuff[entry] = skb;
1400 if (skb == NULL)
1401 break; /* Better luck next round. */
1402 skb->dev = dev; /* Mark as being used by this device. */
1403 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1404 np->rx_ring[entry].frag[0].addr = cpu_to_le32(
1405 pci_map_single(np->pci_dev, skb->data,
1406 np->rx_buf_sz, PCI_DMA_FROMDEVICE));
1407 }
1408 /* Perhaps we need not reset this field. */
1409 np->rx_ring[entry].frag[0].length =
1410 cpu_to_le32(np->rx_buf_sz | LastFrag);
1411 np->rx_ring[entry].status = 0;
1412 cnt++;
1413 }
1414 return;
1415 }
1416 static void netdev_error(struct net_device *dev, int intr_status)
1417 {
1418 struct netdev_private *np = netdev_priv(dev);
1419 void __iomem *ioaddr = np->base;
1420 u16 mii_ctl, mii_advertise, mii_lpa;
1421 int speed;
1422
1423 if (intr_status & LinkChange) {
1424 if (mdio_wait_link(dev, 10) == 0) {
1425 printk(KERN_INFO "%s: Link up\n", dev->name);
1426 if (np->an_enable) {
1427 mii_advertise = mdio_read(dev, np->phys[0],
1428 MII_ADVERTISE);
1429 mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
1430 mii_advertise &= mii_lpa;
1431 printk(KERN_INFO "%s: Link changed: ",
1432 dev->name);
1433 if (mii_advertise & ADVERTISE_100FULL) {
1434 np->speed = 100;
1435 printk("100Mbps, full duplex\n");
1436 } else if (mii_advertise & ADVERTISE_100HALF) {
1437 np->speed = 100;
1438 printk("100Mbps, half duplex\n");
1439 } else if (mii_advertise & ADVERTISE_10FULL) {
1440 np->speed = 10;
1441 printk("10Mbps, full duplex\n");
1442 } else if (mii_advertise & ADVERTISE_10HALF) {
1443 np->speed = 10;
1444 printk("10Mbps, half duplex\n");
1445 } else
1446 printk("\n");
1447
1448 } else {
1449 mii_ctl = mdio_read(dev, np->phys[0], MII_BMCR);
1450 speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
1451 np->speed = speed;
1452 printk(KERN_INFO "%s: Link changed: %dMbps ,",
1453 dev->name, speed);
1454 printk("%s duplex.\n",
1455 (mii_ctl & BMCR_FULLDPLX) ?
1456 "full" : "half");
1457 }
1458 check_duplex(dev);
1459 if (np->flowctrl && np->mii_if.full_duplex) {
1460 iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200,
1461 ioaddr + MulticastFilter1+2);
1462 iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl,
1463 ioaddr + MACCtrl0);
1464 }
1465 netif_carrier_on(dev);
1466 } else {
1467 printk(KERN_INFO "%s: Link down\n", dev->name);
1468 netif_carrier_off(dev);
1469 }
1470 }
1471 if (intr_status & StatsMax) {
1472 get_stats(dev);
1473 }
1474 if (intr_status & IntrPCIErr) {
1475 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1476 dev->name, intr_status);
1477 /* We must do a global reset of DMA to continue. */
1478 }
1479 }
1480
1481 static struct net_device_stats *get_stats(struct net_device *dev)
1482 {
1483 struct netdev_private *np = netdev_priv(dev);
1484 void __iomem *ioaddr = np->base;
1485 int i;
1486
1487 /* We should lock this segment of code for SMP eventually, although
1488 the vulnerability window is very small and statistics are
1489 non-critical. */
1490 /* The chip only need report frame silently dropped. */
1491 dev->stats.rx_missed_errors += ioread8(ioaddr + RxMissed);
1492 dev->stats.tx_packets += ioread16(ioaddr + TxFramesOK);
1493 dev->stats.rx_packets += ioread16(ioaddr + RxFramesOK);
1494 dev->stats.collisions += ioread8(ioaddr + StatsLateColl);
1495 dev->stats.collisions += ioread8(ioaddr + StatsMultiColl);
1496 dev->stats.collisions += ioread8(ioaddr + StatsOneColl);
1497 dev->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError);
1498 ioread8(ioaddr + StatsTxDefer);
1499 for (i = StatsTxDefer; i <= StatsMcastRx; i++)
1500 ioread8(ioaddr + i);
1501 dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow);
1502 dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16;
1503 dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow);
1504 dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16;
1505
1506 return &dev->stats;
1507 }
1508
1509 static void set_rx_mode(struct net_device *dev)
1510 {
1511 struct netdev_private *np = netdev_priv(dev);
1512 void __iomem *ioaddr = np->base;
1513 u16 mc_filter[4]; /* Multicast hash filter */
1514 u32 rx_mode;
1515 int i;
1516
1517 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1518 memset(mc_filter, 0xff, sizeof(mc_filter));
1519 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
1520 } else if ((dev->mc_count > multicast_filter_limit)
1521 || (dev->flags & IFF_ALLMULTI)) {
1522 /* Too many to match, or accept all multicasts. */
1523 memset(mc_filter, 0xff, sizeof(mc_filter));
1524 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1525 } else if (dev->mc_count) {
1526 struct dev_mc_list *mclist;
1527 int bit;
1528 int index;
1529 int crc;
1530 memset (mc_filter, 0, sizeof (mc_filter));
1531 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1532 i++, mclist = mclist->next) {
1533 crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1534 for (index=0, bit=0; bit < 6; bit++, crc <<= 1)
1535 if (crc & 0x80000000) index |= 1 << bit;
1536 mc_filter[index/16] |= (1 << (index % 16));
1537 }
1538 rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
1539 } else {
1540 iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1541 return;
1542 }
1543 if (np->mii_if.full_duplex && np->flowctrl)
1544 mc_filter[3] |= 0x0200;
1545
1546 for (i = 0; i < 4; i++)
1547 iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
1548 iowrite8(rx_mode, ioaddr + RxMode);
1549 }
1550
1551 static int __set_mac_addr(struct net_device *dev)
1552 {
1553 struct netdev_private *np = netdev_priv(dev);
1554 u16 addr16;
1555
1556 addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8));
1557 iowrite16(addr16, np->base + StationAddr);
1558 addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8));
1559 iowrite16(addr16, np->base + StationAddr+2);
1560 addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8));
1561 iowrite16(addr16, np->base + StationAddr+4);
1562 return 0;
1563 }
1564
1565 static int check_if_running(struct net_device *dev)
1566 {
1567 if (!netif_running(dev))
1568 return -EINVAL;
1569 return 0;
1570 }
1571
1572 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1573 {
1574 struct netdev_private *np = netdev_priv(dev);
1575 strcpy(info->driver, DRV_NAME);
1576 strcpy(info->version, DRV_VERSION);
1577 strcpy(info->bus_info, pci_name(np->pci_dev));
1578 }
1579
1580 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1581 {
1582 struct netdev_private *np = netdev_priv(dev);
1583 spin_lock_irq(&np->lock);
1584 mii_ethtool_gset(&np->mii_if, ecmd);
1585 spin_unlock_irq(&np->lock);
1586 return 0;
1587 }
1588
1589 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1590 {
1591 struct netdev_private *np = netdev_priv(dev);
1592 int res;
1593 spin_lock_irq(&np->lock);
1594 res = mii_ethtool_sset(&np->mii_if, ecmd);
1595 spin_unlock_irq(&np->lock);
1596 return res;
1597 }
1598
1599 static int nway_reset(struct net_device *dev)
1600 {
1601 struct netdev_private *np = netdev_priv(dev);
1602 return mii_nway_restart(&np->mii_if);
1603 }
1604
1605 static u32 get_link(struct net_device *dev)
1606 {
1607 struct netdev_private *np = netdev_priv(dev);
1608 return mii_link_ok(&np->mii_if);
1609 }
1610
1611 static u32 get_msglevel(struct net_device *dev)
1612 {
1613 struct netdev_private *np = netdev_priv(dev);
1614 return np->msg_enable;
1615 }
1616
1617 static void set_msglevel(struct net_device *dev, u32 val)
1618 {
1619 struct netdev_private *np = netdev_priv(dev);
1620 np->msg_enable = val;
1621 }
1622
1623 static const struct ethtool_ops ethtool_ops = {
1624 .begin = check_if_running,
1625 .get_drvinfo = get_drvinfo,
1626 .get_settings = get_settings,
1627 .set_settings = set_settings,
1628 .nway_reset = nway_reset,
1629 .get_link = get_link,
1630 .get_msglevel = get_msglevel,
1631 .set_msglevel = set_msglevel,
1632 };
1633
1634 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1635 {
1636 struct netdev_private *np = netdev_priv(dev);
1637 int rc;
1638
1639 if (!netif_running(dev))
1640 return -EINVAL;
1641
1642 spin_lock_irq(&np->lock);
1643 rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL);
1644 spin_unlock_irq(&np->lock);
1645
1646 return rc;
1647 }
1648
1649 static int netdev_close(struct net_device *dev)
1650 {
1651 struct netdev_private *np = netdev_priv(dev);
1652 void __iomem *ioaddr = np->base;
1653 struct sk_buff *skb;
1654 int i;
1655
1656 /* Wait and kill tasklet */
1657 tasklet_kill(&np->rx_tasklet);
1658 tasklet_kill(&np->tx_tasklet);
1659 np->cur_tx = 0;
1660 np->dirty_tx = 0;
1661 np->cur_task = 0;
1662 np->last_tx = NULL;
1663
1664 netif_stop_queue(dev);
1665
1666 if (netif_msg_ifdown(np)) {
1667 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
1668 "Rx %4.4x Int %2.2x.\n",
1669 dev->name, ioread8(ioaddr + TxStatus),
1670 ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus));
1671 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1672 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1673 }
1674
1675 /* Disable interrupts by clearing the interrupt mask. */
1676 iowrite16(0x0000, ioaddr + IntrEnable);
1677
1678 /* Disable Rx and Tx DMA for safely release resource */
1679 iowrite32(0x500, ioaddr + DMACtrl);
1680
1681 /* Stop the chip's Tx and Rx processes. */
1682 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1683
1684 for (i = 2000; i > 0; i--) {
1685 if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
1686 break;
1687 mdelay(1);
1688 }
1689
1690 iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
1691 ioaddr +ASICCtrl + 2);
1692
1693 for (i = 2000; i > 0; i--) {
1694 if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0)
1695 break;
1696 mdelay(1);
1697 }
1698
1699 #ifdef __i386__
1700 if (netif_msg_hw(np)) {
1701 printk(KERN_DEBUG " Tx ring at %8.8x:\n",
1702 (int)(np->tx_ring_dma));
1703 for (i = 0; i < TX_RING_SIZE; i++)
1704 printk(KERN_DEBUG " #%d desc. %4.4x %8.8x %8.8x.\n",
1705 i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
1706 np->tx_ring[i].frag[0].length);
1707 printk(KERN_DEBUG " Rx ring %8.8x:\n",
1708 (int)(np->rx_ring_dma));
1709 for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
1710 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1711 i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
1712 np->rx_ring[i].frag[0].length);
1713 }
1714 }
1715 #endif /* __i386__ debugging only */
1716
1717 free_irq(dev->irq, dev);
1718
1719 del_timer_sync(&np->timer);
1720
1721 /* Free all the skbuffs in the Rx queue. */
1722 for (i = 0; i < RX_RING_SIZE; i++) {
1723 np->rx_ring[i].status = 0;
1724 skb = np->rx_skbuff[i];
1725 if (skb) {
1726 pci_unmap_single(np->pci_dev,
1727 le32_to_cpu(np->rx_ring[i].frag[0].addr),
1728 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1729 dev_kfree_skb(skb);
1730 np->rx_skbuff[i] = NULL;
1731 }
1732 np->rx_ring[i].frag[0].addr = cpu_to_le32(0xBADF00D0); /* poison */
1733 }
1734 for (i = 0; i < TX_RING_SIZE; i++) {
1735 np->tx_ring[i].next_desc = 0;
1736 skb = np->tx_skbuff[i];
1737 if (skb) {
1738 pci_unmap_single(np->pci_dev,
1739 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1740 skb->len, PCI_DMA_TODEVICE);
1741 dev_kfree_skb(skb);
1742 np->tx_skbuff[i] = NULL;
1743 }
1744 }
1745
1746 return 0;
1747 }
1748
1749 static void __devexit sundance_remove1 (struct pci_dev *pdev)
1750 {
1751 struct net_device *dev = pci_get_drvdata(pdev);
1752
1753 if (dev) {
1754 struct netdev_private *np = netdev_priv(dev);
1755
1756 unregister_netdev(dev);
1757 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
1758 np->rx_ring_dma);
1759 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
1760 np->tx_ring_dma);
1761 pci_iounmap(pdev, np->base);
1762 pci_release_regions(pdev);
1763 free_netdev(dev);
1764 pci_set_drvdata(pdev, NULL);
1765 }
1766 }
1767
1768 static struct pci_driver sundance_driver = {
1769 .name = DRV_NAME,
1770 .id_table = sundance_pci_tbl,
1771 .probe = sundance_probe1,
1772 .remove = __devexit_p(sundance_remove1),
1773 };
1774
1775 static int __init sundance_init(void)
1776 {
1777 /* when a module, this is printed whether or not devices are found in probe */
1778 #ifdef MODULE
1779 printk(version);
1780 #endif
1781 return pci_register_driver(&sundance_driver);
1782 }
1783
1784 static void __exit sundance_exit(void)
1785 {
1786 pci_unregister_driver(&sundance_driver);
1787 }
1788
1789 module_init(sundance_init);
1790 module_exit(sundance_exit);
1791
1792
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