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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / wireless / b43 / phy_lp.c
blob1e318d815a5b97b4a98d6c66304e2a2e65dcd439
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11a/g LP-PHY driver
5
6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
7 Copyright (c) 2009 Gábor Stefanik <netrolller.3d@gmail.com>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24 */
25
26 #include "b43.h"
27 #include "main.h"
28 #include "phy_lp.h"
29 #include "phy_common.h"
30 #include "tables_lpphy.h"
31
32
33 static inline u16 channel2freq_lp(u8 channel)
34 {
35 if (channel < 14)
36 return (2407 + 5 * channel);
37 else if (channel == 14)
38 return 2484;
39 else if (channel < 184)
40 return (5000 + 5 * channel);
41 else
42 return (4000 + 5 * channel);
43 }
44
45 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
46 {
47 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
48 return 1;
49 return 36;
50 }
51
52 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
53 {
54 struct b43_phy_lp *lpphy;
55
56 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
57 if (!lpphy)
58 return -ENOMEM;
59 dev->phy.lp = lpphy;
60
61 return 0;
62 }
63
64 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
65 {
66 struct b43_phy *phy = &dev->phy;
67 struct b43_phy_lp *lpphy = phy->lp;
68
69 memset(lpphy, 0, sizeof(*lpphy));
70
71 //TODO
72 }
73
74 static void b43_lpphy_op_free(struct b43_wldev *dev)
75 {
76 struct b43_phy_lp *lpphy = dev->phy.lp;
77
78 kfree(lpphy);
79 dev->phy.lp = NULL;
80 }
81
82 static void lpphy_read_band_sprom(struct b43_wldev *dev)
83 {
84 struct b43_phy_lp *lpphy = dev->phy.lp;
85 struct ssb_bus *bus = dev->dev->bus;
86 u16 cckpo, maxpwr;
87 u32 ofdmpo;
88 int i;
89
90 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
91 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
92 lpphy->bx_arch = bus->sprom.bxa2g;
93 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
94 lpphy->rssi_vf = bus->sprom.rssismf2g;
95 lpphy->rssi_vc = bus->sprom.rssismc2g;
96 lpphy->rssi_gs = bus->sprom.rssisav2g;
97 lpphy->txpa[0] = bus->sprom.pa0b0;
98 lpphy->txpa[1] = bus->sprom.pa0b1;
99 lpphy->txpa[2] = bus->sprom.pa0b2;
100 maxpwr = bus->sprom.maxpwr_bg;
101 lpphy->max_tx_pwr_med_band = maxpwr;
102 cckpo = bus->sprom.cck2gpo;
103 ofdmpo = bus->sprom.ofdm2gpo;
104 if (cckpo) {
105 for (i = 0; i < 4; i++) {
106 lpphy->tx_max_rate[i] =
107 maxpwr - (ofdmpo & 0xF) * 2;
108 ofdmpo >>= 4;
109 }
110 ofdmpo = bus->sprom.ofdm2gpo;
111 for (i = 4; i < 15; i++) {
112 lpphy->tx_max_rate[i] =
113 maxpwr - (ofdmpo & 0xF) * 2;
114 ofdmpo >>= 4;
115 }
116 } else {
117 ofdmpo &= 0xFF;
118 for (i = 0; i < 4; i++)
119 lpphy->tx_max_rate[i] = maxpwr;
120 for (i = 4; i < 15; i++)
121 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
122 }
123 } else { /* 5GHz */
124 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
125 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
126 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
127 lpphy->bx_arch = bus->sprom.bxa5g;
128 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
129 lpphy->rssi_vf = bus->sprom.rssismf5g;
130 lpphy->rssi_vc = bus->sprom.rssismc5g;
131 lpphy->rssi_gs = bus->sprom.rssisav5g;
132 lpphy->txpa[0] = bus->sprom.pa1b0;
133 lpphy->txpa[1] = bus->sprom.pa1b1;
134 lpphy->txpa[2] = bus->sprom.pa1b2;
135 lpphy->txpal[0] = bus->sprom.pa1lob0;
136 lpphy->txpal[1] = bus->sprom.pa1lob1;
137 lpphy->txpal[2] = bus->sprom.pa1lob2;
138 lpphy->txpah[0] = bus->sprom.pa1hib0;
139 lpphy->txpah[1] = bus->sprom.pa1hib1;
140 lpphy->txpah[2] = bus->sprom.pa1hib2;
141 maxpwr = bus->sprom.maxpwr_al;
142 ofdmpo = bus->sprom.ofdm5glpo;
143 lpphy->max_tx_pwr_low_band = maxpwr;
144 for (i = 4; i < 12; i++) {
145 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
146 ofdmpo >>= 4;
147 }
148 maxpwr = bus->sprom.maxpwr_a;
149 ofdmpo = bus->sprom.ofdm5gpo;
150 lpphy->max_tx_pwr_med_band = maxpwr;
151 for (i = 4; i < 12; i++) {
152 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
153 ofdmpo >>= 4;
154 }
155 maxpwr = bus->sprom.maxpwr_ah;
156 ofdmpo = bus->sprom.ofdm5ghpo;
157 lpphy->max_tx_pwr_hi_band = maxpwr;
158 for (i = 4; i < 12; i++) {
159 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
160 ofdmpo >>= 4;
161 }
162 }
163 }
164
165 static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
166 {
167 struct b43_phy_lp *lpphy = dev->phy.lp;
168 u16 temp[3];
169 u16 isolation;
170
171 B43_WARN_ON(dev->phy.rev >= 2);
172
173 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
174 isolation = lpphy->tx_isolation_med_band;
175 else if (freq <= 5320)
176 isolation = lpphy->tx_isolation_low_band;
177 else if (freq <= 5700)
178 isolation = lpphy->tx_isolation_med_band;
179 else
180 isolation = lpphy->tx_isolation_hi_band;
181
182 temp[0] = ((isolation - 26) / 12) << 12;
183 temp[1] = temp[0] + 0x1000;
184 temp[2] = temp[0] + 0x2000;
185
186 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
187 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
188 }
189
190 static void lpphy_table_init(struct b43_wldev *dev)
191 {
192 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
193
194 if (dev->phy.rev < 2)
195 lpphy_rev0_1_table_init(dev);
196 else
197 lpphy_rev2plus_table_init(dev);
198
199 lpphy_init_tx_gain_table(dev);
200
201 if (dev->phy.rev < 2)
202 lpphy_adjust_gain_table(dev, freq);
203 }
204
205 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
206 {
207 struct ssb_bus *bus = dev->dev->bus;
208 struct b43_phy_lp *lpphy = dev->phy.lp;
209 u16 tmp, tmp2;
210
211 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
212 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
213 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
214 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
215 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
216 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
217 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
218 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
219 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
220 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
221 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
222 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
223 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
224 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
225 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
227 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180);
228 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00);
229 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
230 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
231 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
232 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
233 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
234 0xFF00, lpphy->rx_pwr_offset);
235 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
236 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
237 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
238 ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28);
239 ssb_pmu_set_ldo_paref(&bus->chipco, true);
240 if (dev->phy.rev == 0) {
241 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
242 0xFFCF, 0x0010);
243 }
244 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
245 } else {
246 ssb_pmu_set_ldo_paref(&bus->chipco, false);
247 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
248 0xFFCF, 0x0020);
249 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
250 }
251 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
252 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
253 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
254 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
255 else
256 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
257 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
258 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
259 0xFFF9, (lpphy->bx_arch << 1));
260 if (dev->phy.rev == 1 &&
261 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
262 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
263 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
264 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
265 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
266 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
277 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
278 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
279 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
280 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
281 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
282 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
283 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
289 } else if (dev->phy.rev == 1 ||
290 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
292 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
293 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
299 } else {
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
302 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
307 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
308 }
309 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
310 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
311 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
312 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
313 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
314 }
315 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
316 (bus->chip_id == 0x5354) &&
317 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
318 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
319 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
320 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
321 //FIXME the Broadcom driver caches & delays this HF write!
322 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
323 }
324 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
325 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
326 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
327 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
328 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
329 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
330 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
331 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
332 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
333 } else { /* 5GHz */
334 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
335 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
336 }
337 if (dev->phy.rev == 1) {
338 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
339 tmp2 = (tmp & 0x03E0) >> 5;
340 tmp2 |= tmp2 << 5;
341 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
342 tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH);
343 tmp2 = (tmp & 0x1F00) >> 8;
344 tmp2 |= tmp2 << 5;
345 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
346 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
347 tmp2 = tmp & 0x00FF;
348 tmp2 |= tmp << 8;
349 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
350 }
351 }
352
353 static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
354 {
355 static const u16 addr[] = {
356 B43_PHY_OFDM(0xC1),
357 B43_PHY_OFDM(0xC2),
358 B43_PHY_OFDM(0xC3),
359 B43_PHY_OFDM(0xC4),
360 B43_PHY_OFDM(0xC5),
361 B43_PHY_OFDM(0xC6),
362 B43_PHY_OFDM(0xC7),
363 B43_PHY_OFDM(0xC8),
364 B43_PHY_OFDM(0xCF),
365 };
366
367 static const u16 coefs[] = {
368 0xDE5E, 0xE832, 0xE331, 0x4D26,
369 0x0026, 0x1420, 0x0020, 0xFE08,
370 0x0008,
371 };
372
373 struct b43_phy_lp *lpphy = dev->phy.lp;
374 int i;
375
376 for (i = 0; i < ARRAY_SIZE(addr); i++) {
377 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
378 b43_phy_write(dev, addr[i], coefs[i]);
379 }
380 }
381
382 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
383 {
384 static const u16 addr[] = {
385 B43_PHY_OFDM(0xC1),
386 B43_PHY_OFDM(0xC2),
387 B43_PHY_OFDM(0xC3),
388 B43_PHY_OFDM(0xC4),
389 B43_PHY_OFDM(0xC5),
390 B43_PHY_OFDM(0xC6),
391 B43_PHY_OFDM(0xC7),
392 B43_PHY_OFDM(0xC8),
393 B43_PHY_OFDM(0xCF),
394 };
395
396 struct b43_phy_lp *lpphy = dev->phy.lp;
397 int i;
398
399 for (i = 0; i < ARRAY_SIZE(addr); i++)
400 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
401 }
402
403 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
404 {
405 struct ssb_bus *bus = dev->dev->bus;
406 struct b43_phy_lp *lpphy = dev->phy.lp;
407
408 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
409 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
410 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
411 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
412 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
413 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
414 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
415 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
416 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
417 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
418 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
419 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
420 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
421 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
422 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
423 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
424 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
425 if (bus->boardinfo.rev >= 0x18) {
426 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
427 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
428 } else {
429 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
430 }
431 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
432 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
433 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
434 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
435 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
436 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
437 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
438 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
439 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
440 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
441 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
442 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
443 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
444 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
445 } else {
446 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
447 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
448 }
449 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
450 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
451 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
452 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
454 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
455 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
456 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
457 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
458 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
459
460 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
461 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
462 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
463 }
464
465 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
466 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
467 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
468 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
469 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
470 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
471 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
472 } else /* 5GHz */
473 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
474
475 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
476 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
477 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
478 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
479 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
480 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
481 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
482 0x2000 | ((u16)lpphy->rssi_gs << 10) |
483 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
484
485 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
486 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
487 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
488 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
489 }
490
491 lpphy_save_dig_flt_state(dev);
492 }
493
494 static void lpphy_baseband_init(struct b43_wldev *dev)
495 {
496 lpphy_table_init(dev);
497 if (dev->phy.rev >= 2)
498 lpphy_baseband_rev2plus_init(dev);
499 else
500 lpphy_baseband_rev0_1_init(dev);
501 }
502
503 struct b2062_freqdata {
504 u16 freq;
505 u8 data[6];
506 };
507
508 /* Initialize the 2062 radio. */
509 static void lpphy_2062_init(struct b43_wldev *dev)
510 {
511 struct b43_phy_lp *lpphy = dev->phy.lp;
512 struct ssb_bus *bus = dev->dev->bus;
513 u32 crystalfreq, tmp, ref;
514 unsigned int i;
515 const struct b2062_freqdata *fd = NULL;
516
517 static const struct b2062_freqdata freqdata_tab[] = {
518 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
519 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
520 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
521 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
522 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
523 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
524 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
525 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
526 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
527 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
528 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
529 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
530 };
531
532 b2062_upload_init_table(dev);
533
534 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
535 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
536 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
537 b43_radio_write(dev, B2062_N_TX_CTL6, 0);
538 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
539 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
540 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
541 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
542 if (dev->phy.rev > 0) {
543 b43_radio_write(dev, B2062_S_BG_CTL1,
544 (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
545 }
546 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
547 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
548 else
549 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
550
551 /* Get the crystal freq, in Hz. */
552 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
553
554 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
555 B43_WARN_ON(crystalfreq == 0);
556
557 if (crystalfreq <= 30000000) {
558 lpphy->pdiv = 1;
559 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
560 } else {
561 lpphy->pdiv = 2;
562 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
563 }
564
565 tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
566 (2 * crystalfreq)) - 8) & 0xFF;
567 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
568
569 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
570 (32000000 * lpphy->pdiv)) - 1) & 0xFF;
571 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
572
573 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
574 (2000000 * lpphy->pdiv)) - 1) & 0xFF;
575 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
576
577 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
578 ref &= 0xFFFF;
579 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
580 if (ref < freqdata_tab[i].freq) {
581 fd = &freqdata_tab[i];
582 break;
583 }
584 }
585 if (!fd)
586 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
587 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
588 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
589
590 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
591 ((u16)(fd->data[1]) << 4) | fd->data[0]);
592 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
593 ((u16)(fd->data[3]) << 4) | fd->data[2]);
594 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
595 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
596 }
597
598 /* Initialize the 2063 radio. */
599 static void lpphy_2063_init(struct b43_wldev *dev)
600 {
601 b2063_upload_init_table(dev);
602 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
603 b43_radio_set(dev, B2063_COMM8, 0x38);
604 b43_radio_write(dev, B2063_REG_SP1, 0x56);
605 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
606 b43_radio_write(dev, B2063_PA_SP7, 0);
607 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
608 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
609 if (dev->phy.rev == 2) {
610 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
611 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
612 b43_radio_write(dev, B2063_PA_SP2, 0x18);
613 } else {
614 b43_radio_write(dev, B2063_PA_SP3, 0x20);
615 b43_radio_write(dev, B2063_PA_SP2, 0x20);
616 }
617 }
618
619 struct lpphy_stx_table_entry {
620 u16 phy_offset;
621 u16 phy_shift;
622 u16 rf_addr;
623 u16 rf_shift;
624 u16 mask;
625 };
626
627 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
628 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
629 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
630 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
631 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
632 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
633 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
634 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
635 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
636 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
637 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
638 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
639 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
640 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
641 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
642 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
643 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
644 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
645 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
646 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
647 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
648 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
649 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
650 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
651 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
652 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
653 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
654 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
655 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
656 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
657 };
658
659 static void lpphy_sync_stx(struct b43_wldev *dev)
660 {
661 const struct lpphy_stx_table_entry *e;
662 unsigned int i;
663 u16 tmp;
664
665 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
666 e = &lpphy_stx_table[i];
667 tmp = b43_radio_read(dev, e->rf_addr);
668 tmp >>= e->rf_shift;
669 tmp <<= e->phy_shift;
670 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
671 ~(e->mask << e->phy_shift), tmp);
672 }
673 }
674
675 static void lpphy_radio_init(struct b43_wldev *dev)
676 {
677 /* The radio is attached through the 4wire bus. */
678 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
679 udelay(1);
680 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
681 udelay(1);
682
683 if (dev->phy.radio_ver == 0x2062) {
684 lpphy_2062_init(dev);
685 } else {
686 lpphy_2063_init(dev);
687 lpphy_sync_stx(dev);
688 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
689 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
690 if (dev->dev->bus->chip_id == 0x4325) {
691 // TODO SSB PMU recalibration
692 }
693 }
694 }
695
696 struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
697
698 static void lpphy_set_rc_cap(struct b43_wldev *dev)
699 {
700 struct b43_phy_lp *lpphy = dev->phy.lp;
701
702 u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
703
704 if (dev->phy.rev == 1) //FIXME check channel 14!
705 rc_cap = min_t(u8, rc_cap + 5, 15);
706
707 b43_radio_write(dev, B2062_N_RXBB_CALIB2,
708 max_t(u8, lpphy->rc_cap - 4, 0x80));
709 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
710 b43_radio_write(dev, B2062_S_RXG_CNT16,
711 ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
712 }
713
714 static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
715 {
716 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
717 }
718
719 static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
720 {
721 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
722 }
723
724 static void lpphy_set_deaf(struct b43_wldev *dev, bool user)
725 {
726 struct b43_phy_lp *lpphy = dev->phy.lp;
727
728 if (user)
729 lpphy->crs_usr_disable = 1;
730 else
731 lpphy->crs_sys_disable = 1;
732 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
733 }
734
735 static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
736 {
737 struct b43_phy_lp *lpphy = dev->phy.lp;
738
739 if (user)
740 lpphy->crs_usr_disable = 0;
741 else
742 lpphy->crs_sys_disable = 0;
743
744 if (!lpphy->crs_usr_disable && !lpphy->crs_sys_disable) {
745 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
746 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
747 0xFF1F, 0x60);
748 else
749 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
750 0xFF1F, 0x20);
751 }
752 }
753
754 static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
755 {
756 lpphy_set_deaf(dev, user);
757 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
758 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
759 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
760 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
761 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
762 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
763 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
764 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
765 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
766 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
767 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
768 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
769 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
770 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
771 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
772 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
773 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
774 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
775 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
776 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
777 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
778 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
779 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
780 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
781 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
782 }
783
784 static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
785 {
786 lpphy_clear_deaf(dev, user);
787 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
788 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
789 }
790
791 struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
792
793 static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
794 {
795 struct lpphy_tx_gains gains;
796 u16 tmp;
797
798 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
799 if (dev->phy.rev < 2) {
800 tmp = b43_phy_read(dev,
801 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
802 gains.gm = tmp & 0x0007;
803 gains.pga = (tmp & 0x0078) >> 3;
804 gains.pad = (tmp & 0x780) >> 7;
805 } else {
806 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
807 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
808 gains.gm = tmp & 0xFF;
809 gains.pga = (tmp >> 8) & 0xFF;
810 }
811
812 return gains;
813 }
814
815 static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
816 {
817 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
818 ctl |= dac << 7;
819 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
820 }
821
822 static void lpphy_set_tx_gains(struct b43_wldev *dev,
823 struct lpphy_tx_gains gains)
824 {
825 u16 rf_gain, pa_gain;
826
827 if (dev->phy.rev < 2) {
828 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
829 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
830 0xF800, rf_gain);
831 } else {
832 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0;
833 pa_gain <<= 2;
834 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
835 (gains.pga << 8) | gains.gm);
836 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
837 0x8000, gains.pad | pa_gain);
838 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
839 (gains.pga << 8) | gains.gm);
840 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
841 0x8000, gains.pad | pa_gain);
842 }
843 lpphy_set_dac_gain(dev, gains.dac);
844 if (dev->phy.rev < 2) {
845 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
846 } else {
847 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
848 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
849 }
850 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
851 }
852
853 static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
854 {
855 u16 trsw = gain & 0x1;
856 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
857 u16 ext_lna = (gain & 2) >> 1;
858
859 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
860 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
861 0xFBFF, ext_lna << 10);
862 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
863 0xF7FF, ext_lna << 11);
864 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
865 }
866
867 static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
868 {
869 u16 low_gain = gain & 0xFFFF;
870 u16 high_gain = (gain >> 16) & 0xF;
871 u16 ext_lna = (gain >> 21) & 0x1;
872 u16 trsw = ~(gain >> 20) & 0x1;
873 u16 tmp;
874
875 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
876 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
877 0xFDFF, ext_lna << 9);
878 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
879 0xFBFF, ext_lna << 10);
880 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
881 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
882 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
883 tmp = (gain >> 2) & 0x3;
884 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
885 0xE7FF, tmp<<11);
886 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
887 }
888 }
889
890 static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
891 {
892 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
893 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
894 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
895 if (dev->phy.rev >= 2) {
896 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
897 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
898 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
899 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
900 }
901 } else {
902 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
903 }
904 }
905
906 static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
907 {
908 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
909 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
910 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
911 if (dev->phy.rev >= 2) {
912 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
913 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
914 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
915 b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
916 }
917 } else {
918 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
919 }
920 }
921
922 static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
923 {
924 if (dev->phy.rev < 2)
925 lpphy_rev0_1_set_rx_gain(dev, gain);
926 else
927 lpphy_rev2plus_set_rx_gain(dev, gain);
928 lpphy_enable_rx_gain_override(dev);
929 }
930
931 static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
932 {
933 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
934 lpphy_set_rx_gain(dev, gain);
935 }
936
937 static void lpphy_stop_ddfs(struct b43_wldev *dev)
938 {
939 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
940 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
941 }
942
943 static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
944 int incr1, int incr2, int scale_idx)
945 {
946 lpphy_stop_ddfs(dev);
947 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
948 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
949 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
950 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
951 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
952 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
953 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
954 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
955 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
956 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20);
957 }
958
959 static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
960 struct lpphy_iq_est *iq_est)
961 {
962 int i;
963
964 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
965 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
966 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
967 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
968 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200);
969
970 for (i = 0; i < 500; i++) {
971 if (!(b43_phy_read(dev,
972 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
973 break;
974 msleep(1);
975 }
976
977 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
978 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
979 return false;
980 }
981
982 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
983 iq_est->iq_prod <<= 16;
984 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
985
986 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
987 iq_est->i_pwr <<= 16;
988 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
989
990 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
991 iq_est->q_pwr <<= 16;
992 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
993
994 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
995 return true;
996 }
997
998 static int lpphy_loopback(struct b43_wldev *dev)
999 {
1000 struct lpphy_iq_est iq_est;
1001 int i, index = -1;
1002 u32 tmp;
1003
1004 memset(&iq_est, 0, sizeof(iq_est));
1005
1006 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
1007 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
1008 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
1009 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1010 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
1011 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
1012 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
1013 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
1014 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
1015 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
1016 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
1017 for (i = 0; i < 32; i++) {
1018 lpphy_set_rx_gain_by_index(dev, i);
1019 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
1020 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1021 continue;
1022 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
1023 if ((tmp > 4000) && (tmp < 10000)) {
1024 index = i;
1025 break;
1026 }
1027 }
1028 lpphy_stop_ddfs(dev);
1029 return index;
1030 }
1031
1032 /* Fixed-point division algorithm using only integer math. */
1033 static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1034 {
1035 u32 quotient, remainder;
1036
1037 if (divisor == 0)
1038 return 0;
1039
1040 quotient = dividend / divisor;
1041 remainder = dividend % divisor;
1042
1043 while (precision > 0) {
1044 quotient <<= 1;
1045 if (remainder << 1 >= divisor) {
1046 quotient++;
1047 remainder = (remainder << 1) - divisor;
1048 }
1049 precision--;
1050 }
1051
1052 if (remainder << 1 >= divisor)
1053 quotient++;
1054
1055 return quotient;
1056 }
1057
1058 /* Read the TX power control mode from hardware. */
1059 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1060 {
1061 struct b43_phy_lp *lpphy = dev->phy.lp;
1062 u16 ctl;
1063
1064 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1065 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1066 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1067 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1068 break;
1069 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1070 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1071 break;
1072 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1073 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1074 break;
1075 default:
1076 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1077 B43_WARN_ON(1);
1078 break;
1079 }
1080 }
1081
1082 /* Set the TX power control mode in hardware. */
1083 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1084 {
1085 struct b43_phy_lp *lpphy = dev->phy.lp;
1086 u16 ctl;
1087
1088 switch (lpphy->txpctl_mode) {
1089 case B43_LPPHY_TXPCTL_OFF:
1090 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1091 break;
1092 case B43_LPPHY_TXPCTL_HW:
1093 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1094 break;
1095 case B43_LPPHY_TXPCTL_SW:
1096 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1097 break;
1098 default:
1099 ctl = 0;
1100 B43_WARN_ON(1);
1101 }
1102 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1103 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1104 }
1105
1106 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1107 enum b43_lpphy_txpctl_mode mode)
1108 {
1109 struct b43_phy_lp *lpphy = dev->phy.lp;
1110 enum b43_lpphy_txpctl_mode oldmode;
1111
1112 lpphy_read_tx_pctl_mode_from_hardware(dev);
1113 oldmode = lpphy->txpctl_mode;
1114 if (oldmode == mode)
1115 return;
1116 lpphy->txpctl_mode = mode;
1117
1118 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1119 //TODO Update TX Power NPT
1120 //TODO Clear all TX Power offsets
1121 } else {
1122 if (mode == B43_LPPHY_TXPCTL_HW) {
1123 //TODO Recalculate target TX power
1124 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1125 0xFF80, lpphy->tssi_idx);
1126 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1127 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1128 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1129 //TODO Disable TX gain override
1130 lpphy->tx_pwr_idx_over = -1;
1131 }
1132 }
1133 if (dev->phy.rev >= 2) {
1134 if (mode == B43_LPPHY_TXPCTL_HW)
1135 b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2);
1136 else
1137 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD);
1138 }
1139 lpphy_write_tx_pctl_mode_to_hardware(dev);
1140 }
1141
1142 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1143 unsigned int new_channel);
1144
1145 static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1146 {
1147 struct b43_phy_lp *lpphy = dev->phy.lp;
1148 struct lpphy_iq_est iq_est;
1149 struct lpphy_tx_gains tx_gains;
1150 static const u32 ideal_pwr_table[21] = {
1151 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1152 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1153 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1154 0x0004c, 0x0002c, 0x0001a,
1155 };
1156 bool old_txg_ovr;
1157 u8 old_bbmult;
1158 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1159 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1160 enum b43_lpphy_txpctl_mode old_txpctl;
1161 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1162 int loopback, i, j, inner_sum, err;
1163
1164 memset(&iq_est, 0, sizeof(iq_est));
1165
1166 err = b43_lpphy_op_switch_channel(dev, 7);
1167 if (err) {
1168 b43dbg(dev->wl,
1169 "RC calib: Failed to switch to channel 7, error = %d\n",
1170 err);
1171 }
1172 old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40);
1173 old_bbmult = lpphy_get_bb_mult(dev);
1174 if (old_txg_ovr)
1175 tx_gains = lpphy_get_tx_gains(dev);
1176 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1177 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1178 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1179 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1180 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1181 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1182 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1183 lpphy_read_tx_pctl_mode_from_hardware(dev);
1184 old_txpctl = lpphy->txpctl_mode;
1185
1186 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1187 lpphy_disable_crs(dev, true);
1188 loopback = lpphy_loopback(dev);
1189 if (loopback == -1)
1190 goto finish;
1191 lpphy_set_rx_gain_by_index(dev, loopback);
1192 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1193 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1194 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1195 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1196 for (i = 128; i <= 159; i++) {
1197 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1198 inner_sum = 0;
1199 for (j = 5; j <= 25; j++) {
1200 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1201 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1202 goto finish;
1203 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1204 if (j == 5)
1205 tmp = mean_sq_pwr;
1206 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1207 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1208 mean_sq_pwr = ideal_pwr - normal_pwr;
1209 mean_sq_pwr *= mean_sq_pwr;
1210 inner_sum += mean_sq_pwr;
1211 if ((i == 128) || (inner_sum < mean_sq_pwr_min)) {
1212 lpphy->rc_cap = i;
1213 mean_sq_pwr_min = inner_sum;
1214 }
1215 }
1216 }
1217 lpphy_stop_ddfs(dev);
1218
1219 finish:
1220 lpphy_restore_crs(dev, true);
1221 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1222 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1223 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1224 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1225 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1226 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1227 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1228
1229 lpphy_set_bb_mult(dev, old_bbmult);
1230 if (old_txg_ovr) {
1231 /*
1232 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1233 * illogical. According to lwfinger, vendor driver v4.150.10.5
1234 * has a Set here, while v4.174.64.19 has a Get - regression in
1235 * the vendor driver? This should be tested this once the code
1236 * is testable.
1237 */
1238 lpphy_set_tx_gains(dev, tx_gains);
1239 }
1240 lpphy_set_tx_power_control(dev, old_txpctl);
1241 if (lpphy->rc_cap)
1242 lpphy_set_rc_cap(dev);
1243 }
1244
1245 static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1246 {
1247 struct ssb_bus *bus = dev->dev->bus;
1248 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1249 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1250 int i;
1251
1252 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1253 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1254 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1255 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1256 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1257 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1258 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1259 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1260 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1261
1262 for (i = 0; i < 10000; i++) {
1263 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1264 break;
1265 msleep(1);
1266 }
1267
1268 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1269 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1270
1271 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1272
1273 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1274 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1275 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1276 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1277 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1278
1279 if (crystal_freq == 24000000) {
1280 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1281 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1282 } else {
1283 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1284 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1285 }
1286
1287 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1288
1289 for (i = 0; i < 10000; i++) {
1290 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1291 break;
1292 msleep(1);
1293 }
1294
1295 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1296 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1297
1298 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1299 }
1300
1301 static void lpphy_calibrate_rc(struct b43_wldev *dev)
1302 {
1303 struct b43_phy_lp *lpphy = dev->phy.lp;
1304
1305 if (dev->phy.rev >= 2) {
1306 lpphy_rev2plus_rc_calib(dev);
1307 } else if (!lpphy->rc_cap) {
1308 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1309 lpphy_rev0_1_rc_calib(dev);
1310 } else {
1311 lpphy_set_rc_cap(dev);
1312 }
1313 }
1314
1315 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1316 {
1317 struct b43_phy_lp *lpphy = dev->phy.lp;
1318
1319 lpphy->tx_pwr_idx_over = index;
1320 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1321 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1322
1323 //TODO
1324 }
1325
1326 static void lpphy_btcoex_override(struct b43_wldev *dev)
1327 {
1328 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1329 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1330 }
1331
1332 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1333 {
1334 struct b43_phy_lp *lpphy = dev->phy.lp;
1335 u32 *saved_tab;
1336 const unsigned int saved_tab_size = 256;
1337 enum b43_lpphy_txpctl_mode txpctl_mode;
1338 s8 tx_pwr_idx_over;
1339 u16 tssi_npt, tssi_idx;
1340
1341 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1342 if (!saved_tab) {
1343 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1344 return;
1345 }
1346
1347 lpphy_read_tx_pctl_mode_from_hardware(dev);
1348 txpctl_mode = lpphy->txpctl_mode;
1349 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1350 tssi_npt = lpphy->tssi_npt;
1351 tssi_idx = lpphy->tssi_idx;
1352
1353 if (dev->phy.rev < 2) {
1354 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1355 saved_tab_size, saved_tab);
1356 } else {
1357 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1358 saved_tab_size, saved_tab);
1359 }
1360 //TODO
1361
1362 kfree(saved_tab);
1363 }
1364
1365 static void lpphy_calibration(struct b43_wldev *dev)
1366 {
1367 struct b43_phy_lp *lpphy = dev->phy.lp;
1368 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1369
1370 b43_mac_suspend(dev);
1371
1372 lpphy_btcoex_override(dev);
1373 lpphy_read_tx_pctl_mode_from_hardware(dev);
1374 saved_pctl_mode = lpphy->txpctl_mode;
1375 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1376 //TODO Perform transmit power table I/Q LO calibration
1377 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1378 lpphy_pr41573_workaround(dev);
1379 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1380 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1381 //TODO Perform I/Q calibration with a single control value set
1382
1383 b43_mac_enable(dev);
1384 }
1385
1386 static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1387 {
1388 if (mode != TSSI_MUX_EXT) {
1389 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1390 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1391 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1392 if (mode == TSSI_MUX_POSTPA) {
1393 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1394 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1395 } else {
1396 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1397 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1398 0xFFC7, 0x20);
1399 }
1400 } else {
1401 B43_WARN_ON(1);
1402 }
1403 }
1404
1405 static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1406 {
1407 u16 tmp;
1408 int i;
1409
1410 //SPEC TODO Call LP PHY Clear TX Power offsets
1411 for (i = 0; i < 64; i++) {
1412 if (dev->phy.rev >= 2)
1413 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1414 else
1415 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1416 }
1417
1418 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1419 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1420 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1421 if (dev->phy.rev < 2) {
1422 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1423 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1424 } else {
1425 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1426 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1427 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1428 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1429 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1430 }
1431 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1432 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1433 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1434 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1435 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1436 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1437 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1438 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1439 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1440 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1441
1442 if (dev->phy.rev < 2) {
1443 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1444 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1445 } else {
1446 lpphy_set_tx_power_by_index(dev, 0x7F);
1447 }
1448
1449 b43_dummy_transmission(dev, true, true);
1450
1451 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1452 if (tmp & 0x8000) {
1453 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1454 0xFFC0, (tmp & 0xFF) - 32);
1455 }
1456
1457 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1458
1459 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1460 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1461 }
1462
1463 static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1464 {
1465 struct lpphy_tx_gains gains;
1466
1467 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1468 gains.gm = 4;
1469 gains.pad = 12;
1470 gains.pga = 12;
1471 gains.dac = 0;
1472 } else {
1473 gains.gm = 7;
1474 gains.pad = 14;
1475 gains.pga = 15;
1476 gains.dac = 0;
1477 }
1478 lpphy_set_tx_gains(dev, gains);
1479 lpphy_set_bb_mult(dev, 150);
1480 }
1481
1482 /* Initialize TX power control */
1483 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1484 {
1485 if (0/*FIXME HWPCTL capable */) {
1486 lpphy_tx_pctl_init_hw(dev);
1487 } else { /* This device is only software TX power control capable. */
1488 lpphy_tx_pctl_init_sw(dev);
1489 }
1490 }
1491
1492 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1493 {
1494 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1495 return b43_read16(dev, B43_MMIO_PHY_DATA);
1496 }
1497
1498 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1499 {
1500 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1501 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1502 }
1503
1504 static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
1505 u16 set)
1506 {
1507 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1508 b43_write16(dev, B43_MMIO_PHY_DATA,
1509 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
1510 }
1511
1512 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1513 {
1514 /* Register 1 is a 32-bit register. */
1515 B43_WARN_ON(reg == 1);
1516 /* LP-PHY needs a special bit set for read access */
1517 if (dev->phy.rev < 2) {
1518 if (reg != 0x4001)
1519 reg |= 0x100;
1520 } else
1521 reg |= 0x200;
1522
1523 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1524 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1525 }
1526
1527 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1528 {
1529 /* Register 1 is a 32-bit register. */
1530 B43_WARN_ON(reg == 1);
1531
1532 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1533 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1534 }
1535
1536 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
1537 bool blocked)
1538 {
1539 //TODO
1540 }
1541
1542 struct b206x_channel {
1543 u8 channel;
1544 u16 freq;
1545 u8 data[12];
1546 };
1547
1548 static const struct b206x_channel b2062_chantbl[] = {
1549 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1550 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1551 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1552 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1553 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1554 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1555 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1556 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1557 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1558 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1559 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1560 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1561 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1562 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1563 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1564 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1565 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1566 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1567 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1568 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1569 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1570 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1571 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1572 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1573 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1574 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1575 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1576 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1577 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1578 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1579 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1580 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1581 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1582 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1583 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1584 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1585 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1586 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1587 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1588 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1589 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1590 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1591 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1592 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1593 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1594 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1595 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1596 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1597 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1598 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1599 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1600 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1601 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1602 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1603 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1604 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1605 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1606 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1607 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1608 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1609 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1610 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1611 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1612 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1613 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1614 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1615 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1616 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1617 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1618 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1619 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1620 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1621 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1622 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1623 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1624 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1625 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1626 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1627 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1628 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1629 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1630 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1631 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1632 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1633 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1634 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1635 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1636 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1637 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1638 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1639 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1640 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1641 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1642 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1643 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1644 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1645 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1646 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1647 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1648 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1649 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1650 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1651 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1652 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1653 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1654 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1655 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1656 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1657 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1658 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1659 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1660 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1661 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1662 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1663 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1664 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1665 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1666 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1667 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1668 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1669 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1670 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1671 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1672 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1673 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1674 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1675 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1676 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1677 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1678 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1679 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1680 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1681 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1682 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1683 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1684 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1685 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1686 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1687 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1688 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1689 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1690 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1691 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1692 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1693 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1694 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1695 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1696 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1697 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1698 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1699 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1700 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1701 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1702 };
1703
1704 static const struct b206x_channel b2063_chantbl[] = {
1705 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1706 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1707 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1708 .data[10] = 0x80, .data[11] = 0x70, },
1709 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1710 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1711 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1712 .data[10] = 0x80, .data[11] = 0x70, },
1713 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1714 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1715 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1716 .data[10] = 0x80, .data[11] = 0x70, },
1717 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1718 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1719 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1720 .data[10] = 0x80, .data[11] = 0x70, },
1721 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1722 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1723 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1724 .data[10] = 0x80, .data[11] = 0x70, },
1725 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1726 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1727 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1728 .data[10] = 0x80, .data[11] = 0x70, },
1729 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1730 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1731 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1732 .data[10] = 0x80, .data[11] = 0x70, },
1733 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1734 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1735 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1736 .data[10] = 0x80, .data[11] = 0x70, },
1737 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1738 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1739 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1740 .data[10] = 0x80, .data[11] = 0x70, },
1741 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1742 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1743 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1744 .data[10] = 0x80, .data[11] = 0x70, },
1745 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1746 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1747 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1748 .data[10] = 0x80, .data[11] = 0x70, },
1749 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1750 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1751 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1752 .data[10] = 0x80, .data[11] = 0x70, },
1753 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1754 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1755 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1756 .data[10] = 0x80, .data[11] = 0x70, },
1757 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1758 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1759 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1760 .data[10] = 0x80, .data[11] = 0x70, },
1761 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1762 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1763 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1764 .data[10] = 0x20, .data[11] = 0x00, },
1765 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1766 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1767 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1768 .data[10] = 0x20, .data[11] = 0x00, },
1769 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1770 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1771 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1772 .data[10] = 0x20, .data[11] = 0x00, },
1773 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1774 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1775 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1776 .data[10] = 0x20, .data[11] = 0x00, },
1777 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1778 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1779 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1780 .data[10] = 0x20, .data[11] = 0x00, },
1781 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1782 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1783 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1784 .data[10] = 0x20, .data[11] = 0x00, },
1785 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1786 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1787 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1788 .data[10] = 0x20, .data[11] = 0x00, },
1789 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1790 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1791 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1792 .data[10] = 0x20, .data[11] = 0x00, },
1793 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1794 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1795 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1796 .data[10] = 0x20, .data[11] = 0x00, },
1797 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1798 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1799 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1800 .data[10] = 0x10, .data[11] = 0x00, },
1801 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1802 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1803 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1804 .data[10] = 0x10, .data[11] = 0x00, },
1805 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1806 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1807 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1808 .data[10] = 0x10, .data[11] = 0x00, },
1809 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1810 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1811 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1812 .data[10] = 0x00, .data[11] = 0x00, },
1813 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1814 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1815 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1816 .data[10] = 0x00, .data[11] = 0x00, },
1817 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1818 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1819 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1820 .data[10] = 0x00, .data[11] = 0x00, },
1821 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1822 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1823 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1824 .data[10] = 0x00, .data[11] = 0x00, },
1825 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1826 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1827 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1828 .data[10] = 0x00, .data[11] = 0x00, },
1829 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1830 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1831 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1832 .data[10] = 0x00, .data[11] = 0x00, },
1833 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1834 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1835 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1836 .data[10] = 0x00, .data[11] = 0x00, },
1837 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1838 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1839 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1840 .data[10] = 0x00, .data[11] = 0x00, },
1841 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1842 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1843 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1844 .data[10] = 0x00, .data[11] = 0x00, },
1845 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1846 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1847 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1848 .data[10] = 0x00, .data[11] = 0x00, },
1849 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1850 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1851 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1852 .data[10] = 0x00, .data[11] = 0x00, },
1853 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1854 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1855 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1856 .data[10] = 0x00, .data[11] = 0x00, },
1857 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1858 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1859 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1860 .data[10] = 0x00, .data[11] = 0x00, },
1861 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1862 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1863 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1864 .data[10] = 0x00, .data[11] = 0x00, },
1865 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1866 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1867 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1868 .data[10] = 0x00, .data[11] = 0x00, },
1869 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1870 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1871 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1872 .data[10] = 0x00, .data[11] = 0x00, },
1873 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1874 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1875 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1876 .data[10] = 0x50, .data[11] = 0x00, },
1877 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1878 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1879 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1880 .data[10] = 0x50, .data[11] = 0x00, },
1881 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1882 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1883 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1884 .data[10] = 0x50, .data[11] = 0x00, },
1885 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1886 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1887 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1888 .data[10] = 0x40, .data[11] = 0x00, },
1889 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1890 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1891 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1892 .data[10] = 0x40, .data[11] = 0x00, },
1893 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1894 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1895 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1896 .data[10] = 0x40, .data[11] = 0x00, },
1897 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1898 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1899 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1900 .data[10] = 0x40, .data[11] = 0x00, },
1901 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1902 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1903 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1904 .data[10] = 0x40, .data[11] = 0x00, },
1905 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1906 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1907 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1908 .data[10] = 0x40, .data[11] = 0x00, },
1909 };
1910
1911 static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
1912 {
1913 struct ssb_bus *bus = dev->dev->bus;
1914
1915 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1916 udelay(20);
1917 if (bus->chip_id == 0x5354) {
1918 b43_radio_write(dev, B2062_N_COMM1, 4);
1919 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1920 } else {
1921 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1922 }
1923 udelay(5);
1924 }
1925
1926 static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1927 {
1928 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1929 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1930 udelay(200);
1931 }
1932
1933 static int lpphy_b2062_tune(struct b43_wldev *dev,
1934 unsigned int channel)
1935 {
1936 struct b43_phy_lp *lpphy = dev->phy.lp;
1937 struct ssb_bus *bus = dev->dev->bus;
1938 const struct b206x_channel *chandata = NULL;
1939 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1940 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1941 int i, err = 0;
1942
1943 for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
1944 if (b2062_chantbl[i].channel == channel) {
1945 chandata = &b2062_chantbl[i];
1946 break;
1947 }
1948 }
1949
1950 if (B43_WARN_ON(!chandata))
1951 return -EINVAL;
1952
1953 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1954 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1955 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1956 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1957 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1958 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1959 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1960 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1961 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1962 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1963
1964 tmp1 = crystal_freq / 1000;
1965 tmp2 = lpphy->pdiv * 1000;
1966 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1967 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1968 lpphy_b2062_reset_pll_bias(dev);
1969 tmp3 = tmp2 * channel2freq_lp(channel);
1970 if (channel2freq_lp(channel) < 4000)
1971 tmp3 *= 2;
1972 tmp4 = 48 * tmp1;
1973 tmp6 = tmp3 / tmp4;
1974 tmp7 = tmp3 % tmp4;
1975 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1976 tmp5 = tmp7 * 0x100;
1977 tmp6 = tmp5 / tmp4;
1978 tmp7 = tmp5 % tmp4;
1979 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
1980 tmp5 = tmp7 * 0x100;
1981 tmp6 = tmp5 / tmp4;
1982 tmp7 = tmp5 % tmp4;
1983 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1984 tmp5 = tmp7 * 0x100;
1985 tmp6 = tmp5 / tmp4;
1986 tmp7 = tmp5 % tmp4;
1987 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1988 tmp8 = b43_radio_read(dev, B2062_S_RFPLL_CTL19);
1989 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
1990 b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
1991 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1992
1993 lpphy_b2062_vco_calib(dev);
1994 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
1995 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
1996 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
1997 lpphy_b2062_reset_pll_bias(dev);
1998 lpphy_b2062_vco_calib(dev);
1999 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
2000 err = -EIO;
2001 }
2002
2003 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
2004 return err;
2005 }
2006
2007
2008 /* This was previously called lpphy_japan_filter */
2009 static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
2010 {
2011 struct b43_phy_lp *lpphy = dev->phy.lp;
2012 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
2013
2014 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
2015 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
2016 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
2017 lpphy_set_rc_cap(dev);
2018 } else {
2019 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
2020 }
2021 }
2022
2023 static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
2024 {
2025 u16 tmp;
2026
2027 b43_radio_mask(dev, B2063_PLL_SP1, ~0x40);
2028 tmp = b43_radio_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
2029 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
2030 udelay(1);
2031 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
2032 udelay(1);
2033 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
2034 udelay(1);
2035 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
2036 udelay(300);
2037 b43_radio_set(dev, B2063_PLL_SP1, 0x40);
2038 }
2039
2040 static int lpphy_b2063_tune(struct b43_wldev *dev,
2041 unsigned int channel)
2042 {
2043 struct ssb_bus *bus = dev->dev->bus;
2044
2045 static const struct b206x_channel *chandata = NULL;
2046 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2047 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
2048 u16 old_comm15, scale;
2049 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
2050 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
2051
2052 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
2053 if (b2063_chantbl[i].channel == channel) {
2054 chandata = &b2063_chantbl[i];
2055 break;
2056 }
2057 }
2058
2059 if (B43_WARN_ON(!chandata))
2060 return -EINVAL;
2061
2062 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2063 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2064 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2065 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2066 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2067 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2068 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2069 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2070 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2071 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2072 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2073 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2074
2075 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2076 b43_radio_set(dev, B2063_COMM15, 0x1E);
2077
2078 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2079 vco_freq = chandata->freq << 1;
2080 else
2081 vco_freq = chandata->freq << 2;
2082
2083 freqref = crystal_freq * 3;
2084 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2085 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2086 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2087 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2088 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2089 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2090 0xFFF8, timeout >> 2);
2091 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2092 0xFF9F,timeout << 5);
2093
2094 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2095 999999) / 1000000) + 1;
2096 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2097
2098 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2099 count *= (timeout + 1) * (timeoutref + 1);
2100 count--;
2101 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2102 0xF0, count >> 8);
2103 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2104
2105 tmp1 = ((val3 * 62500) / freqref) << 4;
2106 tmp2 = ((val3 * 62500) % freqref) << 4;
2107 while (tmp2 >= freqref) {
2108 tmp1++;
2109 tmp2 -= freqref;
2110 }
2111 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2112 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2113 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2114 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2115 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2116
2117 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2118 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2119 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2120 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2121
2122 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2123 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2124
2125 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2126 scale = 1;
2127 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2128 } else {
2129 scale = 0;
2130 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2131 }
2132 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2133 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2134
2135 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2136 tmp6 *= (tmp5 * 8) * (scale + 1);
2137 if (tmp6 > 150)
2138 tmp6 = 0;
2139
2140 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2141 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2142
2143 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2144 if (crystal_freq > 26000000)
2145 b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2146 else
2147 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2148
2149 if (val1 == 45)
2150 b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2151 else
2152 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2153
2154 b43_radio_set(dev, B2063_PLL_SP2, 0x3);
2155 udelay(1);
2156 b43_radio_mask(dev, B2063_PLL_SP2, 0xFFFC);
2157 lpphy_b2063_vco_calib(dev);
2158 b43_radio_write(dev, B2063_COMM15, old_comm15);
2159
2160 return 0;
2161 }
2162
2163 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2164 unsigned int new_channel)
2165 {
2166 struct b43_phy_lp *lpphy = dev->phy.lp;
2167 int err;
2168
2169 if (dev->phy.radio_ver == 0x2063) {
2170 err = lpphy_b2063_tune(dev, new_channel);
2171 if (err)
2172 return err;
2173 } else {
2174 err = lpphy_b2062_tune(dev, new_channel);
2175 if (err)
2176 return err;
2177 lpphy_set_analog_filter(dev, new_channel);
2178 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
2179 }
2180
2181 lpphy->channel = new_channel;
2182 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2183
2184 return 0;
2185 }
2186
2187 static int b43_lpphy_op_init(struct b43_wldev *dev)
2188 {
2189 int err;
2190
2191 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2192 lpphy_baseband_init(dev);
2193 lpphy_radio_init(dev);
2194 lpphy_calibrate_rc(dev);
2195 err = b43_lpphy_op_switch_channel(dev, 7);
2196 if (err) {
2197 b43dbg(dev->wl, "Switch to channel 7 failed, error = %d.\n",
2198 err);
2199 }
2200 lpphy_tx_pctl_init(dev);
2201 lpphy_calibration(dev);
2202 //TODO ACI init
2203
2204 return 0;
2205 }
2206
2207 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2208 {
2209 if (dev->phy.rev >= 2)
2210 return; // rev2+ doesn't support antenna diversity
2211
2212 if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1))
2213 return;
2214
2215 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2);
2216 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1);
2217 }
2218
2219 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2220 {
2221 //TODO
2222 }
2223
2224 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2225 bool ignore_tssi)
2226 {
2227 //TODO
2228 return B43_TXPWR_RES_DONE;
2229 }
2230
2231 void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on)
2232 {
2233 if (on) {
2234 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8);
2235 } else {
2236 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0x0007);
2237 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x0007);
2238 }
2239 }
2240
2241 const struct b43_phy_operations b43_phyops_lp = {
2242 .allocate = b43_lpphy_op_allocate,
2243 .free = b43_lpphy_op_free,
2244 .prepare_structs = b43_lpphy_op_prepare_structs,
2245 .init = b43_lpphy_op_init,
2246 .phy_read = b43_lpphy_op_read,
2247 .phy_write = b43_lpphy_op_write,
2248 .phy_maskset = b43_lpphy_op_maskset,
2249 .radio_read = b43_lpphy_op_radio_read,
2250 .radio_write = b43_lpphy_op_radio_write,
2251 .software_rfkill = b43_lpphy_op_software_rfkill,
2252 .switch_analog = b43_lpphy_op_switch_analog,
2253 .switch_channel = b43_lpphy_op_switch_channel,
2254 .get_default_chan = b43_lpphy_op_get_default_chan,
2255 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2256 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2257 .adjust_txpower = b43_lpphy_op_adjust_txpower,
2258 };
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