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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / wireless / b43 / phy_n.c
blob992318a78077b2c60f872495a8a6acf8bb981c96
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23 */
24
25 #include <linux/delay.h>
26 #include <linux/types.h>
27
28 #include "b43.h"
29 #include "phy_n.h"
30 #include "tables_nphy.h"
31
32
33 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
34 {//TODO
35 }
36
37 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
38 {//TODO
39 }
40
41 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
42 bool ignore_tssi)
43 {//TODO
44 return B43_TXPWR_RES_DONE;
45 }
46
47 static void b43_chantab_radio_upload(struct b43_wldev *dev,
48 const struct b43_nphy_channeltab_entry *e)
49 {
50 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
51 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
52 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
53 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
54 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
55 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
56 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
57 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
58 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
59 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
60 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
61 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
62 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
63 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
64 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
65 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
66 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
67 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
68 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
69 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
70 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
71 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
72 }
73
74 static void b43_chantab_phy_upload(struct b43_wldev *dev,
75 const struct b43_nphy_channeltab_entry *e)
76 {
77 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
78 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
79 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
80 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
81 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
82 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
83 }
84
85 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
86 {
87 //TODO
88 }
89
90 /* Tune the hardware to a new channel. */
91 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
92 {
93 const struct b43_nphy_channeltab_entry *tabent;
94
95 tabent = b43_nphy_get_chantabent(dev, channel);
96 if (!tabent)
97 return -ESRCH;
98
99 //FIXME enable/disable band select upper20 in RXCTL
100 if (0 /*FIXME 5Ghz*/)
101 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
102 else
103 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
104 b43_chantab_radio_upload(dev, tabent);
105 udelay(50);
106 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
107 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
108 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
109 udelay(300);
110 if (0 /*FIXME 5Ghz*/)
111 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
112 else
113 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
114 b43_chantab_phy_upload(dev, tabent);
115 b43_nphy_tx_power_fix(dev);
116
117 return 0;
118 }
119
120 static void b43_radio_init2055_pre(struct b43_wldev *dev)
121 {
122 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
123 ~B43_NPHY_RFCTL_CMD_PORFORCE);
124 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
125 B43_NPHY_RFCTL_CMD_CHIP0PU |
126 B43_NPHY_RFCTL_CMD_OEPORFORCE);
127 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
128 B43_NPHY_RFCTL_CMD_PORFORCE);
129 }
130
131 static void b43_radio_init2055_post(struct b43_wldev *dev)
132 {
133 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
134 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
135 int i;
136 u16 val;
137
138 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
139 msleep(1);
140 if ((sprom->revision != 4) ||
141 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
142 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
143 (binfo->type != 0x46D) ||
144 (binfo->rev < 0x41)) {
145 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
146 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
147 msleep(1);
148 }
149 }
150 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
151 msleep(1);
152 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
153 msleep(1);
154 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
155 msleep(1);
156 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
157 msleep(1);
158 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
159 msleep(1);
160 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
161 msleep(1);
162 for (i = 0; i < 100; i++) {
163 val = b43_radio_read16(dev, B2055_CAL_COUT2);
164 if (val & 0x80)
165 break;
166 udelay(10);
167 }
168 msleep(1);
169 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
170 msleep(1);
171 nphy_channel_switch(dev, dev->phy.channel);
172 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
173 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
174 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
175 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
176 }
177
178 /* Initialize a Broadcom 2055 N-radio */
179 static void b43_radio_init2055(struct b43_wldev *dev)
180 {
181 b43_radio_init2055_pre(dev);
182 if (b43_status(dev) < B43_STAT_INITIALIZED)
183 b2055_upload_inittab(dev, 0, 1);
184 else
185 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
186 b43_radio_init2055_post(dev);
187 }
188
189 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
190 {
191 b43_radio_init2055(dev);
192 }
193
194 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
195 {
196 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
197 ~B43_NPHY_RFCTL_CMD_EN);
198 }
199
200 #define ntab_upload(dev, offset, data) do { \
201 unsigned int i; \
202 for (i = 0; i < (offset##_SIZE); i++) \
203 b43_ntab_write(dev, (offset) + i, (data)[i]); \
204 } while (0)
205
206 /* Upload the N-PHY tables. */
207 static void b43_nphy_tables_init(struct b43_wldev *dev)
208 {
209 /* Static tables */
210 ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
211 ntab_upload(dev, B43_NTAB_FRAMELT, b43_ntab_framelookup);
212 ntab_upload(dev, B43_NTAB_TMAP, b43_ntab_tmap);
213 ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn);
214 ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel);
215 ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot);
216 ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
217 ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0);
218 ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1);
219 ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0);
220 ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1);
221 ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
222 ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest);
223 ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs);
224
225 /* Volatile tables */
226 ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10);
227 ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11);
228 ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0);
229 ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1);
230 ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0);
231 ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1);
232 ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
233 ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
234 ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0);
235 ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1);
236 ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0);
237 ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
238 }
239
240 static void b43_nphy_workarounds(struct b43_wldev *dev)
241 {
242 struct b43_phy *phy = &dev->phy;
243 unsigned int i;
244
245 b43_phy_set(dev, B43_NPHY_IQFLIP,
246 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
247 if (1 /* FIXME band is 2.4GHz */) {
248 b43_phy_set(dev, B43_NPHY_CLASSCTL,
249 B43_NPHY_CLASSCTL_CCKEN);
250 } else {
251 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
252 ~B43_NPHY_CLASSCTL_CCKEN);
253 }
254 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
255 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
256
257 /* Fixup some tables */
258 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
259 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
260 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
261 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
262 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
263 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
264 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
265 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
266 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
267 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
268
269 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
270 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
271 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
272 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
273
274 //TODO set RF sequence
275
276 /* Set narrowband clip threshold */
277 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
278 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
279
280 /* Set wideband clip 2 threshold */
281 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
282 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
283 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
284 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
285 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
286 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
287
288 /* Set Clip 2 detect */
289 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
290 B43_NPHY_C1_CGAINI_CL2DETECT);
291 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
292 B43_NPHY_C2_CGAINI_CL2DETECT);
293
294 if (0 /*FIXME*/) {
295 /* Set dwell lengths */
296 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
297 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
298 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
299 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
300
301 /* Set gain backoff */
302 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
303 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
304 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
305 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
306 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
307 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
308
309 /* Set HPVGA2 index */
310 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
311 ~B43_NPHY_C1_INITGAIN_HPVGA2,
312 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
313 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
314 ~B43_NPHY_C2_INITGAIN_HPVGA2,
315 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
316
317 //FIXME verify that the specs really mean to use autoinc here.
318 for (i = 0; i < 3; i++)
319 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
320 }
321
322 /* Set minimum gain value */
323 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
324 ~B43_NPHY_C1_MINGAIN,
325 23 << B43_NPHY_C1_MINGAIN_SHIFT);
326 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
327 ~B43_NPHY_C2_MINGAIN,
328 23 << B43_NPHY_C2_MINGAIN_SHIFT);
329
330 if (phy->rev < 2) {
331 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
332 ~B43_NPHY_SCRAM_SIGCTL_SCM);
333 }
334
335 /* Set phase track alpha and beta */
336 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
337 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
338 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
339 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
340 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
341 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
342 }
343
344 static void b43_nphy_reset_cca(struct b43_wldev *dev)
345 {
346 u16 bbcfg;
347
348 ssb_write32(dev->dev, SSB_TMSLOW,
349 ssb_read32(dev->dev, SSB_TMSLOW) | SSB_TMSLOW_FGC);
350 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
351 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTCCA);
352 b43_phy_write(dev, B43_NPHY_BBCFG,
353 bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
354 ssb_write32(dev->dev, SSB_TMSLOW,
355 ssb_read32(dev->dev, SSB_TMSLOW) & ~SSB_TMSLOW_FGC);
356 }
357
358 enum b43_nphy_rf_sequence {
359 B43_RFSEQ_RX2TX,
360 B43_RFSEQ_TX2RX,
361 B43_RFSEQ_RESET2RX,
362 B43_RFSEQ_UPDATE_GAINH,
363 B43_RFSEQ_UPDATE_GAINL,
364 B43_RFSEQ_UPDATE_GAINU,
365 };
366
367 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
368 enum b43_nphy_rf_sequence seq)
369 {
370 static const u16 trigger[] = {
371 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
372 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
373 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
374 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
375 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
376 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
377 };
378 int i;
379
380 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
381
382 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
383 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
384 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
385 for (i = 0; i < 200; i++) {
386 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
387 goto ok;
388 msleep(1);
389 }
390 b43err(dev->wl, "RF sequence status timeout\n");
391 ok:
392 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
393 ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
394 }
395
396 static void b43_nphy_bphy_init(struct b43_wldev *dev)
397 {
398 unsigned int i;
399 u16 val;
400
401 val = 0x1E1F;
402 for (i = 0; i < 14; i++) {
403 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
404 val -= 0x202;
405 }
406 val = 0x3E3F;
407 for (i = 0; i < 16; i++) {
408 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
409 val -= 0x202;
410 }
411 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
412 }
413
414 /* RSSI Calibration */
415 static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
416 {
417 //TODO
418 }
419
420 int b43_phy_initn(struct b43_wldev *dev)
421 {
422 struct b43_phy *phy = &dev->phy;
423 u16 tmp;
424
425 //TODO: Spectral management
426 b43_nphy_tables_init(dev);
427
428 /* Clear all overrides */
429 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
430 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
431 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
432 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
433 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
434 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
435 ~(B43_NPHY_RFSEQMODE_CAOVER |
436 B43_NPHY_RFSEQMODE_TROVER));
437 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
438
439 tmp = (phy->rev < 2) ? 64 : 59;
440 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
441 ~B43_NPHY_BPHY_CTL3_SCALE,
442 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
443
444 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
445 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
446
447 b43_phy_write(dev, B43_NPHY_TXREALFD, 184);
448 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 200);
449 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 80);
450 b43_phy_write(dev, B43_NPHY_C2_BCLIPBKOFF, 511);
451
452 //TODO MIMO-Config
453 //TODO Update TX/RX chain
454
455 if (phy->rev < 2) {
456 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
457 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
458 }
459 b43_nphy_workarounds(dev);
460 b43_nphy_reset_cca(dev);
461
462 ssb_write32(dev->dev, SSB_TMSLOW,
463 ssb_read32(dev->dev, SSB_TMSLOW) | B43_TMSLOW_MACPHYCLKEN);
464 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
465 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
466
467 b43_phy_read(dev, B43_NPHY_CLASSCTL); /* dummy read */
468 //TODO read core1/2 clip1 thres regs
469
470 if (1 /* FIXME Band is 2.4GHz */)
471 b43_nphy_bphy_init(dev);
472 //TODO disable TX power control
473 //TODO Fix the TX power settings
474 //TODO Init periodic calibration with reason 3
475 b43_nphy_rssi_cal(dev, 2);
476 b43_nphy_rssi_cal(dev, 0);
477 b43_nphy_rssi_cal(dev, 1);
478 //TODO get TX gain
479 //TODO init superswitch
480 //TODO calibrate LO
481 //TODO idle TSSI TX pctl
482 //TODO TX power control power setup
483 //TODO table writes
484 //TODO TX power control coefficients
485 //TODO enable TX power control
486 //TODO control antenna selection
487 //TODO init radar detection
488 //TODO reset channel if changed
489
490 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
491 return 0;
492 }
493
494 static int b43_nphy_op_allocate(struct b43_wldev *dev)
495 {
496 struct b43_phy_n *nphy;
497
498 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
499 if (!nphy)
500 return -ENOMEM;
501 dev->phy.n = nphy;
502
503 return 0;
504 }
505
506 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
507 {
508 struct b43_phy *phy = &dev->phy;
509 struct b43_phy_n *nphy = phy->n;
510
511 memset(nphy, 0, sizeof(*nphy));
512
513 //TODO init struct b43_phy_n
514 }
515
516 static void b43_nphy_op_free(struct b43_wldev *dev)
517 {
518 struct b43_phy *phy = &dev->phy;
519 struct b43_phy_n *nphy = phy->n;
520
521 kfree(nphy);
522 phy->n = NULL;
523 }
524
525 static int b43_nphy_op_init(struct b43_wldev *dev)
526 {
527 return b43_phy_initn(dev);
528 }
529
530 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
531 {
532 #if B43_DEBUG
533 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
534 /* OFDM registers are onnly available on A/G-PHYs */
535 b43err(dev->wl, "Invalid OFDM PHY access at "
536 "0x%04X on N-PHY\n", offset);
537 dump_stack();
538 }
539 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
540 /* Ext-G registers are only available on G-PHYs */
541 b43err(dev->wl, "Invalid EXT-G PHY access at "
542 "0x%04X on N-PHY\n", offset);
543 dump_stack();
544 }
545 #endif /* B43_DEBUG */
546 }
547
548 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
549 {
550 check_phyreg(dev, reg);
551 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
552 return b43_read16(dev, B43_MMIO_PHY_DATA);
553 }
554
555 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
556 {
557 check_phyreg(dev, reg);
558 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
559 b43_write16(dev, B43_MMIO_PHY_DATA, value);
560 }
561
562 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
563 {
564 /* Register 1 is a 32-bit register. */
565 B43_WARN_ON(reg == 1);
566 /* N-PHY needs 0x100 for read access */
567 reg |= 0x100;
568
569 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
570 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
571 }
572
573 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
574 {
575 /* Register 1 is a 32-bit register. */
576 B43_WARN_ON(reg == 1);
577
578 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
579 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
580 }
581
582 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
583 bool blocked)
584 {//TODO
585 }
586
587 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
588 {
589 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
590 on ? 0 : 0x7FFF);
591 }
592
593 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
594 unsigned int new_channel)
595 {
596 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
597 if ((new_channel < 1) || (new_channel > 14))
598 return -EINVAL;
599 } else {
600 if (new_channel > 200)
601 return -EINVAL;
602 }
603
604 return nphy_channel_switch(dev, new_channel);
605 }
606
607 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
608 {
609 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
610 return 1;
611 return 36;
612 }
613
614 const struct b43_phy_operations b43_phyops_n = {
615 .allocate = b43_nphy_op_allocate,
616 .free = b43_nphy_op_free,
617 .prepare_structs = b43_nphy_op_prepare_structs,
618 .init = b43_nphy_op_init,
619 .phy_read = b43_nphy_op_read,
620 .phy_write = b43_nphy_op_write,
621 .radio_read = b43_nphy_op_radio_read,
622 .radio_write = b43_nphy_op_radio_write,
623 .software_rfkill = b43_nphy_op_software_rfkill,
624 .switch_analog = b43_nphy_op_switch_analog,
625 .switch_channel = b43_nphy_op_switch_channel,
626 .get_default_chan = b43_nphy_op_get_default_chan,
627 .recalc_txpower = b43_nphy_op_recalc_txpower,
628 .adjust_txpower = b43_nphy_op_adjust_txpower,
629 };
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