[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / wireless / p54 / lmac.h
blob04b63ec80fa46c6b68f17c992278b490a1de7728
1 /*
2 * LMAC Interface specific definitions for mac80211 Prism54 drivers
4 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
5 * Copyright (c) 2007 - 2009, Christian Lamparter <chunkeey@web.de>
7 * Based on:
8 * - the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
11 * - LMAC API interface header file for STLC4560 (lmac_longbow.h)
12 * Copyright (C) 2007 Conexant Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #ifndef LMAC_H
20 #define LMAC_H
22 enum p54_control_frame_types {
23 P54_CONTROL_TYPE_SETUP = 0,
24 P54_CONTROL_TYPE_SCAN,
25 P54_CONTROL_TYPE_TRAP,
26 P54_CONTROL_TYPE_DCFINIT,
27 P54_CONTROL_TYPE_RX_KEYCACHE,
28 P54_CONTROL_TYPE_TIM,
29 P54_CONTROL_TYPE_PSM,
30 P54_CONTROL_TYPE_TXCANCEL,
31 P54_CONTROL_TYPE_TXDONE,
32 P54_CONTROL_TYPE_BURST,
33 P54_CONTROL_TYPE_STAT_READBACK,
34 P54_CONTROL_TYPE_BBP,
35 P54_CONTROL_TYPE_EEPROM_READBACK,
36 P54_CONTROL_TYPE_LED,
37 P54_CONTROL_TYPE_GPIO,
38 P54_CONTROL_TYPE_TIMER,
39 P54_CONTROL_TYPE_MODULATION,
40 P54_CONTROL_TYPE_SYNTH_CONFIG,
41 P54_CONTROL_TYPE_DETECTOR_VALUE,
42 P54_CONTROL_TYPE_XBOW_SYNTH_CFG,
43 P54_CONTROL_TYPE_CCE_QUIET,
44 P54_CONTROL_TYPE_PSM_STA_UNLOCK,
45 P54_CONTROL_TYPE_PCS,
46 P54_CONTROL_TYPE_BT_BALANCER = 28,
47 P54_CONTROL_TYPE_GROUP_ADDRESS_TABLE = 30,
48 P54_CONTROL_TYPE_ARPTABLE = 31,
49 P54_CONTROL_TYPE_BT_OPTIONS = 35,
52 #define P54_HDR_FLAG_CONTROL BIT(15)
53 #define P54_HDR_FLAG_CONTROL_OPSET (BIT(15) + BIT(0))
54 #define P54_HDR_FLAG_DATA_ALIGN BIT(14)
56 #define P54_HDR_FLAG_DATA_OUT_PROMISC BIT(0)
57 #define P54_HDR_FLAG_DATA_OUT_TIMESTAMP BIT(1)
58 #define P54_HDR_FLAG_DATA_OUT_SEQNR BIT(2)
59 #define P54_HDR_FLAG_DATA_OUT_BIT3 BIT(3)
60 #define P54_HDR_FLAG_DATA_OUT_BURST BIT(4)
61 #define P54_HDR_FLAG_DATA_OUT_NOCANCEL BIT(5)
62 #define P54_HDR_FLAG_DATA_OUT_CLEARTIM BIT(6)
63 #define P54_HDR_FLAG_DATA_OUT_HITCHHIKE BIT(7)
64 #define P54_HDR_FLAG_DATA_OUT_COMPRESS BIT(8)
65 #define P54_HDR_FLAG_DATA_OUT_CONCAT BIT(9)
66 #define P54_HDR_FLAG_DATA_OUT_PCS_ACCEPT BIT(10)
67 #define P54_HDR_FLAG_DATA_OUT_WAITEOSP BIT(11)
69 #define P54_HDR_FLAG_DATA_IN_FCS_GOOD BIT(0)
70 #define P54_HDR_FLAG_DATA_IN_MATCH_MAC BIT(1)
71 #define P54_HDR_FLAG_DATA_IN_MCBC BIT(2)
72 #define P54_HDR_FLAG_DATA_IN_BEACON BIT(3)
73 #define P54_HDR_FLAG_DATA_IN_MATCH_BSS BIT(4)
74 #define P54_HDR_FLAG_DATA_IN_BCAST_BSS BIT(5)
75 #define P54_HDR_FLAG_DATA_IN_DATA BIT(6)
76 #define P54_HDR_FLAG_DATA_IN_TRUNCATED BIT(7)
77 #define P54_HDR_FLAG_DATA_IN_BIT8 BIT(8)
78 #define P54_HDR_FLAG_DATA_IN_TRANSPARENT BIT(9)
80 struct p54_hdr {
81 __le16 flags;
82 __le16 len;
83 __le32 req_id;
84 __le16 type; /* enum p54_control_frame_types */
85 u8 rts_tries;
86 u8 tries;
87 u8 data[0];
88 } __packed;
90 #define GET_REQ_ID(skb) \
91 (((struct p54_hdr *) ((struct sk_buff *) skb)->data)->req_id) \
93 #define FREE_AFTER_TX(skb) \
94 ((((struct p54_hdr *) ((struct sk_buff *) skb)->data)-> \
95 flags) == cpu_to_le16(P54_HDR_FLAG_CONTROL_OPSET))
97 #define IS_DATA_FRAME(skb) \
98 (!((((struct p54_hdr *) ((struct sk_buff *) skb)->data)-> \
99 flags) & cpu_to_le16(P54_HDR_FLAG_CONTROL)))
101 #define GET_HW_QUEUE(skb) \
102 (((struct p54_tx_data *)((struct p54_hdr *) \
103 skb->data)->data)->hw_queue)
106 * shared interface ID definitions
107 * The interface ID is a unique identification of a specific interface.
108 * The following values are reserved: 0x0000, 0x0002, 0x0012, 0x0014, 0x0015
110 #define IF_ID_ISL36356A 0x0001 /* ISL36356A <-> Firmware */
111 #define IF_ID_MVC 0x0003 /* MAC Virtual Coprocessor */
112 #define IF_ID_DEBUG 0x0008 /* PolDebug Interface */
113 #define IF_ID_PRODUCT 0x0009
114 #define IF_ID_OEM 0x000a
115 #define IF_ID_PCI3877 0x000b /* 3877 <-> Host PCI */
116 #define IF_ID_ISL37704C 0x000c /* ISL37704C <-> Fw */
117 #define IF_ID_ISL39000 0x000f /* ISL39000 <-> Fw */
118 #define IF_ID_ISL39300A 0x0010 /* ISL39300A <-> Fw */
119 #define IF_ID_ISL37700_UAP 0x0016 /* ISL37700 uAP Fw <-> Fw */
120 #define IF_ID_ISL39000_UAP 0x0017 /* ISL39000 uAP Fw <-> Fw */
121 #define IF_ID_LMAC 0x001a /* Interface exposed by LMAC */
123 struct exp_if {
124 __le16 role;
125 __le16 if_id;
126 __le16 variant;
127 __le16 btm_compat;
128 __le16 top_compat;
129 } __packed;
131 struct dep_if {
132 __le16 role;
133 __le16 if_id;
134 __le16 variant;
135 } __packed;
137 /* driver <-> lmac definitions */
138 struct p54_eeprom_lm86 {
139 union {
140 struct {
141 __le16 offset;
142 __le16 len;
143 u8 data[0];
144 } __packed v1;
145 struct {
146 __le32 offset;
147 __le16 len;
148 u8 magic2;
149 u8 pad;
150 u8 magic[4];
151 u8 data[0];
152 } __packed v2;
153 } __packed;
154 } __packed;
156 enum p54_rx_decrypt_status {
157 P54_DECRYPT_NONE = 0,
158 P54_DECRYPT_OK,
159 P54_DECRYPT_NOKEY,
160 P54_DECRYPT_NOMICHAEL,
161 P54_DECRYPT_NOCKIPMIC,
162 P54_DECRYPT_FAIL_WEP,
163 P54_DECRYPT_FAIL_TKIP,
164 P54_DECRYPT_FAIL_MICHAEL,
165 P54_DECRYPT_FAIL_CKIPKP,
166 P54_DECRYPT_FAIL_CKIPMIC,
167 P54_DECRYPT_FAIL_AESCCMP
170 struct p54_rx_data {
171 __le16 flags;
172 __le16 len;
173 __le16 freq;
174 u8 antenna;
175 u8 rate;
176 u8 rssi;
177 u8 quality;
178 u8 decrypt_status;
179 u8 rssi_raw;
180 __le32 tsf32;
181 __le32 unalloc0;
182 u8 align[0];
183 } __packed;
185 enum p54_trap_type {
186 P54_TRAP_SCAN = 0,
187 P54_TRAP_TIMER,
188 P54_TRAP_BEACON_TX,
189 P54_TRAP_FAA_RADIO_ON,
190 P54_TRAP_FAA_RADIO_OFF,
191 P54_TRAP_RADAR,
192 P54_TRAP_NO_BEACON,
193 P54_TRAP_TBTT,
194 P54_TRAP_SCO_ENTER,
195 P54_TRAP_SCO_EXIT
198 struct p54_trap {
199 __le16 event;
200 __le16 frequency;
201 } __packed;
203 enum p54_frame_sent_status {
204 P54_TX_OK = 0,
205 P54_TX_FAILED,
206 P54_TX_PSM,
207 P54_TX_PSM_CANCELLED = 4
210 struct p54_frame_sent {
211 u8 status;
212 u8 tries;
213 u8 ack_rssi;
214 u8 quality;
215 __le16 seq;
216 u8 antenna;
217 u8 padding;
218 } __packed;
220 enum p54_tx_data_crypt {
221 P54_CRYPTO_NONE = 0,
222 P54_CRYPTO_WEP,
223 P54_CRYPTO_TKIP,
224 P54_CRYPTO_TKIPMICHAEL,
225 P54_CRYPTO_CCX_WEPMIC,
226 P54_CRYPTO_CCX_KPMIC,
227 P54_CRYPTO_CCX_KP,
228 P54_CRYPTO_AESCCMP
231 enum p54_tx_data_queue {
232 P54_QUEUE_BEACON = 0,
233 P54_QUEUE_FWSCAN = 1,
234 P54_QUEUE_MGMT = 2,
235 P54_QUEUE_CAB = 3,
236 P54_QUEUE_DATA = 4,
238 P54_QUEUE_AC_NUM = 4,
239 P54_QUEUE_AC_VO = 4,
240 P54_QUEUE_AC_VI = 5,
241 P54_QUEUE_AC_BE = 6,
242 P54_QUEUE_AC_BK = 7,
244 /* keep last */
245 P54_QUEUE_NUM = 8,
248 #define IS_QOS_QUEUE(n) (n >= P54_QUEUE_DATA)
250 struct p54_tx_data {
251 u8 rateset[8];
252 u8 rts_rate_idx;
253 u8 crypt_offset;
254 u8 key_type;
255 u8 key_len;
256 u8 key[16];
257 u8 hw_queue;
258 u8 backlog;
259 __le16 durations[4];
260 u8 tx_antenna;
261 union {
262 struct {
263 u8 cts_rate;
264 __le16 output_power;
265 } __packed longbow;
266 struct {
267 u8 output_power;
268 u8 cts_rate;
269 u8 unalloc;
270 } __packed normal;
271 } __packed;
272 u8 unalloc2[2];
273 u8 align[0];
274 } __packed;
276 /* unit is ms */
277 #define P54_TX_FRAME_LIFETIME 2000
278 #define P54_TX_TIMEOUT 4000
279 #define P54_STATISTICS_UPDATE 5000
281 #define P54_FILTER_TYPE_NONE 0
282 #define P54_FILTER_TYPE_STATION BIT(0)
283 #define P54_FILTER_TYPE_IBSS BIT(1)
284 #define P54_FILTER_TYPE_AP BIT(2)
285 #define P54_FILTER_TYPE_TRANSPARENT BIT(3)
286 #define P54_FILTER_TYPE_PROMISCUOUS BIT(4)
287 #define P54_FILTER_TYPE_HIBERNATE BIT(5)
288 #define P54_FILTER_TYPE_NOACK BIT(6)
289 #define P54_FILTER_TYPE_RX_DISABLED BIT(7)
291 struct p54_setup_mac {
292 __le16 mac_mode;
293 u8 mac_addr[ETH_ALEN];
294 u8 bssid[ETH_ALEN];
295 u8 rx_antenna;
296 u8 rx_align;
297 union {
298 struct {
299 __le32 basic_rate_mask;
300 u8 rts_rates[8];
301 __le32 rx_addr;
302 __le16 max_rx;
303 __le16 rxhw;
304 __le16 wakeup_timer;
305 __le16 unalloc0;
306 } __packed v1;
307 struct {
308 __le32 rx_addr;
309 __le16 max_rx;
310 __le16 rxhw;
311 __le16 timer;
312 __le16 truncate;
313 __le32 basic_rate_mask;
314 u8 sbss_offset;
315 u8 mcast_window;
316 u8 rx_rssi_threshold;
317 u8 rx_ed_threshold;
318 __le32 ref_clock;
319 __le16 lpf_bandwidth;
320 __le16 osc_start_delay;
321 } __packed v2;
322 } __packed;
323 } __packed;
325 #define P54_SETUP_V1_LEN 40
326 #define P54_SETUP_V2_LEN (sizeof(struct p54_setup_mac))
328 #define P54_SCAN_EXIT BIT(0)
329 #define P54_SCAN_TRAP BIT(1)
330 #define P54_SCAN_ACTIVE BIT(2)
331 #define P54_SCAN_FILTER BIT(3)
333 struct p54_scan_head {
334 __le16 mode;
335 __le16 dwell;
336 u8 scan_params[20];
337 __le16 freq;
338 } __packed;
340 struct p54_pa_curve_data_sample {
341 u8 rf_power;
342 u8 pa_detector;
343 u8 data_barker;
344 u8 data_bpsk;
345 u8 data_qpsk;
346 u8 data_16qam;
347 u8 data_64qam;
348 u8 padding;
349 } __packed;
351 struct p54_scan_body {
352 u8 pa_points_per_curve;
353 u8 val_barker;
354 u8 val_bpsk;
355 u8 val_qpsk;
356 u8 val_16qam;
357 u8 val_64qam;
358 struct p54_pa_curve_data_sample curve_data[8];
359 u8 dup_bpsk;
360 u8 dup_qpsk;
361 u8 dup_16qam;
362 u8 dup_64qam;
363 } __packed;
366 * Warning: Longbow's structures are bogus.
368 struct p54_channel_output_limit_longbow {
369 __le16 rf_power_points[12];
370 } __packed;
372 struct p54_pa_curve_data_sample_longbow {
373 __le16 rf_power;
374 __le16 pa_detector;
375 struct {
376 __le16 data[4];
377 } points[3] __packed;
378 } __packed;
380 struct p54_scan_body_longbow {
381 struct p54_channel_output_limit_longbow power_limits;
382 struct p54_pa_curve_data_sample_longbow curve_data[8];
383 __le16 unkn[6]; /* maybe more power_limits or rate_mask */
384 } __packed;
386 union p54_scan_body_union {
387 struct p54_scan_body normal;
388 struct p54_scan_body_longbow longbow;
389 } __packed;
391 struct p54_scan_tail_rate {
392 __le32 basic_rate_mask;
393 u8 rts_rates[8];
394 } __packed;
396 struct p54_led {
397 __le16 flags;
398 __le16 mask[2];
399 __le16 delay[2];
400 } __packed;
402 struct p54_edcf {
403 u8 flags;
404 u8 slottime;
405 u8 sifs;
406 u8 eofpad;
407 struct p54_edcf_queue_param queue[8];
408 u8 mapping[4];
409 __le16 frameburst;
410 __le16 round_trip_delay;
411 } __packed;
413 struct p54_statistics {
414 __le32 rx_success;
415 __le32 rx_bad_fcs;
416 __le32 rx_abort;
417 __le32 rx_abort_phy;
418 __le32 rts_success;
419 __le32 rts_fail;
420 __le32 tsf32;
421 __le32 airtime;
422 __le32 noise;
423 __le32 sample_noise[8];
424 __le32 sample_cca;
425 __le32 sample_tx;
426 } __packed;
428 struct p54_xbow_synth {
429 __le16 magic1;
430 __le16 magic2;
431 __le16 freq;
432 u32 padding[5];
433 } __packed;
435 struct p54_timer {
436 __le32 interval;
437 } __packed;
439 struct p54_keycache {
440 u8 entry;
441 u8 key_id;
442 u8 mac[ETH_ALEN];
443 u8 padding[2];
444 u8 key_type;
445 u8 key_len;
446 u8 key[24];
447 } __packed;
449 struct p54_burst {
450 u8 flags;
451 u8 queue;
452 u8 backlog;
453 u8 pad;
454 __le16 durations[32];
455 } __packed;
457 struct p54_psm_interval {
458 __le16 interval;
459 __le16 periods;
460 } __packed;
462 #define P54_PSM_CAM 0
463 #define P54_PSM BIT(0)
464 #define P54_PSM_DTIM BIT(1)
465 #define P54_PSM_MCBC BIT(2)
466 #define P54_PSM_CHECKSUM BIT(3)
467 #define P54_PSM_SKIP_MORE_DATA BIT(4)
468 #define P54_PSM_BEACON_TIMEOUT BIT(5)
469 #define P54_PSM_HFOSLEEP BIT(6)
470 #define P54_PSM_AUTOSWITCH_SLEEP BIT(7)
471 #define P54_PSM_LPIT BIT(8)
472 #define P54_PSM_BF_UCAST_SKIP BIT(9)
473 #define P54_PSM_BF_MCAST_SKIP BIT(10)
475 struct p54_psm {
476 __le16 mode;
477 __le16 aid;
478 struct p54_psm_interval intervals[4];
479 u8 beacon_rssi_skip_max;
480 u8 rssi_delta_threshold;
481 u8 nr;
482 u8 exclude[1];
483 } __packed;
485 #define MC_FILTER_ADDRESS_NUM 4
487 struct p54_group_address_table {
488 __le16 filter_enable;
489 __le16 num_address;
490 u8 mac_list[MC_FILTER_ADDRESS_NUM][ETH_ALEN];
491 } __packed;
493 struct p54_txcancel {
494 __le32 req_id;
495 } __packed;
497 struct p54_sta_unlock {
498 u8 addr[ETH_ALEN];
499 u16 padding;
500 } __packed;
502 #define P54_TIM_CLEAR BIT(15)
503 struct p54_tim {
504 u8 count;
505 u8 padding[3];
506 __le16 entry[8];
507 } __packed;
509 struct p54_cce_quiet {
510 __le32 period;
511 } __packed;
513 struct p54_bt_balancer {
514 __le16 prio_thresh;
515 __le16 acl_thresh;
516 } __packed;
518 struct p54_arp_table {
519 __le16 filter_enable;
520 u8 ipv4_addr[4];
521 } __packed;
523 /* LED control */
524 int p54_set_leds(struct p54_common *priv);
525 int p54_init_leds(struct p54_common *priv);
526 void p54_unregister_leds(struct p54_common *priv);
528 /* xmit functions */
529 int p54_tx_80211(struct ieee80211_hw *dev, struct sk_buff *skb);
530 int p54_tx_cancel(struct p54_common *priv, __le32 req_id);
531 void p54_tx(struct p54_common *priv, struct sk_buff *skb);
533 /* synth/phy configuration */
534 int p54_init_xbow_synth(struct p54_common *priv);
535 int p54_scan(struct p54_common *priv, u16 mode, u16 dwell);
537 /* MAC */
538 int p54_sta_unlock(struct p54_common *priv, u8 *addr);
539 int p54_update_beacon_tim(struct p54_common *priv, u16 aid, bool set);
540 int p54_setup_mac(struct p54_common *priv);
541 int p54_set_ps(struct p54_common *priv);
542 int p54_fetch_statistics(struct p54_common *priv);
544 /* e/v DCF setup */
545 int p54_set_edcf(struct p54_common *priv);
547 /* cryptographic engine */
548 int p54_upload_key(struct p54_common *priv, u8 algo, int slot,
549 u8 idx, u8 len, u8 *addr, u8* key);
551 /* eeprom */
552 int p54_download_eeprom(struct p54_common *priv, void *buf,
553 u16 offset, u16 len);
555 /* utility */
556 u8 *p54_find_ie(struct sk_buff *skb, u8 ie);
558 #endif /* LMAC_H */