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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / net / wireless / rtl818x / rtl8180_dev.c
blob16429c49139c2da3953a6d5fef836f2f093b1443
1
2 /*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/etherdevice.h>
22 #include <linux/eeprom_93cx6.h>
23 #include <net/mac80211.h>
24
25 #include "rtl8180.h"
26 #include "rtl8180_rtl8225.h"
27 #include "rtl8180_sa2400.h"
28 #include "rtl8180_max2820.h"
29 #include "rtl8180_grf5101.h"
30
31 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
32 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
33 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
34 MODULE_LICENSE("GPL");
35
36 static struct pci_device_id rtl8180_table[] __devinitdata = {
37 /* rtl8185 */
38 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
39 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
40 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
41
42 /* rtl8180 */
43 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
44 { PCI_DEVICE(0x1799, 0x6001) },
45 { PCI_DEVICE(0x1799, 0x6020) },
46 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
47 { }
48 };
49
50 MODULE_DEVICE_TABLE(pci, rtl8180_table);
51
52 static const struct ieee80211_rate rtl818x_rates[] = {
53 { .bitrate = 10, .hw_value = 0, },
54 { .bitrate = 20, .hw_value = 1, },
55 { .bitrate = 55, .hw_value = 2, },
56 { .bitrate = 110, .hw_value = 3, },
57 { .bitrate = 60, .hw_value = 4, },
58 { .bitrate = 90, .hw_value = 5, },
59 { .bitrate = 120, .hw_value = 6, },
60 { .bitrate = 180, .hw_value = 7, },
61 { .bitrate = 240, .hw_value = 8, },
62 { .bitrate = 360, .hw_value = 9, },
63 { .bitrate = 480, .hw_value = 10, },
64 { .bitrate = 540, .hw_value = 11, },
65 };
66
67 static const struct ieee80211_channel rtl818x_channels[] = {
68 { .center_freq = 2412 },
69 { .center_freq = 2417 },
70 { .center_freq = 2422 },
71 { .center_freq = 2427 },
72 { .center_freq = 2432 },
73 { .center_freq = 2437 },
74 { .center_freq = 2442 },
75 { .center_freq = 2447 },
76 { .center_freq = 2452 },
77 { .center_freq = 2457 },
78 { .center_freq = 2462 },
79 { .center_freq = 2467 },
80 { .center_freq = 2472 },
81 { .center_freq = 2484 },
82 };
83
84
85
86
87 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
88 {
89 struct rtl8180_priv *priv = dev->priv;
90 int i = 10;
91 u32 buf;
92
93 buf = (data << 8) | addr;
94
95 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
96 while (i--) {
97 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
98 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
99 return;
100 }
101 }
102
103 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
104 {
105 struct rtl8180_priv *priv = dev->priv;
106 unsigned int count = 32;
107
108 while (count--) {
109 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
110 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
111 u32 flags = le32_to_cpu(entry->flags);
112
113 if (flags & RTL818X_RX_DESC_FLAG_OWN)
114 return;
115
116 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
117 RTL818X_RX_DESC_FLAG_FOF |
118 RTL818X_RX_DESC_FLAG_RX_ERR)))
119 goto done;
120 else {
121 u32 flags2 = le32_to_cpu(entry->flags2);
122 struct ieee80211_rx_status rx_status = {0};
123 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
124
125 if (unlikely(!new_skb))
126 goto done;
127
128 pci_unmap_single(priv->pdev,
129 *((dma_addr_t *)skb->cb),
130 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
131 skb_put(skb, flags & 0xFFF);
132
133 rx_status.antenna = (flags2 >> 15) & 1;
134 /* TODO: improve signal/rssi reporting */
135 rx_status.qual = flags2 & 0xFF;
136 rx_status.signal = (flags2 >> 8) & 0x7F;
137 /* XXX: is this correct? */
138 rx_status.rate_idx = (flags >> 20) & 0xF;
139 rx_status.freq = dev->conf.channel->center_freq;
140 rx_status.band = dev->conf.channel->band;
141 rx_status.mactime = le64_to_cpu(entry->tsft);
142 rx_status.flag |= RX_FLAG_TSFT;
143 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
144 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
145
146 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
147 ieee80211_rx_irqsafe(dev, skb);
148
149 skb = new_skb;
150 priv->rx_buf[priv->rx_idx] = skb;
151 *((dma_addr_t *) skb->cb) =
152 pci_map_single(priv->pdev, skb_tail_pointer(skb),
153 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
154 }
155
156 done:
157 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
158 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
159 MAX_RX_SIZE);
160 if (priv->rx_idx == 31)
161 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
162 priv->rx_idx = (priv->rx_idx + 1) % 32;
163 }
164 }
165
166 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
167 {
168 struct rtl8180_priv *priv = dev->priv;
169 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
170
171 while (skb_queue_len(&ring->queue)) {
172 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
173 struct sk_buff *skb;
174 struct ieee80211_tx_info *info;
175 u32 flags = le32_to_cpu(entry->flags);
176
177 if (flags & RTL818X_TX_DESC_FLAG_OWN)
178 return;
179
180 ring->idx = (ring->idx + 1) % ring->entries;
181 skb = __skb_dequeue(&ring->queue);
182 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
183 skb->len, PCI_DMA_TODEVICE);
184
185 info = IEEE80211_SKB_CB(skb);
186 ieee80211_tx_info_clear_status(info);
187
188 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
189 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
190 info->flags |= IEEE80211_TX_STAT_ACK;
191
192 info->status.rates[0].count = (flags & 0xFF) + 1;
193
194 ieee80211_tx_status_irqsafe(dev, skb);
195 if (ring->entries - skb_queue_len(&ring->queue) == 2)
196 ieee80211_wake_queue(dev, prio);
197 }
198 }
199
200 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
201 {
202 struct ieee80211_hw *dev = dev_id;
203 struct rtl8180_priv *priv = dev->priv;
204 u16 reg;
205
206 spin_lock(&priv->lock);
207 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
208 if (unlikely(reg == 0xFFFF)) {
209 spin_unlock(&priv->lock);
210 return IRQ_HANDLED;
211 }
212
213 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
214
215 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
216 rtl8180_handle_tx(dev, 3);
217
218 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
219 rtl8180_handle_tx(dev, 2);
220
221 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
222 rtl8180_handle_tx(dev, 1);
223
224 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
225 rtl8180_handle_tx(dev, 0);
226
227 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
228 rtl8180_handle_rx(dev);
229
230 spin_unlock(&priv->lock);
231
232 return IRQ_HANDLED;
233 }
234
235 static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
236 {
237 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
238 struct rtl8180_priv *priv = dev->priv;
239 struct rtl8180_tx_ring *ring;
240 struct rtl8180_tx_desc *entry;
241 unsigned long flags;
242 unsigned int idx, prio;
243 dma_addr_t mapping;
244 u32 tx_flags;
245 u8 rc_flags;
246 u16 plcp_len = 0;
247 __le16 rts_duration = 0;
248
249 prio = skb_get_queue_mapping(skb);
250 ring = &priv->tx_ring[prio];
251
252 mapping = pci_map_single(priv->pdev, skb->data,
253 skb->len, PCI_DMA_TODEVICE);
254
255 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
256 RTL818X_TX_DESC_FLAG_LS |
257 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
258 skb->len;
259
260 if (priv->r8185)
261 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
262 RTL818X_TX_DESC_FLAG_NO_ENC;
263
264 rc_flags = info->control.rates[0].flags;
265 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
266 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
267 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
268 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
269 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
270 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
271 }
272
273 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
274 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
275 info);
276
277 if (!priv->r8185) {
278 unsigned int remainder;
279
280 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
281 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
282 remainder = (16 * (skb->len + 4)) %
283 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
284 if (remainder <= 6)
285 plcp_len |= 1 << 15;
286 }
287
288 spin_lock_irqsave(&priv->lock, flags);
289 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
290 entry = &ring->desc[idx];
291
292 entry->rts_duration = rts_duration;
293 entry->plcp_len = cpu_to_le16(plcp_len);
294 entry->tx_buf = cpu_to_le32(mapping);
295 entry->frame_len = cpu_to_le32(skb->len);
296 entry->flags2 = info->control.rates[1].idx >= 0 ?
297 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
298 entry->retry_limit = info->control.rates[0].count;
299 entry->flags = cpu_to_le32(tx_flags);
300 __skb_queue_tail(&ring->queue, skb);
301 if (ring->entries - skb_queue_len(&ring->queue) < 2)
302 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
303 spin_unlock_irqrestore(&priv->lock, flags);
304
305 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
306
307 return 0;
308 }
309
310 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
311 {
312 u8 reg;
313
314 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
315 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
316 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
317 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
318 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
319 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
320 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
321 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
322 }
323
324 static int rtl8180_init_hw(struct ieee80211_hw *dev)
325 {
326 struct rtl8180_priv *priv = dev->priv;
327 u16 reg;
328
329 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
330 rtl818x_ioread8(priv, &priv->map->CMD);
331 msleep(10);
332
333 /* reset */
334 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
335 rtl818x_ioread8(priv, &priv->map->CMD);
336
337 reg = rtl818x_ioread8(priv, &priv->map->CMD);
338 reg &= (1 << 1);
339 reg |= RTL818X_CMD_RESET;
340 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
341 rtl818x_ioread8(priv, &priv->map->CMD);
342 msleep(200);
343
344 /* check success of reset */
345 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
346 printk(KERN_ERR "%s: reset timeout!\n", wiphy_name(dev->wiphy));
347 return -ETIMEDOUT;
348 }
349
350 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
351 rtl818x_ioread8(priv, &priv->map->CMD);
352 msleep(200);
353
354 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
355 /* For cardbus */
356 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
357 reg |= 1 << 1;
358 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
359 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
360 reg |= (1 << 15) | (1 << 14) | (1 << 4);
361 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
362 }
363
364 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
365
366 if (!priv->r8185)
367 rtl8180_set_anaparam(priv, priv->anaparam);
368
369 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
370 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
371 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
372 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
373 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
374
375 /* TODO: necessary? specs indicate not */
376 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
377 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
378 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
379 if (priv->r8185) {
380 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
381 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
382 }
383 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
384
385 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
386
387 /* TODO: turn off hw wep on rtl8180 */
388
389 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
390
391 if (priv->r8185) {
392 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
393 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
394 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
395
396 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
397
398 /* TODO: set ClkRun enable? necessary? */
399 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
400 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
401 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
402 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
403 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
404 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
405 } else {
406 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
407 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
408
409 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
410 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
411 }
412
413 priv->rf->init(dev);
414 if (priv->r8185)
415 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
416 return 0;
417 }
418
419 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
420 {
421 struct rtl8180_priv *priv = dev->priv;
422 struct rtl8180_rx_desc *entry;
423 int i;
424
425 priv->rx_ring = pci_alloc_consistent(priv->pdev,
426 sizeof(*priv->rx_ring) * 32,
427 &priv->rx_ring_dma);
428
429 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
430 printk(KERN_ERR "%s: Cannot allocate RX ring\n",
431 wiphy_name(dev->wiphy));
432 return -ENOMEM;
433 }
434
435 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
436 priv->rx_idx = 0;
437
438 for (i = 0; i < 32; i++) {
439 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
440 dma_addr_t *mapping;
441 entry = &priv->rx_ring[i];
442 if (!skb)
443 return 0;
444
445 priv->rx_buf[i] = skb;
446 mapping = (dma_addr_t *)skb->cb;
447 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
448 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
449 entry->rx_buf = cpu_to_le32(*mapping);
450 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
451 MAX_RX_SIZE);
452 }
453 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
454 return 0;
455 }
456
457 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
458 {
459 struct rtl8180_priv *priv = dev->priv;
460 int i;
461
462 for (i = 0; i < 32; i++) {
463 struct sk_buff *skb = priv->rx_buf[i];
464 if (!skb)
465 continue;
466
467 pci_unmap_single(priv->pdev,
468 *((dma_addr_t *)skb->cb),
469 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
470 kfree_skb(skb);
471 }
472
473 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
474 priv->rx_ring, priv->rx_ring_dma);
475 priv->rx_ring = NULL;
476 }
477
478 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
479 unsigned int prio, unsigned int entries)
480 {
481 struct rtl8180_priv *priv = dev->priv;
482 struct rtl8180_tx_desc *ring;
483 dma_addr_t dma;
484 int i;
485
486 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
487 if (!ring || (unsigned long)ring & 0xFF) {
488 printk(KERN_ERR "%s: Cannot allocate TX ring (prio = %d)\n",
489 wiphy_name(dev->wiphy), prio);
490 return -ENOMEM;
491 }
492
493 memset(ring, 0, sizeof(*ring)*entries);
494 priv->tx_ring[prio].desc = ring;
495 priv->tx_ring[prio].dma = dma;
496 priv->tx_ring[prio].idx = 0;
497 priv->tx_ring[prio].entries = entries;
498 skb_queue_head_init(&priv->tx_ring[prio].queue);
499
500 for (i = 0; i < entries; i++)
501 ring[i].next_tx_desc =
502 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
503
504 return 0;
505 }
506
507 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
508 {
509 struct rtl8180_priv *priv = dev->priv;
510 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
511
512 while (skb_queue_len(&ring->queue)) {
513 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
514 struct sk_buff *skb = __skb_dequeue(&ring->queue);
515
516 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
517 skb->len, PCI_DMA_TODEVICE);
518 kfree_skb(skb);
519 ring->idx = (ring->idx + 1) % ring->entries;
520 }
521
522 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
523 ring->desc, ring->dma);
524 ring->desc = NULL;
525 }
526
527 static int rtl8180_start(struct ieee80211_hw *dev)
528 {
529 struct rtl8180_priv *priv = dev->priv;
530 int ret, i;
531 u32 reg;
532
533 ret = rtl8180_init_rx_ring(dev);
534 if (ret)
535 return ret;
536
537 for (i = 0; i < 4; i++)
538 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
539 goto err_free_rings;
540
541 ret = rtl8180_init_hw(dev);
542 if (ret)
543 goto err_free_rings;
544
545 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
546 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
547 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
548 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
549 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
550
551 ret = request_irq(priv->pdev->irq, &rtl8180_interrupt,
552 IRQF_SHARED, KBUILD_MODNAME, dev);
553 if (ret) {
554 printk(KERN_ERR "%s: failed to register IRQ handler\n",
555 wiphy_name(dev->wiphy));
556 goto err_free_rings;
557 }
558
559 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
560
561 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
562 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
563
564 reg = RTL818X_RX_CONF_ONLYERLPKT |
565 RTL818X_RX_CONF_RX_AUTORESETPHY |
566 RTL818X_RX_CONF_MGMT |
567 RTL818X_RX_CONF_DATA |
568 (7 << 8 /* MAX RX DMA */) |
569 RTL818X_RX_CONF_BROADCAST |
570 RTL818X_RX_CONF_NICMAC;
571
572 if (priv->r8185)
573 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
574 else {
575 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
576 ? RTL818X_RX_CONF_CSDM1 : 0;
577 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
578 ? RTL818X_RX_CONF_CSDM2 : 0;
579 }
580
581 priv->rx_conf = reg;
582 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
583
584 if (priv->r8185) {
585 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
586 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
587 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
588 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
589
590 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
591 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
592 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
593 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
594 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
595
596 /* disable early TX */
597 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
598 }
599
600 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
601 reg |= (6 << 21 /* MAX TX DMA */) |
602 RTL818X_TX_CONF_NO_ICV;
603
604 if (priv->r8185)
605 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
606 else
607 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
608
609 /* different meaning, same value on both rtl8185 and rtl8180 */
610 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
611
612 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
613
614 reg = rtl818x_ioread8(priv, &priv->map->CMD);
615 reg |= RTL818X_CMD_RX_ENABLE;
616 reg |= RTL818X_CMD_TX_ENABLE;
617 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
618
619 priv->mode = NL80211_IFTYPE_MONITOR;
620 return 0;
621
622 err_free_rings:
623 rtl8180_free_rx_ring(dev);
624 for (i = 0; i < 4; i++)
625 if (priv->tx_ring[i].desc)
626 rtl8180_free_tx_ring(dev, i);
627
628 return ret;
629 }
630
631 static void rtl8180_stop(struct ieee80211_hw *dev)
632 {
633 struct rtl8180_priv *priv = dev->priv;
634 u8 reg;
635 int i;
636
637 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
638
639 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
640
641 reg = rtl818x_ioread8(priv, &priv->map->CMD);
642 reg &= ~RTL818X_CMD_TX_ENABLE;
643 reg &= ~RTL818X_CMD_RX_ENABLE;
644 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
645
646 priv->rf->stop(dev);
647
648 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
649 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
650 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
651 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
652
653 free_irq(priv->pdev->irq, dev);
654
655 rtl8180_free_rx_ring(dev);
656 for (i = 0; i < 4; i++)
657 rtl8180_free_tx_ring(dev, i);
658 }
659
660 static int rtl8180_add_interface(struct ieee80211_hw *dev,
661 struct ieee80211_if_init_conf *conf)
662 {
663 struct rtl8180_priv *priv = dev->priv;
664
665 if (priv->mode != NL80211_IFTYPE_MONITOR)
666 return -EOPNOTSUPP;
667
668 switch (conf->type) {
669 case NL80211_IFTYPE_STATION:
670 priv->mode = conf->type;
671 break;
672 default:
673 return -EOPNOTSUPP;
674 }
675
676 priv->vif = conf->vif;
677
678 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
679 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
680 le32_to_cpu(*(__le32 *)conf->mac_addr));
681 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
682 le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
683 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
684
685 return 0;
686 }
687
688 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
689 struct ieee80211_if_init_conf *conf)
690 {
691 struct rtl8180_priv *priv = dev->priv;
692 priv->mode = NL80211_IFTYPE_MONITOR;
693 priv->vif = NULL;
694 }
695
696 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
697 {
698 struct rtl8180_priv *priv = dev->priv;
699 struct ieee80211_conf *conf = &dev->conf;
700
701 priv->rf->set_chan(dev, conf);
702
703 return 0;
704 }
705
706 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
707 struct ieee80211_vif *vif,
708 struct ieee80211_bss_conf *info,
709 u32 changed)
710 {
711 struct rtl8180_priv *priv = dev->priv;
712 int i;
713
714 if (changed & BSS_CHANGED_BSSID) {
715 for (i = 0; i < ETH_ALEN; i++)
716 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
717 info->bssid[i]);
718
719 if (is_valid_ether_addr(info->bssid))
720 rtl818x_iowrite8(priv, &priv->map->MSR,
721 RTL818X_MSR_INFRA);
722 else
723 rtl818x_iowrite8(priv, &priv->map->MSR,
724 RTL818X_MSR_NO_LINK);
725 }
726
727 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
728 priv->rf->conf_erp(dev, info);
729 }
730
731 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev, int mc_count,
732 struct dev_addr_list *mc_list)
733 {
734 return mc_count;
735 }
736
737 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
738 unsigned int changed_flags,
739 unsigned int *total_flags,
740 u64 multicast)
741 {
742 struct rtl8180_priv *priv = dev->priv;
743
744 if (changed_flags & FIF_FCSFAIL)
745 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
746 if (changed_flags & FIF_CONTROL)
747 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
748 if (changed_flags & FIF_OTHER_BSS)
749 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
750 if (*total_flags & FIF_ALLMULTI || multicast > 0)
751 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
752 else
753 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
754
755 *total_flags = 0;
756
757 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
758 *total_flags |= FIF_FCSFAIL;
759 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
760 *total_flags |= FIF_CONTROL;
761 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
762 *total_flags |= FIF_OTHER_BSS;
763 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
764 *total_flags |= FIF_ALLMULTI;
765
766 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
767 }
768
769 static const struct ieee80211_ops rtl8180_ops = {
770 .tx = rtl8180_tx,
771 .start = rtl8180_start,
772 .stop = rtl8180_stop,
773 .add_interface = rtl8180_add_interface,
774 .remove_interface = rtl8180_remove_interface,
775 .config = rtl8180_config,
776 .bss_info_changed = rtl8180_bss_info_changed,
777 .prepare_multicast = rtl8180_prepare_multicast,
778 .configure_filter = rtl8180_configure_filter,
779 };
780
781 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
782 {
783 struct ieee80211_hw *dev = eeprom->data;
784 struct rtl8180_priv *priv = dev->priv;
785 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
786
787 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
788 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
789 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
790 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
791 }
792
793 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
794 {
795 struct ieee80211_hw *dev = eeprom->data;
796 struct rtl8180_priv *priv = dev->priv;
797 u8 reg = 2 << 6;
798
799 if (eeprom->reg_data_in)
800 reg |= RTL818X_EEPROM_CMD_WRITE;
801 if (eeprom->reg_data_out)
802 reg |= RTL818X_EEPROM_CMD_READ;
803 if (eeprom->reg_data_clock)
804 reg |= RTL818X_EEPROM_CMD_CK;
805 if (eeprom->reg_chip_select)
806 reg |= RTL818X_EEPROM_CMD_CS;
807
808 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
809 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
810 udelay(10);
811 }
812
813 static int __devinit rtl8180_probe(struct pci_dev *pdev,
814 const struct pci_device_id *id)
815 {
816 struct ieee80211_hw *dev;
817 struct rtl8180_priv *priv;
818 unsigned long mem_addr, mem_len;
819 unsigned int io_addr, io_len;
820 int err, i;
821 struct eeprom_93cx6 eeprom;
822 const char *chip_name, *rf_name = NULL;
823 u32 reg;
824 u16 eeprom_val;
825
826 err = pci_enable_device(pdev);
827 if (err) {
828 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
829 pci_name(pdev));
830 return err;
831 }
832
833 err = pci_request_regions(pdev, KBUILD_MODNAME);
834 if (err) {
835 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
836 pci_name(pdev));
837 return err;
838 }
839
840 io_addr = pci_resource_start(pdev, 0);
841 io_len = pci_resource_len(pdev, 0);
842 mem_addr = pci_resource_start(pdev, 1);
843 mem_len = pci_resource_len(pdev, 1);
844
845 if (mem_len < sizeof(struct rtl818x_csr) ||
846 io_len < sizeof(struct rtl818x_csr)) {
847 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
848 pci_name(pdev));
849 err = -ENOMEM;
850 goto err_free_reg;
851 }
852
853 if ((err = pci_set_dma_mask(pdev, 0xFFFFFF00ULL)) ||
854 (err = pci_set_consistent_dma_mask(pdev, 0xFFFFFF00ULL))) {
855 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
856 pci_name(pdev));
857 goto err_free_reg;
858 }
859
860 pci_set_master(pdev);
861
862 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
863 if (!dev) {
864 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
865 pci_name(pdev));
866 err = -ENOMEM;
867 goto err_free_reg;
868 }
869
870 priv = dev->priv;
871 priv->pdev = pdev;
872
873 dev->max_rates = 2;
874 SET_IEEE80211_DEV(dev, &pdev->dev);
875 pci_set_drvdata(pdev, dev);
876
877 priv->map = pci_iomap(pdev, 1, mem_len);
878 if (!priv->map)
879 priv->map = pci_iomap(pdev, 0, io_len);
880
881 if (!priv->map) {
882 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
883 pci_name(pdev));
884 goto err_free_dev;
885 }
886
887 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
888 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
889
890 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
891 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
892
893 priv->band.band = IEEE80211_BAND_2GHZ;
894 priv->band.channels = priv->channels;
895 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
896 priv->band.bitrates = priv->rates;
897 priv->band.n_bitrates = 4;
898 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
899
900 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
901 IEEE80211_HW_RX_INCLUDES_FCS |
902 IEEE80211_HW_SIGNAL_UNSPEC;
903 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
904 dev->queues = 1;
905 dev->max_signal = 65;
906
907 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
908 reg &= RTL818X_TX_CONF_HWVER_MASK;
909 switch (reg) {
910 case RTL818X_TX_CONF_R8180_ABCD:
911 chip_name = "RTL8180";
912 break;
913 case RTL818X_TX_CONF_R8180_F:
914 chip_name = "RTL8180vF";
915 break;
916 case RTL818X_TX_CONF_R8185_ABC:
917 chip_name = "RTL8185";
918 break;
919 case RTL818X_TX_CONF_R8185_D:
920 chip_name = "RTL8185vD";
921 break;
922 default:
923 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
924 pci_name(pdev), reg >> 25);
925 goto err_iounmap;
926 }
927
928 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
929 if (priv->r8185) {
930 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
931 pci_try_set_mwi(pdev);
932 }
933
934 eeprom.data = dev;
935 eeprom.register_read = rtl8180_eeprom_register_read;
936 eeprom.register_write = rtl8180_eeprom_register_write;
937 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
938 eeprom.width = PCI_EEPROM_WIDTH_93C66;
939 else
940 eeprom.width = PCI_EEPROM_WIDTH_93C46;
941
942 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
943 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
944 udelay(10);
945
946 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
947 eeprom_val &= 0xFF;
948 switch (eeprom_val) {
949 case 1: rf_name = "Intersil";
950 break;
951 case 2: rf_name = "RFMD";
952 break;
953 case 3: priv->rf = &sa2400_rf_ops;
954 break;
955 case 4: priv->rf = &max2820_rf_ops;
956 break;
957 case 5: priv->rf = &grf5101_rf_ops;
958 break;
959 case 9: priv->rf = rtl8180_detect_rf(dev);
960 break;
961 case 10:
962 rf_name = "RTL8255";
963 break;
964 default:
965 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
966 pci_name(pdev), eeprom_val);
967 goto err_iounmap;
968 }
969
970 if (!priv->rf) {
971 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
972 pci_name(pdev), rf_name);
973 goto err_iounmap;
974 }
975
976 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
977 priv->csthreshold = eeprom_val >> 8;
978 if (!priv->r8185) {
979 __le32 anaparam;
980 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
981 priv->anaparam = le32_to_cpu(anaparam);
982 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
983 }
984
985 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)dev->wiphy->perm_addr, 3);
986 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
987 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
988 " randomly generated MAC addr\n", pci_name(pdev));
989 random_ether_addr(dev->wiphy->perm_addr);
990 }
991
992 /* CCK TX power */
993 for (i = 0; i < 14; i += 2) {
994 u16 txpwr;
995 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
996 priv->channels[i].hw_value = txpwr & 0xFF;
997 priv->channels[i + 1].hw_value = txpwr >> 8;
998 }
999
1000 /* OFDM TX power */
1001 if (priv->r8185) {
1002 for (i = 0; i < 14; i += 2) {
1003 u16 txpwr;
1004 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1005 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1006 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1007 }
1008 }
1009
1010 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1011
1012 spin_lock_init(&priv->lock);
1013
1014 err = ieee80211_register_hw(dev);
1015 if (err) {
1016 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1017 pci_name(pdev));
1018 goto err_iounmap;
1019 }
1020
1021 printk(KERN_INFO "%s: hwaddr %pM, %s + %s\n",
1022 wiphy_name(dev->wiphy), dev->wiphy->perm_addr,
1023 chip_name, priv->rf->name);
1024
1025 return 0;
1026
1027 err_iounmap:
1028 iounmap(priv->map);
1029
1030 err_free_dev:
1031 pci_set_drvdata(pdev, NULL);
1032 ieee80211_free_hw(dev);
1033
1034 err_free_reg:
1035 pci_release_regions(pdev);
1036 pci_disable_device(pdev);
1037 return err;
1038 }
1039
1040 static void __devexit rtl8180_remove(struct pci_dev *pdev)
1041 {
1042 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1043 struct rtl8180_priv *priv;
1044
1045 if (!dev)
1046 return;
1047
1048 ieee80211_unregister_hw(dev);
1049
1050 priv = dev->priv;
1051
1052 pci_iounmap(pdev, priv->map);
1053 pci_release_regions(pdev);
1054 pci_disable_device(pdev);
1055 ieee80211_free_hw(dev);
1056 }
1057
1058 #ifdef CONFIG_PM
1059 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1060 {
1061 pci_save_state(pdev);
1062 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1063 return 0;
1064 }
1065
1066 static int rtl8180_resume(struct pci_dev *pdev)
1067 {
1068 pci_set_power_state(pdev, PCI_D0);
1069 pci_restore_state(pdev);
1070 return 0;
1071 }
1072
1073 #endif /* CONFIG_PM */
1074
1075 static struct pci_driver rtl8180_driver = {
1076 .name = KBUILD_MODNAME,
1077 .id_table = rtl8180_table,
1078 .probe = rtl8180_probe,
1079 .remove = __devexit_p(rtl8180_remove),
1080 #ifdef CONFIG_PM
1081 .suspend = rtl8180_suspend,
1082 .resume = rtl8180_resume,
1083 #endif /* CONFIG_PM */
1084 };
1085
1086 static int __init rtl8180_init(void)
1087 {
1088 return pci_register_driver(&rtl8180_driver);
1089 }
1090
1091 static void __exit rtl8180_exit(void)
1092 {
1093 pci_unregister_driver(&rtl8180_driver);
1094 }
1095
1096 module_init(rtl8180_init);
1097 module_exit(rtl8180_exit);
Verdex Pro support