drivers/net/wireless/zd1211rw/zd_rf_uw2453.c

   1 /* ZD1211 USB-WLAN driver for Linux
   2  *
   3  * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
   4  * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19  */
  20
  21 #include <linux/kernel.h>
  22
  23 #include "zd_rf.h"
  24 #include "zd_usb.h"
  25 #include "zd_chip.h"
  26
  27 /* This RF programming code is based upon the code found in v2.16.0.0 of the
  28  * ZyDAS vendor driver. Unlike other RF's, Ubec publish full technical specs
  29  * for this RF on their website, so we're able to understand more than
  30  * usual as to what is going on. Thumbs up for Ubec for doing that. */
  31
  32 /* The 3-wire serial interface provides access to 8 write-only registers.
  33  * The data format is a 4 bit register address followed by a 20 bit value. */
  34 #define UW2453_REGWRITE(reg, val) ((((reg) & 0xf) << 20) | ((val) & 0xfffff))
  35
  36 /* For channel tuning, we have to configure registers 1 (synthesizer), 2 (synth
  37  * fractional divide ratio) and 3 (VCO config).
  38  *
  39  * We configure the RF to produce an interrupt when the PLL is locked onto
  40  * the configured frequency. During initialization, we run through a variety
  41  * of different VCO configurations on channel 1 until we detect a PLL lock.
  42  * When this happens, we remember which VCO configuration produced the lock
  43  * and use it later. Actually, we use the configuration *after* the one that
  44  * produced the lock, which seems odd, but it works.
  45  *
  46  * If we do not see a PLL lock on any standard VCO config, we fall back on an
  47  * autocal configuration, which has a fixed (as opposed to per-channel) VCO
  48  * config and different synth values from the standard set (divide ratio
  49  * is still shared with the standard set). */
  50
  51 /* The per-channel synth values for all standard VCO configurations. These get
  52  * written to register 1. */
  53 static const u8 uw2453_std_synth[] = {
  54         RF_CHANNEL( 1) = 0x47,
  55         RF_CHANNEL( 2) = 0x47,
  56         RF_CHANNEL( 3) = 0x67,
  57         RF_CHANNEL( 4) = 0x67,
  58         RF_CHANNEL( 5) = 0x67,
  59         RF_CHANNEL( 6) = 0x67,
  60         RF_CHANNEL( 7) = 0x57,
  61         RF_CHANNEL( 8) = 0x57,
  62         RF_CHANNEL( 9) = 0x57,
  63         RF_CHANNEL(10) = 0x57,
  64         RF_CHANNEL(11) = 0x77,
  65         RF_CHANNEL(12) = 0x77,
  66         RF_CHANNEL(13) = 0x77,
  67         RF_CHANNEL(14) = 0x4f,
  68 };
  69
  70 /* This table stores the synthesizer fractional divide ratio for *all* VCO
  71  * configurations (both standard and autocal). These get written to register 2.
  72  */
  73 static const u16 uw2453_synth_divide[] = {
  74         RF_CHANNEL( 1) = 0x999,
  75         RF_CHANNEL( 2) = 0x99b,
  76         RF_CHANNEL( 3) = 0x998,
  77         RF_CHANNEL( 4) = 0x99a,
  78         RF_CHANNEL( 5) = 0x999,
  79         RF_CHANNEL( 6) = 0x99b,
  80         RF_CHANNEL( 7) = 0x998,
  81         RF_CHANNEL( 8) = 0x99a,
  82         RF_CHANNEL( 9) = 0x999,
  83         RF_CHANNEL(10) = 0x99b,
  84         RF_CHANNEL(11) = 0x998,
  85         RF_CHANNEL(12) = 0x99a,
  86         RF_CHANNEL(13) = 0x999,
  87         RF_CHANNEL(14) = 0xccc,
  88 };
  89
  90 /* Here is the data for all the standard VCO configurations. We shrink our
  91  * table a little by observing that both channels in a consecutive pair share
  92  * the same value. We also observe that the high 4 bits ([0:3] in the specs)
  93  * are all 'Reserved' and are always set to 0x4 - we chop them off in the data
  94  * below. */
  95 #define CHAN_TO_PAIRIDX(a) ((a - 1) / 2)
  96 #define RF_CHANPAIR(a,b) [CHAN_TO_PAIRIDX(a)]
  97 static const u16 uw2453_std_vco_cfg[][7] = {
  98         { /* table 1 */
  99                 RF_CHANPAIR( 1,  2) = 0x664d,
 100                 RF_CHANPAIR( 3,  4) = 0x604d,
 101                 RF_CHANPAIR( 5,  6) = 0x6675,
 102                 RF_CHANPAIR( 7,  8) = 0x6475,
 103                 RF_CHANPAIR( 9, 10) = 0x6655,
 104                 RF_CHANPAIR(11, 12) = 0x6455,
 105                 RF_CHANPAIR(13, 14) = 0x6665,
 106         },
 107         { /* table 2 */
 108                 RF_CHANPAIR( 1,  2) = 0x666d,
 109                 RF_CHANPAIR( 3,  4) = 0x606d,
 110                 RF_CHANPAIR( 5,  6) = 0x664d,
 111                 RF_CHANPAIR( 7,  8) = 0x644d,
 112                 RF_CHANPAIR( 9, 10) = 0x6675,
 113                 RF_CHANPAIR(11, 12) = 0x6475,
 114                 RF_CHANPAIR(13, 14) = 0x6655,
 115         },
 116         { /* table 3 */
 117                 RF_CHANPAIR( 1,  2) = 0x665d,
 118                 RF_CHANPAIR( 3,  4) = 0x605d,
 119                 RF_CHANPAIR( 5,  6) = 0x666d,
 120                 RF_CHANPAIR( 7,  8) = 0x646d,
 121                 RF_CHANPAIR( 9, 10) = 0x664d,
 122                 RF_CHANPAIR(11, 12) = 0x644d,
 123                 RF_CHANPAIR(13, 14) = 0x6675,
 124         },
 125         { /* table 4 */
 126                 RF_CHANPAIR( 1,  2) = 0x667d,
 127                 RF_CHANPAIR( 3,  4) = 0x607d,
 128                 RF_CHANPAIR( 5,  6) = 0x665d,
 129                 RF_CHANPAIR( 7,  8) = 0x645d,
 130                 RF_CHANPAIR( 9, 10) = 0x666d,
 131                 RF_CHANPAIR(11, 12) = 0x646d,
 132                 RF_CHANPAIR(13, 14) = 0x664d,
 133         },
 134         { /* table 5 */
 135                 RF_CHANPAIR( 1,  2) = 0x6643,
 136                 RF_CHANPAIR( 3,  4) = 0x6043,
 137                 RF_CHANPAIR( 5,  6) = 0x667d,
 138                 RF_CHANPAIR( 7,  8) = 0x647d,
 139                 RF_CHANPAIR( 9, 10) = 0x665d,
 140                 RF_CHANPAIR(11, 12) = 0x645d,
 141                 RF_CHANPAIR(13, 14) = 0x666d,
 142         },
 143         { /* table 6 */
 144                 RF_CHANPAIR( 1,  2) = 0x6663,
 145                 RF_CHANPAIR( 3,  4) = 0x6063,
 146                 RF_CHANPAIR( 5,  6) = 0x6643,
 147                 RF_CHANPAIR( 7,  8) = 0x6443,
 148                 RF_CHANPAIR( 9, 10) = 0x667d,
 149                 RF_CHANPAIR(11, 12) = 0x647d,
 150                 RF_CHANPAIR(13, 14) = 0x665d,
 151         },
 152         { /* table 7 */
 153                 RF_CHANPAIR( 1,  2) = 0x6653,
 154                 RF_CHANPAIR( 3,  4) = 0x6053,
 155                 RF_CHANPAIR( 5,  6) = 0x6663,
 156                 RF_CHANPAIR( 7,  8) = 0x6463,
 157                 RF_CHANPAIR( 9, 10) = 0x6643,
 158                 RF_CHANPAIR(11, 12) = 0x6443,
 159                 RF_CHANPAIR(13, 14) = 0x667d,
 160         },
 161         { /* table 8 */
 162                 RF_CHANPAIR( 1,  2) = 0x6673,
 163                 RF_CHANPAIR( 3,  4) = 0x6073,
 164                 RF_CHANPAIR( 5,  6) = 0x6653,
 165                 RF_CHANPAIR( 7,  8) = 0x6453,
 166                 RF_CHANPAIR( 9, 10) = 0x6663,
 167                 RF_CHANPAIR(11, 12) = 0x6463,
 168                 RF_CHANPAIR(13, 14) = 0x6643,
 169         },
 170         { /* table 9 */
 171                 RF_CHANPAIR( 1,  2) = 0x664b,
 172                 RF_CHANPAIR( 3,  4) = 0x604b,
 173                 RF_CHANPAIR( 5,  6) = 0x6673,
 174                 RF_CHANPAIR( 7,  8) = 0x6473,
 175                 RF_CHANPAIR( 9, 10) = 0x6653,
 176                 RF_CHANPAIR(11, 12) = 0x6453,
 177                 RF_CHANPAIR(13, 14) = 0x6663,
 178         },
 179         { /* table 10 */
 180                 RF_CHANPAIR( 1,  2) = 0x666b,
 181                 RF_CHANPAIR( 3,  4) = 0x606b,
 182                 RF_CHANPAIR( 5,  6) = 0x664b,
 183                 RF_CHANPAIR( 7,  8) = 0x644b,
 184                 RF_CHANPAIR( 9, 10) = 0x6673,
 185                 RF_CHANPAIR(11, 12) = 0x6473,
 186                 RF_CHANPAIR(13, 14) = 0x6653,
 187         },
 188         { /* table 11 */
 189                 RF_CHANPAIR( 1,  2) = 0x665b,
 190                 RF_CHANPAIR( 3,  4) = 0x605b,
 191                 RF_CHANPAIR( 5,  6) = 0x666b,
 192                 RF_CHANPAIR( 7,  8) = 0x646b,
 193                 RF_CHANPAIR( 9, 10) = 0x664b,
 194                 RF_CHANPAIR(11, 12) = 0x644b,
 195                 RF_CHANPAIR(13, 14) = 0x6673,
 196         },
 197
 198 };
 199
 200 /* The per-channel synth values for autocal. These get written to register 1. */
 201 static const u16 uw2453_autocal_synth[] = {
 202         RF_CHANNEL( 1) = 0x6847,
 203         RF_CHANNEL( 2) = 0x6847,
 204         RF_CHANNEL( 3) = 0x6867,
 205         RF_CHANNEL( 4) = 0x6867,
 206         RF_CHANNEL( 5) = 0x6867,
 207         RF_CHANNEL( 6) = 0x6867,
 208         RF_CHANNEL( 7) = 0x6857,
 209         RF_CHANNEL( 8) = 0x6857,
 210         RF_CHANNEL( 9) = 0x6857,
 211         RF_CHANNEL(10) = 0x6857,
 212         RF_CHANNEL(11) = 0x6877,
 213         RF_CHANNEL(12) = 0x6877,
 214         RF_CHANNEL(13) = 0x6877,
 215         RF_CHANNEL(14) = 0x684f,
 216 };
 217
 218 /* The VCO configuration for autocal (all channels) */
 219 static const u16 UW2453_AUTOCAL_VCO_CFG = 0x6662;
 220
 221 /* TX gain settings. The array index corresponds to the TX power integration
 222  * values found in the EEPROM. The values get written to register 7. */
 223 static u32 uw2453_txgain[] = {
 224         [0x00] = 0x0e313,
 225         [0x01] = 0x0fb13,
 226         [0x02] = 0x0e093,
 227         [0x03] = 0x0f893,
 228         [0x04] = 0x0ea93,
 229         [0x05] = 0x1f093,
 230         [0x06] = 0x1f493,
 231         [0x07] = 0x1f693,
 232         [0x08] = 0x1f393,
 233         [0x09] = 0x1f35b,
 234         [0x0a] = 0x1e6db,
 235         [0x0b] = 0x1ff3f,
 236         [0x0c] = 0x1ffff,
 237         [0x0d] = 0x361d7,
 238         [0x0e] = 0x37fbf,
 239         [0x0f] = 0x3ff8b,
 240         [0x10] = 0x3ff33,
 241         [0x11] = 0x3fb3f,
 242         [0x12] = 0x3ffff,
 243 };
 244
 245 /* RF-specific structure */
 246 struct uw2453_priv {
 247         /* index into synth/VCO config tables where PLL lock was found
 248          * -1 means autocal */
 249         int config;
 250 };
 251
 252 #define UW2453_PRIV(rf) ((struct uw2453_priv *) (rf)->priv)
 253
 254 static int uw2453_synth_set_channel(struct zd_chip *chip, int channel,
 255         bool autocal)
 256 {
 257         int r;
 258         int idx = channel - 1;
 259         u32 val;
 260
 261         if (autocal)
 262                 val = UW2453_REGWRITE(1, uw2453_autocal_synth[idx]);
 263         else
 264                 val = UW2453_REGWRITE(1, uw2453_std_synth[idx]);
 265
 266         r = zd_rfwrite_locked(chip, val, RF_RV_BITS);
 267         if (r)
 268                 return r;
 269
 270         return zd_rfwrite_locked(chip,
 271                 UW2453_REGWRITE(2, uw2453_synth_divide[idx]), RF_RV_BITS);
 272 }
 273
 274 static int uw2453_write_vco_cfg(struct zd_chip *chip, u16 value)
 275 {
 276         /* vendor driver always sets these upper bits even though the specs say
 277          * they are reserved */
 278         u32 val = 0x40000 | value;
 279         return zd_rfwrite_locked(chip, UW2453_REGWRITE(3, val), RF_RV_BITS);
 280 }
 281
 282 static int uw2453_init_mode(struct zd_chip *chip)
 283 {
 284         static const u32 rv[] = {
 285                 UW2453_REGWRITE(0, 0x25f98), /* enter IDLE mode */
 286                 UW2453_REGWRITE(0, 0x25f9a), /* enter CAL_VCO mode */
 287                 UW2453_REGWRITE(0, 0x25f94), /* enter RX/TX mode */
 288                 UW2453_REGWRITE(0, 0x27fd4), /* power down RSSI circuit */
 289         };
 290
 291         return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
 292 }
 293
 294 static int uw2453_set_tx_gain_level(struct zd_chip *chip, int channel)
 295 {
 296         u8 int_value = chip->pwr_int_values[channel - 1];
 297
 298         if (int_value >= ARRAY_SIZE(uw2453_txgain)) {
 299                 dev_dbg_f(zd_chip_dev(chip), "can't configure TX gain for "
 300                           "int value %x on channel %d\n", int_value, channel);
 301                 return 0;
 302         }
 303
 304         return zd_rfwrite_locked(chip,
 305                 UW2453_REGWRITE(7, uw2453_txgain[int_value]), RF_RV_BITS);
 306 }
 307
 308 static int uw2453_init_hw(struct zd_rf *rf)
 309 {
 310         int i, r;
 311         int found_config = -1;
 312         u16 intr_status;
 313         struct zd_chip *chip = zd_rf_to_chip(rf);
 314
 315         static const struct zd_ioreq16 ioreqs[] = {
 316                 { CR10,  0x89 }, { CR15,  0x20 },
 317                 { CR17,  0x28 }, /* 6112 no change */
 318                 { CR23,  0x38 }, { CR24,  0x20 }, { CR26,  0x93 },
 319                 { CR27,  0x15 }, { CR28,  0x3e }, { CR29,  0x00 },
 320                 { CR33,  0x28 }, { CR34,  0x30 },
 321                 { CR35,  0x43 }, /* 6112 3e->43 */
 322                 { CR41,  0x24 }, { CR44,  0x32 },
 323                 { CR46,  0x92 }, /* 6112 96->92 */
 324                 { CR47,  0x1e },
 325                 { CR48,  0x04 }, /* 5602 Roger */
 326                 { CR49,  0xfa }, { CR79,  0x58 }, { CR80,  0x30 },
 327                 { CR81,  0x30 }, { CR87,  0x0a }, { CR89,  0x04 },
 328                 { CR91,  0x00 }, { CR92,  0x0a }, { CR98,  0x8d },
 329                 { CR99,  0x28 }, { CR100, 0x02 },
 330                 { CR101, 0x09 }, /* 6112 13->1f 6220 1f->13 6407 13->9 */
 331                 { CR102, 0x27 },
 332                 { CR106, 0x1c }, /* 5d07 5112 1f->1c 6220 1c->1f 6221 1f->1c */
 333                 { CR107, 0x1c }, /* 6220 1c->1a 5221 1a->1c */
 334                 { CR109, 0x13 },
 335                 { CR110, 0x1f }, /* 6112 13->1f 6221 1f->13 6407 13->0x09 */
 336                 { CR111, 0x13 }, { CR112, 0x1f }, { CR113, 0x27 },
 337                 { CR114, 0x23 }, /* 6221 27->23 */
 338                 { CR115, 0x24 }, /* 6112 24->1c 6220 1c->24 */
 339                 { CR116, 0x24 }, /* 6220 1c->24 */
 340                 { CR117, 0xfa }, /* 6112 fa->f8 6220 f8->f4 6220 f4->fa */
 341                 { CR118, 0xf0 }, /* 5d07 6112 f0->f2 6220 f2->f0 */
 342                 { CR119, 0x1a }, /* 6112 1a->10 6220 10->14 6220 14->1a */
 343                 { CR120, 0x4f },
 344                 { CR121, 0x1f }, /* 6220 4f->1f */
 345                 { CR122, 0xf0 }, { CR123, 0x57 }, { CR125, 0xad },
 346                 { CR126, 0x6c }, { CR127, 0x03 },
 347                 { CR128, 0x14 }, /* 6302 12->11 */
 348                 { CR129, 0x12 }, /* 6301 10->0f */
 349                 { CR130, 0x10 }, { CR137, 0x50 }, { CR138, 0xa8 },
 350                 { CR144, 0xac }, { CR146, 0x20 }, { CR252, 0xff },
 351                 { CR253, 0xff },
 352         };
 353
 354         static const u32 rv[] = {
 355                 UW2453_REGWRITE(4, 0x2b),    /* configure reciever gain */
 356                 UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */
 357                 UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */
 358                 UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */
 359
 360                 /* enter CAL_FIL mode, TX gain set by registers, RX gain set by pins,
 361                  * RSSI circuit powered down, reduced RSSI range */
 362                 UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */
 363
 364                 /* synthesizer configuration for channel 1 */
 365                 UW2453_REGWRITE(1, 0x47),
 366                 UW2453_REGWRITE(2, 0x999),
 367
 368                 /* disable manual VCO band selection */
 369                 UW2453_REGWRITE(3, 0x7602),
 370
 371                 /* enable manual VCO band selection, configure current level */
 372                 UW2453_REGWRITE(3, 0x46063),
 373         };
 374
 375         r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 376         if (r)
 377                 return r;
 378
 379         r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
 380         if (r)
 381                 return r;
 382
 383         r = uw2453_init_mode(chip);
 384         if (r)
 385                 return r;
 386
 387         /* Try all standard VCO configuration settings on channel 1 */
 388         for (i = 0; i < ARRAY_SIZE(uw2453_std_vco_cfg) - 1; i++) {
 389                 /* Configure synthesizer for channel 1 */
 390                 r = uw2453_synth_set_channel(chip, 1, false);
 391                 if (r)
 392                         return r;
 393
 394                 /* Write VCO config */
 395                 r = uw2453_write_vco_cfg(chip, uw2453_std_vco_cfg[i][0]);
 396                 if (r)
 397                         return r;
 398
 399                 /* ack interrupt event */
 400                 r = zd_iowrite16_locked(chip, 0x0f, UW2453_INTR_REG);
 401                 if (r)
 402                         return r;
 403
 404                 /* check interrupt status */
 405                 r = zd_ioread16_locked(chip, &intr_status, UW2453_INTR_REG);
 406                 if (r)
 407                         return r;
 408
 409                 if (!(intr_status & 0xf)) {
 410                         dev_dbg_f(zd_chip_dev(chip),
 411                                 "PLL locked on configuration %d\n", i);
 412                         found_config = i;
 413                         break;
 414                 }
 415         }
 416
 417         if (found_config == -1) {
 418                 /* autocal */
 419                 dev_dbg_f(zd_chip_dev(chip),
 420                         "PLL did not lock, using autocal\n");
 421
 422                 r = uw2453_synth_set_channel(chip, 1, true);
 423                 if (r)
 424                         return r;
 425
 426                 r = uw2453_write_vco_cfg(chip, UW2453_AUTOCAL_VCO_CFG);
 427                 if (r)
 428                         return r;
 429         }
 430
 431         /* To match the vendor driver behaviour, we use the configuration after
 432          * the one that produced a lock. */
 433         UW2453_PRIV(rf)->config = found_config + 1;
 434
 435         return zd_iowrite16_locked(chip, 0x06, CR203);
 436 }
 437
 438 static int uw2453_set_channel(struct zd_rf *rf, u8 channel)
 439 {
 440         int r;
 441         u16 vco_cfg;
 442         int config = UW2453_PRIV(rf)->config;
 443         bool autocal = (config == -1);
 444         struct zd_chip *chip = zd_rf_to_chip(rf);
 445
 446         static const struct zd_ioreq16 ioreqs[] = {
 447                 { CR80,  0x30 }, { CR81,  0x30 }, { CR79,  0x58 },
 448                 { CR12,  0xf0 }, { CR77,  0x1b }, { CR78,  0x58 },
 449         };
 450
 451         r = uw2453_synth_set_channel(chip, channel, autocal);
 452         if (r)
 453                 return r;
 454
 455         if (autocal)
 456                 vco_cfg = UW2453_AUTOCAL_VCO_CFG;
 457         else
 458                 vco_cfg = uw2453_std_vco_cfg[config][CHAN_TO_PAIRIDX(channel)];
 459
 460         r = uw2453_write_vco_cfg(chip, vco_cfg);
 461         if (r)
 462                 return r;
 463
 464         r = uw2453_init_mode(chip);
 465         if (r)
 466                 return r;
 467
 468         r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 469         if (r)
 470                 return r;
 471
 472         r = uw2453_set_tx_gain_level(chip, channel);
 473         if (r)
 474                 return r;
 475
 476         return zd_iowrite16_locked(chip, 0x06, CR203);
 477 }
 478
 479 static int uw2453_switch_radio_on(struct zd_rf *rf)
 480 {
 481         int r;
 482         struct zd_chip *chip = zd_rf_to_chip(rf);
 483         struct zd_ioreq16 ioreqs[] = {
 484                 { CR11,  0x00 }, { CR251, 0x3f },
 485         };
 486
 487         /* enter RXTX mode */
 488         r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f94), RF_RV_BITS);
 489         if (r)
 490                 return r;
 491
 492         if (zd_chip_is_zd1211b(chip))
 493                 ioreqs[1].value = 0x7f;
 494
 495         return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 496 }
 497
 498 static int uw2453_switch_radio_off(struct zd_rf *rf)
 499 {
 500         int r;
 501         struct zd_chip *chip = zd_rf_to_chip(rf);
 502         static const struct zd_ioreq16 ioreqs[] = {
 503                 { CR11,  0x04 }, { CR251, 0x2f },
 504         };
 505
 506         /* enter IDLE mode */
 507         /* FIXME: shouldn't we go to SLEEP? sent email to zydas */
 508         r = zd_rfwrite_locked(chip, UW2453_REGWRITE(0, 0x25f90), RF_RV_BITS);
 509         if (r)
 510                 return r;
 511
 512         return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
 513 }
 514
 515 static void uw2453_clear(struct zd_rf *rf)
 516 {
 517         kfree(rf->priv);
 518 }
 519
 520 int zd_rf_init_uw2453(struct zd_rf *rf)
 521 {
 522         rf->init_hw = uw2453_init_hw;
 523         rf->set_channel = uw2453_set_channel;
 524         rf->switch_radio_on = uw2453_switch_radio_on;
 525         rf->switch_radio_off = uw2453_switch_radio_off;
 526         rf->patch_6m_band_edge = zd_rf_generic_patch_6m;
 527         rf->clear = uw2453_clear;
 528         /* we have our own TX integration code */
 529         rf->update_channel_int = 0;
 530
 531         rf->priv = kmalloc(sizeof(struct uw2453_priv), GFP_KERNEL);
 532         if (rf->priv == NULL)
 533                 return -ENOMEM;
 534
 535         return 0;
 536 }
 537