drivers/pci/msi.c

   1 /*
   2  * File:        msi.c
   3  * Purpose:     PCI Message Signaled Interrupt (MSI)
   4  *
   5  * Copyright (C) 2003-2004 Intel
   6  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7  */
   8
   9 #include <linux/err.h>
  10 #include <linux/mm.h>
  11 #include <linux/irq.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/init.h>
  14 #include <linux/ioport.h>
  15 #include <linux/pci.h>
  16 #include <linux/proc_fs.h>
  17 #include <linux/msi.h>
  18 #include <linux/smp.h>
  19 #include <linux/errno.h>
  20 #include <linux/io.h>
  21
  22 #include "pci.h"
  23 #include "msi.h"
  24
  25 static int pci_msi_enable = 1;
  26
  27 /* Arch hooks */
  28
  29 #ifndef arch_msi_check_device
  30 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
  31 {
  32         return 0;
  33 }
  34 #endif
  35
  36 #ifndef arch_setup_msi_irqs
  37 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  38 {
  39         struct msi_desc *entry;
  40         int ret;
  41
  42         /*
  43          * If an architecture wants to support multiple MSI, it needs to
  44          * override arch_setup_msi_irqs()
  45          */
  46         if (type == PCI_CAP_ID_MSI && nvec > 1)
  47                 return 1;
  48
  49         list_for_each_entry(entry, &dev->msi_list, list) {
  50                 ret = arch_setup_msi_irq(dev, entry);
  51                 if (ret < 0)
  52                         return ret;
  53                 if (ret > 0)
  54                         return -ENOSPC;
  55         }
  56
  57         return 0;
  58 }
  59 #endif
  60
  61 #ifndef arch_teardown_msi_irqs
  62 void arch_teardown_msi_irqs(struct pci_dev *dev)
  63 {
  64         struct msi_desc *entry;
  65
  66         list_for_each_entry(entry, &dev->msi_list, list) {
  67                 int i, nvec;
  68                 if (entry->irq == 0)
  69                         continue;
  70                 nvec = 1 << entry->msi_attrib.multiple;
  71                 for (i = 0; i < nvec; i++)
  72                         arch_teardown_msi_irq(entry->irq + i);
  73         }
  74 }
  75 #endif
  76
  77 static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
  78 {
  79         u16 control;
  80
  81         BUG_ON(!pos);
  82
  83         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
  84         control &= ~PCI_MSI_FLAGS_ENABLE;
  85         if (enable)
  86                 control |= PCI_MSI_FLAGS_ENABLE;
  87         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
  88 }
  89
  90 static void msix_set_enable(struct pci_dev *dev, int enable)
  91 {
  92         int pos;
  93         u16 control;
  94
  95         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
  96         if (pos) {
  97                 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
  98                 control &= ~PCI_MSIX_FLAGS_ENABLE;
  99                 if (enable)
 100                         control |= PCI_MSIX_FLAGS_ENABLE;
 101                 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 102         }
 103 }
 104
 105 static inline __attribute_const__ u32 msi_mask(unsigned x)
 106 {
 107         /* Don't shift by >= width of type */
 108         if (x >= 5)
 109                 return 0xffffffff;
 110         return (1 << (1 << x)) - 1;
 111 }
 112
 113 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
 114 {
 115         return msi_mask((control >> 1) & 7);
 116 }
 117
 118 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
 119 {
 120         return msi_mask((control >> 4) & 7);
 121 }
 122
 123 /*
 124  * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
 125  * mask all MSI interrupts by clearing the MSI enable bit does not work
 126  * reliably as devices without an INTx disable bit will then generate a
 127  * level IRQ which will never be cleared.
 128  */
 129 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 130 {
 131         u32 mask_bits = desc->masked;
 132
 133         if (!desc->msi_attrib.maskbit)
 134                 return 0;
 135
 136         mask_bits &= ~mask;
 137         mask_bits |= flag;
 138         pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
 139
 140         return mask_bits;
 141 }
 142
 143 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 144 {
 145         desc->masked = __msi_mask_irq(desc, mask, flag);
 146 }
 147
 148 /*
 149  * This internal function does not flush PCI writes to the device.
 150  * All users must ensure that they read from the device before either
 151  * assuming that the device state is up to date, or returning out of this
 152  * file.  This saves a few milliseconds when initialising devices with lots
 153  * of MSI-X interrupts.
 154  */
 155 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
 156 {
 157         u32 mask_bits = desc->masked;
 158         unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
 159                                                 PCI_MSIX_ENTRY_VECTOR_CTRL;
 160         mask_bits &= ~1;
 161         mask_bits |= flag;
 162         writel(mask_bits, desc->mask_base + offset);
 163
 164         return mask_bits;
 165 }
 166
 167 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
 168 {
 169         desc->masked = __msix_mask_irq(desc, flag);
 170 }
 171
 172 static void msi_set_mask_bit(unsigned irq, u32 flag)
 173 {
 174         struct msi_desc *desc = get_irq_msi(irq);
 175
 176         if (desc->msi_attrib.is_msix) {
 177                 msix_mask_irq(desc, flag);
 178                 readl(desc->mask_base);         /* Flush write to device */
 179         } else {
 180                 unsigned offset = irq - desc->dev->irq;
 181                 msi_mask_irq(desc, 1 << offset, flag << offset);
 182         }
 183 }
 184
 185 void mask_msi_irq(unsigned int irq)
 186 {
 187         msi_set_mask_bit(irq, 1);
 188 }
 189
 190 void unmask_msi_irq(unsigned int irq)
 191 {
 192         msi_set_mask_bit(irq, 0);
 193 }
 194
 195 void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
 196 {
 197         struct msi_desc *entry = get_irq_desc_msi(desc);
 198         if (entry->msi_attrib.is_msix) {
 199                 void __iomem *base = entry->mask_base +
 200                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 201
 202                 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
 203                 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
 204                 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
 205         } else {
 206                 struct pci_dev *dev = entry->dev;
 207                 int pos = entry->msi_attrib.pos;
 208                 u16 data;
 209
 210                 pci_read_config_dword(dev, msi_lower_address_reg(pos),
 211                                         &msg->address_lo);
 212                 if (entry->msi_attrib.is_64) {
 213                         pci_read_config_dword(dev, msi_upper_address_reg(pos),
 214                                                 &msg->address_hi);
 215                         pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
 216                 } else {
 217                         msg->address_hi = 0;
 218                         pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
 219                 }
 220                 msg->data = data;
 221         }
 222 }
 223
 224 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
 225 {
 226         struct irq_desc *desc = irq_to_desc(irq);
 227
 228         read_msi_msg_desc(desc, msg);
 229 }
 230
 231 void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
 232 {
 233         struct msi_desc *entry = get_irq_desc_msi(desc);
 234         if (entry->msi_attrib.is_msix) {
 235                 void __iomem *base;
 236                 base = entry->mask_base +
 237                         entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 238
 239                 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
 240                 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
 241                 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
 242         } else {
 243                 struct pci_dev *dev = entry->dev;
 244                 int pos = entry->msi_attrib.pos;
 245                 u16 msgctl;
 246
 247                 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
 248                 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
 249                 msgctl |= entry->msi_attrib.multiple << 4;
 250                 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
 251
 252                 pci_write_config_dword(dev, msi_lower_address_reg(pos),
 253                                         msg->address_lo);
 254                 if (entry->msi_attrib.is_64) {
 255                         pci_write_config_dword(dev, msi_upper_address_reg(pos),
 256                                                 msg->address_hi);
 257                         pci_write_config_word(dev, msi_data_reg(pos, 1),
 258                                                 msg->data);
 259                 } else {
 260                         pci_write_config_word(dev, msi_data_reg(pos, 0),
 261                                                 msg->data);
 262                 }
 263         }
 264         entry->msg = *msg;
 265 }
 266
 267 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
 268 {
 269         struct irq_desc *desc = irq_to_desc(irq);
 270
 271         write_msi_msg_desc(desc, msg);
 272 }
 273
 274 static void free_msi_irqs(struct pci_dev *dev)
 275 {
 276         struct msi_desc *entry, *tmp;
 277
 278         list_for_each_entry(entry, &dev->msi_list, list) {
 279                 int i, nvec;
 280                 if (!entry->irq)
 281                         continue;
 282                 nvec = 1 << entry->msi_attrib.multiple;
 283                 for (i = 0; i < nvec; i++)
 284                         BUG_ON(irq_has_action(entry->irq + i));
 285         }
 286
 287         arch_teardown_msi_irqs(dev);
 288
 289         list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
 290                 if (entry->msi_attrib.is_msix) {
 291                         if (list_is_last(&entry->list, &dev->msi_list))
 292                                 iounmap(entry->mask_base);
 293                 }
 294                 list_del(&entry->list);
 295                 kfree(entry);
 296         }
 297 }
 298
 299 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
 300 {
 301         struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 302         if (!desc)
 303                 return NULL;
 304
 305         INIT_LIST_HEAD(&desc->list);
 306         desc->dev = dev;
 307
 308         return desc;
 309 }
 310
 311 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
 312 {
 313         if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
 314                 pci_intx(dev, enable);
 315 }
 316
 317 static void __pci_restore_msi_state(struct pci_dev *dev)
 318 {
 319         int pos;
 320         u16 control;
 321         struct msi_desc *entry;
 322
 323         if (!dev->msi_enabled)
 324                 return;
 325
 326         entry = get_irq_msi(dev->irq);
 327         pos = entry->msi_attrib.pos;
 328
 329         pci_intx_for_msi(dev, 0);
 330         msi_set_enable(dev, pos, 0);
 331         write_msi_msg(dev->irq, &entry->msg);
 332
 333         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
 334         msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
 335         control &= ~PCI_MSI_FLAGS_QSIZE;
 336         control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
 337         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 338 }
 339
 340 static void __pci_restore_msix_state(struct pci_dev *dev)
 341 {
 342         int pos;
 343         struct msi_desc *entry;
 344         u16 control;
 345
 346         if (!dev->msix_enabled)
 347                 return;
 348         BUG_ON(list_empty(&dev->msi_list));
 349         entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
 350         pos = entry->msi_attrib.pos;
 351         pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 352
 353         /* route the table */
 354         pci_intx_for_msi(dev, 0);
 355         control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
 356         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 357
 358         list_for_each_entry(entry, &dev->msi_list, list) {
 359                 write_msi_msg(entry->irq, &entry->msg);
 360                 msix_mask_irq(entry, entry->masked);
 361         }
 362
 363         control &= ~PCI_MSIX_FLAGS_MASKALL;
 364         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 365 }
 366
 367 void pci_restore_msi_state(struct pci_dev *dev)
 368 {
 369         __pci_restore_msi_state(dev);
 370         __pci_restore_msix_state(dev);
 371 }
 372 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
 373
 374 /**
 375  * msi_capability_init - configure device's MSI capability structure
 376  * @dev: pointer to the pci_dev data structure of MSI device function
 377  * @nvec: number of interrupts to allocate
 378  *
 379  * Setup the MSI capability structure of the device with the requested
 380  * number of interrupts.  A return value of zero indicates the successful
 381  * setup of an entry with the new MSI irq.  A negative return value indicates
 382  * an error, and a positive return value indicates the number of interrupts
 383  * which could have been allocated.
 384  */
 385 static int msi_capability_init(struct pci_dev *dev, int nvec)
 386 {
 387         struct msi_desc *entry;
 388         int pos, ret;
 389         u16 control;
 390         unsigned mask;
 391
 392         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 393         msi_set_enable(dev, pos, 0);    /* Disable MSI during set up */
 394
 395         pci_read_config_word(dev, msi_control_reg(pos), &control);
 396         /* MSI Entry Initialization */
 397         entry = alloc_msi_entry(dev);
 398         if (!entry)
 399                 return -ENOMEM;
 400
 401         entry->msi_attrib.is_msix       = 0;
 402         entry->msi_attrib.is_64         = is_64bit_address(control);
 403         entry->msi_attrib.entry_nr      = 0;
 404         entry->msi_attrib.maskbit       = is_mask_bit_support(control);
 405         entry->msi_attrib.default_irq   = dev->irq;     /* Save IOAPIC IRQ */
 406         entry->msi_attrib.pos           = pos;
 407
 408         entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
 409         /* All MSIs are unmasked by default, Mask them all */
 410         if (entry->msi_attrib.maskbit)
 411                 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
 412         mask = msi_capable_mask(control);
 413         msi_mask_irq(entry, mask, mask);
 414
 415         list_add_tail(&entry->list, &dev->msi_list);
 416
 417         /* Configure MSI capability structure */
 418         ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
 419         if (ret) {
 420                 msi_mask_irq(entry, mask, ~mask);
 421                 free_msi_irqs(dev);
 422                 return ret;
 423         }
 424
 425         /* Set MSI enabled bits  */
 426         pci_intx_for_msi(dev, 0);
 427         msi_set_enable(dev, pos, 1);
 428         dev->msi_enabled = 1;
 429
 430         dev->irq = entry->irq;
 431         return 0;
 432 }
 433
 434 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
 435                                                         unsigned nr_entries)
 436 {
 437         unsigned long phys_addr;
 438         u32 table_offset;
 439         u8 bir;
 440
 441         pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
 442         bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
 443         table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
 444         phys_addr = pci_resource_start(dev, bir) + table_offset;
 445
 446         return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 447 }
 448
 449 static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
 450                                 void __iomem *base, struct msix_entry *entries,
 451                                 int nvec)
 452 {
 453         struct msi_desc *entry;
 454         int i;
 455
 456         for (i = 0; i < nvec; i++) {
 457                 entry = alloc_msi_entry(dev);
 458                 if (!entry) {
 459                         if (!i)
 460                                 iounmap(base);
 461                         else
 462                                 free_msi_irqs(dev);
 463                         /* No enough memory. Don't try again */
 464                         return -ENOMEM;
 465                 }
 466
 467                 entry->msi_attrib.is_msix       = 1;
 468                 entry->msi_attrib.is_64         = 1;
 469                 entry->msi_attrib.entry_nr      = entries[i].entry;
 470                 entry->msi_attrib.default_irq   = dev->irq;
 471                 entry->msi_attrib.pos           = pos;
 472                 entry->mask_base                = base;
 473
 474                 list_add_tail(&entry->list, &dev->msi_list);
 475         }
 476
 477         return 0;
 478 }
 479
 480 static void msix_program_entries(struct pci_dev *dev,
 481                                         struct msix_entry *entries)
 482 {
 483         struct msi_desc *entry;
 484         int i = 0;
 485
 486         list_for_each_entry(entry, &dev->msi_list, list) {
 487                 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
 488                                                 PCI_MSIX_ENTRY_VECTOR_CTRL;
 489
 490                 entries[i].vector = entry->irq;
 491                 set_irq_msi(entry->irq, entry);
 492                 entry->masked = readl(entry->mask_base + offset);
 493                 msix_mask_irq(entry, 1);
 494                 i++;
 495         }
 496 }
 497
 498 /**
 499  * msix_capability_init - configure device's MSI-X capability
 500  * @dev: pointer to the pci_dev data structure of MSI-X device function
 501  * @entries: pointer to an array of struct msix_entry entries
 502  * @nvec: number of @entries
 503  *
 504  * Setup the MSI-X capability structure of device function with a
 505  * single MSI-X irq. A return of zero indicates the successful setup of
 506  * requested MSI-X entries with allocated irqs or non-zero for otherwise.
 507  **/
 508 static int msix_capability_init(struct pci_dev *dev,
 509                                 struct msix_entry *entries, int nvec)
 510 {
 511         int pos, ret;
 512         u16 control;
 513         void __iomem *base;
 514
 515         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 516         pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
 517
 518         /* Ensure MSI-X is disabled while it is set up */
 519         control &= ~PCI_MSIX_FLAGS_ENABLE;
 520         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 521
 522         /* Request & Map MSI-X table region */
 523         base = msix_map_region(dev, pos, multi_msix_capable(control));
 524         if (!base)
 525                 return -ENOMEM;
 526
 527         ret = msix_setup_entries(dev, pos, base, entries, nvec);
 528         if (ret)
 529                 return ret;
 530
 531         ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
 532         if (ret)
 533                 goto error;
 534
 535         /*
 536          * Some devices require MSI-X to be enabled before we can touch the
 537          * MSI-X registers.  We need to mask all the vectors to prevent
 538          * interrupts coming in before they're fully set up.
 539          */
 540         control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
 541         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 542
 543         msix_program_entries(dev, entries);
 544
 545         /* Set MSI-X enabled bits and unmask the function */
 546         pci_intx_for_msi(dev, 0);
 547         dev->msix_enabled = 1;
 548
 549         control &= ~PCI_MSIX_FLAGS_MASKALL;
 550         pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
 551
 552         return 0;
 553
 554 error:
 555         if (ret < 0) {
 556                 /*
 557                  * If we had some success, report the number of irqs
 558                  * we succeeded in setting up.
 559                  */
 560                 struct msi_desc *entry;
 561                 int avail = 0;
 562
 563                 list_for_each_entry(entry, &dev->msi_list, list) {
 564                         if (entry->irq != 0)
 565                                 avail++;
 566                 }
 567                 if (avail != 0)
 568                         ret = avail;
 569         }
 570
 571         free_msi_irqs(dev);
 572
 573         return ret;
 574 }
 575
 576 /**
 577  * pci_msi_check_device - check whether MSI may be enabled on a device
 578  * @dev: pointer to the pci_dev data structure of MSI device function
 579  * @nvec: how many MSIs have been requested ?
 580  * @type: are we checking for MSI or MSI-X ?
 581  *
 582  * Look at global flags, the device itself, and its parent busses
 583  * to determine if MSI/-X are supported for the device. If MSI/-X is
 584  * supported return 0, else return an error code.
 585  **/
 586 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
 587 {
 588         struct pci_bus *bus;
 589         int ret;
 590
 591         /* MSI must be globally enabled and supported by the device */
 592         if (!pci_msi_enable || !dev || dev->no_msi)
 593                 return -EINVAL;
 594
 595         /*
 596          * You can't ask to have 0 or less MSIs configured.
 597          *  a) it's stupid ..
 598          *  b) the list manipulation code assumes nvec >= 1.
 599          */
 600         if (nvec < 1)
 601                 return -ERANGE;
 602
 603         /*
 604          * Any bridge which does NOT route MSI transactions from its
 605          * secondary bus to its primary bus must set NO_MSI flag on
 606          * the secondary pci_bus.
 607          * We expect only arch-specific PCI host bus controller driver
 608          * or quirks for specific PCI bridges to be setting NO_MSI.
 609          */
 610         for (bus = dev->bus; bus; bus = bus->parent)
 611                 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 612                         return -EINVAL;
 613
 614         ret = arch_msi_check_device(dev, nvec, type);
 615         if (ret)
 616                 return ret;
 617
 618         if (!pci_find_capability(dev, type))
 619                 return -EINVAL;
 620
 621         return 0;
 622 }
 623
 624 /**
 625  * pci_enable_msi_block - configure device's MSI capability structure
 626  * @dev: device to configure
 627  * @nvec: number of interrupts to configure
 628  *
 629  * Allocate IRQs for a device with the MSI capability.
 630  * This function returns a negative errno if an error occurs.  If it
 631  * is unable to allocate the number of interrupts requested, it returns
 632  * the number of interrupts it might be able to allocate.  If it successfully
 633  * allocates at least the number of interrupts requested, it returns 0 and
 634  * updates the @dev's irq member to the lowest new interrupt number; the
 635  * other interrupt numbers allocated to this device are consecutive.
 636  */
 637 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
 638 {
 639         int status, pos, maxvec;
 640         u16 msgctl;
 641
 642         pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
 643         if (!pos)
 644                 return -EINVAL;
 645         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
 646         maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
 647         if (nvec > maxvec)
 648                 return maxvec;
 649
 650         status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
 651         if (status)
 652                 return status;
 653
 654         WARN_ON(!!dev->msi_enabled);
 655
 656         /* Check whether driver already requested MSI-X irqs */
 657         if (dev->msix_enabled) {
 658                 dev_info(&dev->dev, "can't enable MSI "
 659                          "(MSI-X already enabled)\n");
 660                 return -EINVAL;
 661         }
 662
 663         status = msi_capability_init(dev, nvec);
 664         return status;
 665 }
 666 EXPORT_SYMBOL(pci_enable_msi_block);
 667
 668 void pci_msi_shutdown(struct pci_dev *dev)
 669 {
 670         struct msi_desc *desc;
 671         u32 mask;
 672         u16 ctrl;
 673         unsigned pos;
 674
 675         if (!pci_msi_enable || !dev || !dev->msi_enabled)
 676                 return;
 677
 678         BUG_ON(list_empty(&dev->msi_list));
 679         desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
 680         pos = desc->msi_attrib.pos;
 681
 682         msi_set_enable(dev, pos, 0);
 683         pci_intx_for_msi(dev, 1);
 684         dev->msi_enabled = 0;
 685
 686         /* Return the device with MSI unmasked as initial states */
 687         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
 688         mask = msi_capable_mask(ctrl);
 689         /* Keep cached state to be restored */
 690         __msi_mask_irq(desc, mask, ~mask);
 691
 692         /* Restore dev->irq to its default pin-assertion irq */
 693         dev->irq = desc->msi_attrib.default_irq;
 694 }
 695
 696 void pci_disable_msi(struct pci_dev *dev)
 697 {
 698         if (!pci_msi_enable || !dev || !dev->msi_enabled)
 699                 return;
 700
 701         pci_msi_shutdown(dev);
 702         free_msi_irqs(dev);
 703 }
 704 EXPORT_SYMBOL(pci_disable_msi);
 705
 706 /**
 707  * pci_msix_table_size - return the number of device's MSI-X table entries
 708  * @dev: pointer to the pci_dev data structure of MSI-X device function
 709  */
 710 int pci_msix_table_size(struct pci_dev *dev)
 711 {
 712         int pos;
 713         u16 control;
 714
 715         pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
 716         if (!pos)
 717                 return 0;
 718
 719         pci_read_config_word(dev, msi_control_reg(pos), &control);
 720         return multi_msix_capable(control);
 721 }
 722
 723 /**
 724  * pci_enable_msix - configure device's MSI-X capability structure
 725  * @dev: pointer to the pci_dev data structure of MSI-X device function
 726  * @entries: pointer to an array of MSI-X entries
 727  * @nvec: number of MSI-X irqs requested for allocation by device driver
 728  *
 729  * Setup the MSI-X capability structure of device function with the number
 730  * of requested irqs upon its software driver call to request for
 731  * MSI-X mode enabled on its hardware device function. A return of zero
 732  * indicates the successful configuration of MSI-X capability structure
 733  * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
 734  * Or a return of > 0 indicates that driver request is exceeding the number
 735  * of irqs or MSI-X vectors available. Driver should use the returned value to
 736  * re-send its request.
 737  **/
 738 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
 739 {
 740         int status, nr_entries;
 741         int i, j;
 742
 743         if (!entries)
 744                 return -EINVAL;
 745
 746         status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
 747         if (status)
 748                 return status;
 749
 750         nr_entries = pci_msix_table_size(dev);
 751         if (nvec > nr_entries)
 752                 return nr_entries;
 753
 754         /* Check for any invalid entries */
 755         for (i = 0; i < nvec; i++) {
 756                 if (entries[i].entry >= nr_entries)
 757                         return -EINVAL;         /* invalid entry */
 758                 for (j = i + 1; j < nvec; j++) {
 759                         if (entries[i].entry == entries[j].entry)
 760                                 return -EINVAL; /* duplicate entry */
 761                 }
 762         }
 763         WARN_ON(!!dev->msix_enabled);
 764
 765         /* Check whether driver already requested for MSI irq */
 766         if (dev->msi_enabled) {
 767                 dev_info(&dev->dev, "can't enable MSI-X "
 768                        "(MSI IRQ already assigned)\n");
 769                 return -EINVAL;
 770         }
 771         status = msix_capability_init(dev, entries, nvec);
 772         return status;
 773 }
 774 EXPORT_SYMBOL(pci_enable_msix);
 775
 776 void pci_msix_shutdown(struct pci_dev *dev)
 777 {
 778         struct msi_desc *entry;
 779
 780         if (!pci_msi_enable || !dev || !dev->msix_enabled)
 781                 return;
 782
 783         /* Return the device with MSI-X masked as initial states */
 784         list_for_each_entry(entry, &dev->msi_list, list) {
 785                 /* Keep cached states to be restored */
 786                 __msix_mask_irq(entry, 1);
 787         }
 788
 789         msix_set_enable(dev, 0);
 790         pci_intx_for_msi(dev, 1);
 791         dev->msix_enabled = 0;
 792 }
 793
 794 void pci_disable_msix(struct pci_dev *dev)
 795 {
 796         if (!pci_msi_enable || !dev || !dev->msix_enabled)
 797                 return;
 798
 799         pci_msix_shutdown(dev);
 800         free_msi_irqs(dev);
 801 }
 802 EXPORT_SYMBOL(pci_disable_msix);
 803
 804 /**
 805  * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
 806  * @dev: pointer to the pci_dev data structure of MSI(X) device function
 807  *
 808  * Being called during hotplug remove, from which the device function
 809  * is hot-removed. All previous assigned MSI/MSI-X irqs, if
 810  * allocated for this device function, are reclaimed to unused state,
 811  * which may be used later on.
 812  **/
 813 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
 814 {
 815         if (!pci_msi_enable || !dev)
 816                 return;
 817
 818         if (dev->msi_enabled || dev->msix_enabled)
 819                 free_msi_irqs(dev);
 820 }
 821
 822 void pci_no_msi(void)
 823 {
 824         pci_msi_enable = 0;
 825 }
 826
 827 /**
 828  * pci_msi_enabled - is MSI enabled?
 829  *
 830  * Returns true if MSI has not been disabled by the command-line option
 831  * pci=nomsi.
 832  **/
 833 int pci_msi_enabled(void)
 834 {
 835         return pci_msi_enable;
 836 }
 837 EXPORT_SYMBOL(pci_msi_enabled);
 838
 839 void pci_msi_init_pci_dev(struct pci_dev *dev)
 840 {
 841         INIT_LIST_HEAD(&dev->msi_list);
 842 }