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[ARM] pxa: Gumstix Verdex PCMCIA support
[linux-2.6/verdex.git] / drivers / staging / cx25821 / cx25821-video-upstream.c
blob3d7dd3f66541d9d3d91a050cdd5a3892d4eeaafa
1 /*
2 * Driver for the Conexant CX25821 PCIe bridge
3 *
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 *
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include "cx25821-video.h"
24 #include "cx25821-video-upstream.h"
25
26 #include <linux/fs.h>
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/syscalls.h>
32 #include <linux/file.h>
33 #include <linux/fcntl.h>
34 #include <asm/uaccess.h>
35
36 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
37 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
38 MODULE_LICENSE("GPL");
39
40 static int _intr_msk =
41 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
42
43 int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
44 struct sram_channel *ch,
45 unsigned int bpl, u32 risc)
46 {
47 unsigned int i, lines;
48 u32 cdt;
49
50 if (ch->cmds_start == 0) {
51 cx_write(ch->ptr1_reg, 0);
52 cx_write(ch->ptr2_reg, 0);
53 cx_write(ch->cnt2_reg, 0);
54 cx_write(ch->cnt1_reg, 0);
55 return 0;
56 }
57
58 bpl = (bpl + 7) & ~7; /* alignment */
59 cdt = ch->cdt;
60 lines = ch->fifo_size / bpl;
61
62 if (lines > 4) {
63 lines = 4;
64 }
65
66 BUG_ON(lines < 2);
67
68 /* write CDT */
69 for (i = 0; i < lines; i++) {
70 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
71 cx_write(cdt + 16 * i + 4, 0);
72 cx_write(cdt + 16 * i + 8, 0);
73 cx_write(cdt + 16 * i + 12, 0);
74 }
75
76 /* write CMDS */
77 cx_write(ch->cmds_start + 0, risc);
78
79 cx_write(ch->cmds_start + 4, 0);
80 cx_write(ch->cmds_start + 8, cdt);
81 cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
82 cx_write(ch->cmds_start + 16, ch->ctrl_start);
83
84 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
85
86 for (i = 24; i < 80; i += 4)
87 cx_write(ch->cmds_start + i, 0);
88
89 /* fill registers */
90 cx_write(ch->ptr1_reg, ch->fifo_start);
91 cx_write(ch->ptr2_reg, cdt);
92 cx_write(ch->cnt2_reg, (lines * 16) >> 3);
93 cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
94
95 return 0;
96 }
97
98 static __le32 *cx25821_update_riscprogram(struct cx25821_dev *dev,
99 __le32 * rp, unsigned int offset,
100 unsigned int bpl, u32 sync_line,
101 unsigned int lines, int fifo_enable,
102 int field_type)
103 {
104 unsigned int line, i;
105 int dist_betwn_starts = bpl * 2;
106
107 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
108
109 if (USE_RISC_NOOP_VIDEO) {
110 for (i = 0; i < NUM_NO_OPS; i++) {
111 *(rp++) = cpu_to_le32(RISC_NOOP);
112 }
113 }
114
115 /* scan lines */
116 for (line = 0; line < lines; line++) {
117 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
118 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr + offset);
119 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
120
121 if ((lines <= NTSC_FIELD_HEIGHT)
122 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
123 offset += dist_betwn_starts;
124 }
125 }
126
127 return rp;
128 }
129
130 static __le32 *cx25821_risc_field_upstream(struct cx25821_dev *dev, __le32 * rp,
131 dma_addr_t databuf_phys_addr,
132 unsigned int offset, u32 sync_line,
133 unsigned int bpl, unsigned int lines,
134 int fifo_enable, int field_type)
135 {
136 unsigned int line, i;
137 struct sram_channel *sram_ch =
138 &dev->sram_channels[dev->_channel_upstream_select];
139 int dist_betwn_starts = bpl * 2;
140
141 /* sync instruction */
142 if (sync_line != NO_SYNC_LINE) {
143 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
144 }
145
146 if (USE_RISC_NOOP_VIDEO) {
147 for (i = 0; i < NUM_NO_OPS; i++) {
148 *(rp++) = cpu_to_le32(RISC_NOOP);
149 }
150 }
151
152 /* scan lines */
153 for (line = 0; line < lines; line++) {
154 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
155 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
156 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
157
158 if ((lines <= NTSC_FIELD_HEIGHT)
159 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(dev->_isNTSC)) {
160 offset += dist_betwn_starts; //to skip the other field line
161 }
162
163 // check if we need to enable the FIFO after the first 4 lines
164 // For the upstream video channel, the risc engine will enable the FIFO.
165 if (fifo_enable && line == 3) {
166 *(rp++) = RISC_WRITECR;
167 *(rp++) = sram_ch->dma_ctl;
168 *(rp++) = FLD_VID_FIFO_EN;
169 *(rp++) = 0x00000001;
170 }
171 }
172
173 return rp;
174 }
175
176 int cx25821_risc_buffer_upstream(struct cx25821_dev *dev,
177 struct pci_dev *pci,
178 unsigned int top_offset,
179 unsigned int bpl, unsigned int lines)
180 {
181 __le32 *rp;
182 int fifo_enable = 0;
183 int singlefield_lines = lines >> 1; //get line count for single field
184 int odd_num_lines = singlefield_lines;
185 int frame = 0;
186 int frame_size = 0;
187 int databuf_offset = 0;
188 int risc_program_size = 0;
189 int risc_flag = RISC_CNT_RESET;
190 unsigned int bottom_offset = bpl;
191 dma_addr_t risc_phys_jump_addr;
192
193 if (dev->_isNTSC) {
194 odd_num_lines = singlefield_lines + 1;
195 risc_program_size = FRAME1_VID_PROG_SIZE;
196 frame_size =
197 (bpl ==
198 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
199 FRAME_SIZE_NTSC_Y422;
200 } else {
201 risc_program_size = PAL_VID_PROG_SIZE;
202 frame_size =
203 (bpl ==
204 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
205 }
206
207 /* Virtual address of Risc buffer program */
208 rp = dev->_dma_virt_addr;
209
210 for (frame = 0; frame < NUM_FRAMES; frame++) {
211 databuf_offset = frame_size * frame;
212
213 if (UNSET != top_offset) {
214 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
215 rp = cx25821_risc_field_upstream(dev, rp,
216 dev->
217 _data_buf_phys_addr +
218 databuf_offset,
219 top_offset, 0, bpl,
220 odd_num_lines,
221 fifo_enable,
222 ODD_FIELD);
223 }
224
225 fifo_enable = FIFO_DISABLE;
226
227 //Even Field
228 rp = cx25821_risc_field_upstream(dev, rp,
229 dev->_data_buf_phys_addr +
230 databuf_offset, bottom_offset,
231 0x200, bpl, singlefield_lines,
232 fifo_enable, EVEN_FIELD);
233
234 if (frame == 0) {
235 risc_flag = RISC_CNT_RESET;
236 risc_phys_jump_addr =
237 dev->_dma_phys_start_addr + risc_program_size;
238 } else {
239 risc_phys_jump_addr = dev->_dma_phys_start_addr;
240 risc_flag = RISC_CNT_INC;
241 }
242
243 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
244 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
245 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
246 *(rp++) = cpu_to_le32(0);
247 }
248
249 return 0;
250 }
251
252 void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
253 {
254 struct sram_channel *sram_ch =
255 &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_I];
256 u32 tmp = 0;
257
258 if (!dev->_is_running) {
259 printk
260 ("cx25821: No video file is currently running so return!\n");
261 return;
262 }
263 //Disable RISC interrupts
264 tmp = cx_read(sram_ch->int_msk);
265 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
266
267 //Turn OFF risc and fifo enable
268 tmp = cx_read(sram_ch->dma_ctl);
269 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
270
271 //Clear data buffer memory
272 if (dev->_data_buf_virt_addr)
273 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
274
275 dev->_is_running = 0;
276 dev->_is_first_frame = 0;
277 dev->_frame_count = 0;
278 dev->_file_status = END_OF_FILE;
279
280 if (dev->_irq_queues) {
281 kfree(dev->_irq_queues);
282 dev->_irq_queues = NULL;
283 }
284
285 if (dev->_filename != NULL)
286 kfree(dev->_filename);
287
288 tmp = cx_read(VID_CH_MODE_SEL);
289 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
290 }
291
292 void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
293 {
294 if (dev->_is_running) {
295 cx25821_stop_upstream_video_ch1(dev);
296 }
297
298 if (dev->_dma_virt_addr) {
299 pci_free_consistent(dev->pci, dev->_risc_size,
300 dev->_dma_virt_addr, dev->_dma_phys_addr);
301 dev->_dma_virt_addr = NULL;
302 }
303
304 if (dev->_data_buf_virt_addr) {
305 pci_free_consistent(dev->pci, dev->_data_buf_size,
306 dev->_data_buf_virt_addr,
307 dev->_data_buf_phys_addr);
308 dev->_data_buf_virt_addr = NULL;
309 }
310 }
311
312 int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch)
313 {
314 struct file *myfile;
315 int frame_index_temp = dev->_frame_index;
316 int i = 0;
317 int line_size =
318 (dev->_pixel_format ==
319 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
320 int frame_size = 0;
321 int frame_offset = 0;
322 ssize_t vfs_read_retval = 0;
323 char mybuf[line_size];
324 loff_t file_offset;
325 loff_t pos;
326 mm_segment_t old_fs;
327
328 if (dev->_file_status == END_OF_FILE)
329 return 0;
330
331 if (dev->_isNTSC) {
332 frame_size =
333 (line_size ==
334 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
335 FRAME_SIZE_NTSC_Y422;
336 } else {
337 frame_size =
338 (line_size ==
339 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
340 }
341
342 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
343 file_offset = dev->_frame_count * frame_size;
344
345 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
346
347 if (IS_ERR(myfile)) {
348 const int open_errno = -PTR_ERR(myfile);
349 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
350 __func__, dev->_filename, open_errno);
351 return PTR_ERR(myfile);
352 } else {
353 if (!(myfile->f_op)) {
354 printk("%s: File has no file operations registered!",
355 __func__);
356 filp_close(myfile, NULL);
357 return -EIO;
358 }
359
360 if (!myfile->f_op->read) {
361 printk("%s: File has no READ operations registered!",
362 __func__);
363 filp_close(myfile, NULL);
364 return -EIO;
365 }
366
367 pos = myfile->f_pos;
368 old_fs = get_fs();
369 set_fs(KERNEL_DS);
370
371 for (i = 0; i < dev->_lines_count; i++) {
372 pos = file_offset;
373
374 vfs_read_retval =
375 vfs_read(myfile, mybuf, line_size, &pos);
376
377 if (vfs_read_retval > 0 && vfs_read_retval == line_size
378 && dev->_data_buf_virt_addr != NULL) {
379 memcpy((void *)(dev->_data_buf_virt_addr +
380 frame_offset / 4), mybuf,
381 vfs_read_retval);
382 }
383
384 file_offset += vfs_read_retval;
385 frame_offset += vfs_read_retval;
386
387 if (vfs_read_retval < line_size) {
388 printk(KERN_INFO
389 "Done: exit %s() since no more bytes to read from Video file.\n",
390 __func__);
391 break;
392 }
393 }
394
395 if (i > 0)
396 dev->_frame_count++;
397
398 dev->_file_status =
399 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
400
401 set_fs(old_fs);
402 filp_close(myfile, NULL);
403 }
404
405 return 0;
406 }
407
408 static void cx25821_vidups_handler(struct work_struct *work)
409 {
410 struct cx25821_dev *dev =
411 container_of(work, struct cx25821_dev, _irq_work_entry);
412
413 if (!dev) {
414 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
415 __func__);
416 return;
417 }
418
419 cx25821_get_frame(dev,
420 &dev->sram_channels[dev->_channel_upstream_select]);
421 }
422
423 int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
424 {
425 struct file *myfile;
426 int i = 0, j = 0;
427 int line_size =
428 (dev->_pixel_format ==
429 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
430 ssize_t vfs_read_retval = 0;
431 char mybuf[line_size];
432 loff_t pos;
433 loff_t offset = (unsigned long)0;
434 mm_segment_t old_fs;
435
436 myfile = filp_open(dev->_filename, O_RDONLY | O_LARGEFILE, 0);
437
438 if (IS_ERR(myfile)) {
439 const int open_errno = -PTR_ERR(myfile);
440 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
441 __func__, dev->_filename, open_errno);
442 return PTR_ERR(myfile);
443 } else {
444 if (!(myfile->f_op)) {
445 printk("%s: File has no file operations registered!",
446 __func__);
447 filp_close(myfile, NULL);
448 return -EIO;
449 }
450
451 if (!myfile->f_op->read) {
452 printk
453 ("%s: File has no READ operations registered! Returning.",
454 __func__);
455 filp_close(myfile, NULL);
456 return -EIO;
457 }
458
459 pos = myfile->f_pos;
460 old_fs = get_fs();
461 set_fs(KERNEL_DS);
462
463 for (j = 0; j < NUM_FRAMES; j++) {
464 for (i = 0; i < dev->_lines_count; i++) {
465 pos = offset;
466
467 vfs_read_retval =
468 vfs_read(myfile, mybuf, line_size, &pos);
469
470 if (vfs_read_retval > 0
471 && vfs_read_retval == line_size
472 && dev->_data_buf_virt_addr != NULL) {
473 memcpy((void *)(dev->
474 _data_buf_virt_addr +
475 offset / 4), mybuf,
476 vfs_read_retval);
477 }
478
479 offset += vfs_read_retval;
480
481 if (vfs_read_retval < line_size) {
482 printk(KERN_INFO
483 "Done: exit %s() since no more bytes to read from Video file.\n",
484 __func__);
485 break;
486 }
487 }
488
489 if (i > 0)
490 dev->_frame_count++;
491
492 if (vfs_read_retval < line_size) {
493 break;
494 }
495 }
496
497 dev->_file_status =
498 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
499
500 set_fs(old_fs);
501 myfile->f_pos = 0;
502 filp_close(myfile, NULL);
503 }
504
505 return 0;
506 }
507
508 int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
509 struct sram_channel *sram_ch, int bpl)
510 {
511 int ret = 0;
512 dma_addr_t dma_addr;
513 dma_addr_t data_dma_addr;
514
515 if (dev->_dma_virt_addr != NULL) {
516 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size,
517 dev->_dma_virt_addr, dev->_dma_phys_addr);
518 }
519
520 dev->_dma_virt_addr =
521 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size,
522 &dma_addr);
523 dev->_dma_virt_start_addr = dev->_dma_virt_addr;
524 dev->_dma_phys_start_addr = dma_addr;
525 dev->_dma_phys_addr = dma_addr;
526 dev->_risc_size = dev->upstream_riscbuf_size;
527
528 if (!dev->_dma_virt_addr) {
529 printk
530 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
531 return -ENOMEM;
532 }
533
534 //Clear memory at address
535 memset(dev->_dma_virt_addr, 0, dev->_risc_size);
536
537 if (dev->_data_buf_virt_addr != NULL) {
538 pci_free_consistent(dev->pci, dev->upstream_databuf_size,
539 dev->_data_buf_virt_addr,
540 dev->_data_buf_phys_addr);
541 }
542 //For Video Data buffer allocation
543 dev->_data_buf_virt_addr =
544 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size,
545 &data_dma_addr);
546 dev->_data_buf_phys_addr = data_dma_addr;
547 dev->_data_buf_size = dev->upstream_databuf_size;
548
549 if (!dev->_data_buf_virt_addr) {
550 printk
551 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
552 return -ENOMEM;
553 }
554
555 //Clear memory at address
556 memset(dev->_data_buf_virt_addr, 0, dev->_data_buf_size);
557
558 ret = cx25821_openfile(dev, sram_ch);
559 if (ret < 0)
560 return ret;
561
562 //Create RISC programs
563 ret =
564 cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl,
565 dev->_lines_count);
566 if (ret < 0) {
567 printk(KERN_INFO
568 "cx25821: Failed creating Video Upstream Risc programs! \n");
569 goto error;
570 }
571
572 return 0;
573
574 error:
575 return ret;
576 }
577
578 int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num,
579 u32 status)
580 {
581 u32 int_msk_tmp;
582 struct sram_channel *channel = &dev->sram_channels[chan_num];
583 int singlefield_lines = NTSC_FIELD_HEIGHT;
584 int line_size_in_bytes = Y422_LINE_SZ;
585 int odd_risc_prog_size = 0;
586 dma_addr_t risc_phys_jump_addr;
587 __le32 *rp;
588
589 if (status & FLD_VID_SRC_RISC1) {
590 // We should only process one program per call
591 u32 prog_cnt = cx_read(channel->gpcnt);
592
593 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
594 int_msk_tmp = cx_read(channel->int_msk);
595 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
596 cx_write(channel->int_stat, _intr_msk);
597
598 spin_lock(&dev->slock);
599
600 dev->_frame_index = prog_cnt;
601
602 queue_work(dev->_irq_queues, &dev->_irq_work_entry);
603
604 if (dev->_is_first_frame) {
605 dev->_is_first_frame = 0;
606
607 if (dev->_isNTSC) {
608 singlefield_lines += 1;
609 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
610 } else {
611 singlefield_lines = PAL_FIELD_HEIGHT;
612 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
613 }
614
615 if (dev->_dma_virt_start_addr != NULL) {
616 line_size_in_bytes =
617 (dev->_pixel_format ==
618 PIXEL_FRMT_411) ? Y411_LINE_SZ :
619 Y422_LINE_SZ;
620 risc_phys_jump_addr =
621 dev->_dma_phys_start_addr +
622 odd_risc_prog_size;
623
624 rp = cx25821_update_riscprogram(dev,
625 dev->
626 _dma_virt_start_addr,
627 TOP_OFFSET,
628 line_size_in_bytes,
629 0x0,
630 singlefield_lines,
631 FIFO_DISABLE,
632 ODD_FIELD);
633
634 // Jump to Even Risc program of 1st Frame
635 *(rp++) = cpu_to_le32(RISC_JUMP);
636 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
637 *(rp++) = cpu_to_le32(0);
638 }
639 }
640
641 spin_unlock(&dev->slock);
642 } else {
643 if (status & FLD_VID_SRC_UF)
644 printk
645 ("%s: Video Received Underflow Error Interrupt!\n",
646 __func__);
647
648 if (status & FLD_VID_SRC_SYNC)
649 printk("%s: Video Received Sync Error Interrupt!\n",
650 __func__);
651
652 if (status & FLD_VID_SRC_OPC_ERR)
653 printk("%s: Video Received OpCode Error Interrupt!\n",
654 __func__);
655 }
656
657 if (dev->_file_status == END_OF_FILE) {
658 printk("cx25821: EOF Channel 1 Framecount = %d\n",
659 dev->_frame_count);
660 return -1;
661 }
662 //ElSE, set the interrupt mask register, re-enable irq.
663 int_msk_tmp = cx_read(channel->int_msk);
664 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
665
666 return 0;
667 }
668
669 static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
670 {
671 struct cx25821_dev *dev = dev_id;
672 u32 msk_stat, vid_status;
673 int handled = 0;
674 int channel_num = 0;
675 struct sram_channel *sram_ch;
676
677 if (!dev)
678 return -1;
679
680 channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
681
682 sram_ch = &dev->sram_channels[channel_num];
683
684 msk_stat = cx_read(sram_ch->int_mstat);
685 vid_status = cx_read(sram_ch->int_stat);
686
687 // Only deal with our interrupt
688 if (vid_status) {
689 handled =
690 cx25821_video_upstream_irq(dev, channel_num, vid_status);
691 }
692
693 if (handled < 0) {
694 cx25821_stop_upstream_video_ch1(dev);
695 } else {
696 handled += handled;
697 }
698
699 return IRQ_RETVAL(handled);
700 }
701
702 void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch,
703 int pix_format)
704 {
705 int width = WIDTH_D1;
706 int height = dev->_lines_count;
707 int num_lines, odd_num_lines;
708 u32 value;
709 int vip_mode = OUTPUT_FRMT_656;
710
711 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
712 value &= 0xFFFFFFEF;
713 value |= dev->_isNTSC ? 0 : 0x10;
714 cx_write(ch->vid_fmt_ctl, value);
715
716 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
717 cx_write(ch->vid_active_ctl1, width);
718
719 num_lines = (height / 2) & 0x3FF;
720 odd_num_lines = num_lines;
721
722 if (dev->_isNTSC) {
723 odd_num_lines += 1;
724 }
725
726 value = (num_lines << 16) | odd_num_lines;
727
728 // set number of active lines in field 0 (top) and field 1 (bottom)
729 cx_write(ch->vid_active_ctl2, value);
730
731 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
732 }
733
734 int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
735 struct sram_channel *sram_ch)
736 {
737 u32 tmp = 0;
738 int err = 0;
739
740 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
741 tmp = cx_read(VID_CH_MODE_SEL);
742 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
743
744 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
745 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
746 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
747
748 /* reset counter */
749 cx_write(sram_ch->gpcnt_ctl, 3);
750
751 // Clear our bits from the interrupt status register.
752 cx_write(sram_ch->int_stat, _intr_msk);
753
754 //Set the interrupt mask register, enable irq.
755 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
756 tmp = cx_read(sram_ch->int_msk);
757 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
758
759 err =
760 request_irq(dev->pci->irq, cx25821_upstream_irq,
761 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
762 if (err < 0) {
763 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
764 dev->pci->irq);
765 goto fail_irq;
766 }
767
768 // Start the DMA engine
769 tmp = cx_read(sram_ch->dma_ctl);
770 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
771
772 dev->_is_running = 1;
773 dev->_is_first_frame = 1;
774
775 return 0;
776
777 fail_irq:
778 cx25821_dev_unregister(dev);
779 return err;
780 }
781
782 int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select,
783 int pixel_format)
784 {
785 struct sram_channel *sram_ch;
786 u32 tmp;
787 int retval = 0;
788 int err = 0;
789 int data_frame_size = 0;
790 int risc_buffer_size = 0;
791 int str_length = 0;
792
793 if (dev->_is_running) {
794 printk("Video Channel is still running so return!\n");
795 return 0;
796 }
797
798 dev->_channel_upstream_select = channel_select;
799 sram_ch = &dev->sram_channels[channel_select];
800
801 INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
802 dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
803
804 if (!dev->_irq_queues) {
805 printk
806 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
807 return -ENOMEM;
808 }
809 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
810 tmp = cx_read(VID_CH_MODE_SEL);
811 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
812
813 dev->_is_running = 0;
814 dev->_frame_count = 0;
815 dev->_file_status = RESET_STATUS;
816 dev->_lines_count = dev->_isNTSC ? 480 : 576;
817 dev->_pixel_format = pixel_format;
818 dev->_line_size =
819 (dev->_pixel_format ==
820 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
821 data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
822 risc_buffer_size =
823 dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
824
825 if (dev->input_filename) {
826 str_length = strlen(dev->input_filename);
827 dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL);
828
829 if (!dev->_filename)
830 goto error;
831
832 memcpy(dev->_filename, dev->input_filename, str_length + 1);
833 } else {
834 str_length = strlen(dev->_defaultname);
835 dev->_filename = (char *)kmalloc(str_length + 1, GFP_KERNEL);
836
837 if (!dev->_filename)
838 goto error;
839
840 memcpy(dev->_filename, dev->_defaultname, str_length + 1);
841 }
842
843 //Default if filename is empty string
844 if (strcmp(dev->input_filename, "") == 0) {
845 if (dev->_isNTSC) {
846 dev->_filename =
847 (dev->_pixel_format ==
848 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
849 "/root/vidtest.yuv";
850 } else {
851 dev->_filename =
852 (dev->_pixel_format ==
853 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
854 "/root/pal422.yuv";
855 }
856 }
857
858 dev->_is_running = 0;
859 dev->_frame_count = 0;
860 dev->_file_status = RESET_STATUS;
861 dev->_lines_count = dev->_isNTSC ? 480 : 576;
862 dev->_pixel_format = pixel_format;
863 dev->_line_size =
864 (dev->_pixel_format ==
865 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
866
867 retval =
868 cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size,
869 0);
870
871 /* setup fifo + format */
872 cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
873
874 dev->upstream_riscbuf_size = risc_buffer_size * 2;
875 dev->upstream_databuf_size = data_frame_size * 2;
876
877 //Allocating buffers and prepare RISC program
878 retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
879 if (retval < 0) {
880 printk(KERN_ERR
881 "%s: Failed to set up Video upstream buffers!\n",
882 dev->name);
883 goto error;
884 }
885
886 cx25821_start_video_dma_upstream(dev, sram_ch);
887
888 return 0;
889
890 error:
891 cx25821_dev_unregister(dev);
892
893 return err;
894 }
Verdex Pro support